Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13385131	14422	0	0
gen_assertions[0].RstEnOn_A	13385131	1004	0	0
gen_assertions[0].RstNOff_A	13385131	14422	0	0
gen_assertions[0].RstNOn_A	13385131	1004	0	0
gen_assertions[1].RstEnOff_A	53540381	13180	0	0
gen_assertions[1].RstEnOn_A	53540381	985	0	0
gen_assertions[1].RstNOff_A	53540381	13180	0	0
gen_assertions[1].RstNOn_A	53540381	985	0	0
gen_assertions[2].RstEnOff_A	26771067	13229	0	0
gen_assertions[2].RstEnOn_A	26771067	1013	0	0
gen_assertions[2].RstNOff_A	26771067	13229	0	0
gen_assertions[2].RstNOn_A	26771067	1013	0	0
gen_assertions[3].RstEnOff_A	26771131	13278	0	0
gen_assertions[3].RstEnOn_A	26771131	1057	0	0
gen_assertions[3].RstNOff_A	26771131	13278	0	0
gen_assertions[3].RstNOn_A	26771131	1057	0	0
gen_assertions[4].RstEnOff_A	1690295	22313	0	0
gen_assertions[4].RstEnOn_A	1690295	1098	0	0
gen_assertions[4].RstNOff_A	1690295	22313	0	0
gen_assertions[4].RstNOn_A	1690295	1098	0	0
gen_assertions[5].RstEnOff_A	13385131	14670	0	0
gen_assertions[5].RstEnOn_A	13385131	1132	0	0
gen_assertions[5].RstNOff_A	13385131	14670	0	0
gen_assertions[5].RstNOn_A	13385131	1132	0	0
gen_assertions[6].RstEnOff_A	13385131	14738	0	0
gen_assertions[6].RstEnOn_A	13385131	1190	0	0
gen_assertions[6].RstNOff_A	13385131	14738	0	0
gen_assertions[6].RstNOn_A	13385131	1190	0	0
gen_assertions[7].RstEnOff_A	13385131	14791	0	0
gen_assertions[7].RstEnOn_A	13385131	1254	0	0
gen_assertions[7].RstNOff_A	13385131	14791	0	0
gen_assertions[7].RstNOn_A	13385131	1254	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14422	0	0
T1	302151	265	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	72	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1004	0	0
T1	302151	22	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	11	0	0
T6	2458	0	0	0
T7	5551	4	0	0
T8	5822	0	0	0
T9	4233	3	0	0
T10	2040	0	0	0
T34	0	24	0	0
T37	0	1	0	0
T72	0	2	0	0
T73	0	7	0	0
T74	0	23	0	0
T75	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14422	0	0
T1	302151	265	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	72	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1004	0	0
T1	302151	22	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	11	0	0
T6	2458	0	0	0
T7	5551	4	0	0
T8	5822	0	0	0
T9	4233	3	0	0
T10	2040	0	0	0
T34	0	24	0	0
T37	0	1	0	0
T72	0	2	0	0
T73	0	7	0	0
T74	0	23	0	0
T75	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	13180	0	0
T1	120864	239	0	0
T2	120249	32	0	0
T3	84199	34	0	0
T4	14996	2	0	0
T5	238366	69	0	0
T6	9835	0	0	0
T7	22205	19	0	0
T8	23296	0	0	0
T9	16934	10	0	0
T10	8164	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	985	0	0
T1	120864	22	0	0
T2	120249	0	0	0
T3	84199	0	0	0
T4	14996	0	0	0
T5	238366	15	0	0
T6	9835	0	0	0
T7	22205	0	0	0
T8	23296	0	0	0
T9	16934	0	0	0
T10	8164	0	0	0
T34	0	30	0	0
T49	0	5	0	0
T50	0	1	0	0
T68	0	15	0	0
T72	0	3	0	0
T73	0	9	0	0
T74	0	26	0	0
T76	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	13180	0	0
T1	120864	239	0	0
T2	120249	32	0	0
T3	84199	34	0	0
T4	14996	2	0	0
T5	238366	69	0	0
T6	9835	0	0	0
T7	22205	19	0	0
T8	23296	0	0	0
T9	16934	10	0	0
T10	8164	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	985	0	0
T1	120864	22	0	0
T2	120249	0	0	0
T3	84199	0	0	0
T4	14996	0	0	0
T5	238366	15	0	0
T6	9835	0	0	0
T7	22205	0	0	0
T8	23296	0	0	0
T9	16934	0	0	0
T10	8164	0	0	0
T34	0	30	0	0
T49	0	5	0	0
T50	0	1	0	0
T68	0	15	0	0
T72	0	3	0	0
T73	0	9	0	0
T74	0	26	0	0
T76	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	13229	0	0
T1	604362	242	0	0
T2	60122	32	0	0
T3	42098	34	0	0
T4	7500	2	0	0
T5	119187	65	0	0
T6	4916	0	0	0
T7	11104	19	0	0
T8	11649	0	0	0
T9	8467	10	0	0
T10	4082	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	1013	0	0
T1	604362	26	0	0
T2	60122	0	0	0
T3	42098	0	0	0
T4	7500	0	0	0
T5	119187	11	0	0
T6	4916	0	0	0
T7	11104	0	0	0
T8	11649	0	0	0
T9	8467	0	0	0
T10	4082	0	0	0
T34	0	29	0	0
T49	0	7	0	0
T50	0	3	0	0
T51	0	11	0	0
T68	0	11	0	0
T73	0	9	0	0
T74	0	27	0	0
T76	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	13229	0	0
T1	604362	242	0	0
T2	60122	32	0	0
T3	42098	34	0	0
T4	7500	2	0	0
T5	119187	65	0	0
T6	4916	0	0	0
T7	11104	19	0	0
T8	11649	0	0	0
T9	8467	10	0	0
T10	4082	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	1013	0	0
T1	604362	26	0	0
T2	60122	0	0	0
T3	42098	0	0	0
T4	7500	0	0	0
T5	119187	11	0	0
T6	4916	0	0	0
T7	11104	0	0	0
T8	11649	0	0	0
T9	8467	0	0	0
T10	4082	0	0	0
T34	0	29	0	0
T49	0	7	0	0
T50	0	3	0	0
T51	0	11	0	0
T68	0	11	0	0
T73	0	9	0	0
T74	0	27	0	0
T76	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	13278	0	0
T1	604339	239	0	0
T2	60123	32	0	0
T3	42094	34	0	0
T4	7500	2	0	0
T5	119210	69	0	0
T6	4916	0	0	0
T7	11104	19	0	0
T8	11649	0	0	0
T9	8466	10	0	0
T10	4082	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	1057	0	0
T1	604339	24	0	0
T2	60123	0	0	0
T3	42094	0	0	0
T4	7500	0	0	0
T5	119210	15	0	0
T6	4916	0	0	0
T7	11104	0	0	0
T8	11649	0	0	0
T9	8466	0	0	0
T10	4082	0	0	0
T34	0	29	0	0
T37	0	1	0	0
T49	0	8	0	0
T50	0	4	0	0
T68	0	12	0	0
T73	0	8	0	0
T74	0	27	0	0
T76	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	13278	0	0
T1	604339	239	0	0
T2	60123	32	0	0
T3	42094	34	0	0
T4	7500	2	0	0
T5	119210	69	0	0
T6	4916	0	0	0
T7	11104	19	0	0
T8	11649	0	0	0
T9	8466	10	0	0
T10	4082	4	0	0
T11	0	71	0	0
T22	0	1	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	1057	0	0
T1	604339	24	0	0
T2	60123	0	0	0
T3	42094	0	0	0
T4	7500	0	0	0
T5	119210	15	0	0
T6	4916	0	0	0
T7	11104	0	0	0
T8	11649	0	0	0
T9	8466	0	0	0
T10	4082	0	0	0
T34	0	29	0	0
T37	0	1	0	0
T49	0	8	0	0
T50	0	4	0	0
T68	0	12	0	0
T73	0	8	0	0
T74	0	27	0	0
T76	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	22313	0	0
T1	38178	383	0	0
T2	3812	48	0	0
T3	2695	55	0	0
T4	467	6	0	0
T5	7494	96	0	0
T6	306	2	0	0
T7	692	20	0	0
T8	729	3	0	0
T9	528	11	0	0
T10	254	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	1098	0	0
T1	38178	24	0	0
T2	3812	0	0	0
T3	2695	0	0	0
T4	467	0	0	0
T5	7494	13	0	0
T6	306	0	0	0
T7	692	0	0	0
T8	729	0	0	0
T9	528	0	0	0
T10	254	0	0	0
T34	0	30	0	0
T49	0	9	0	0
T50	0	5	0	0
T51	0	11	0	0
T68	0	13	0	0
T73	0	7	0	0
T74	0	24	0	0
T76	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	22313	0	0
T1	38178	383	0	0
T2	3812	48	0	0
T3	2695	55	0	0
T4	467	6	0	0
T5	7494	96	0	0
T6	306	2	0	0
T7	692	20	0	0
T8	729	3	0	0
T9	528	11	0	0
T10	254	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	1098	0	0
T1	38178	24	0	0
T2	3812	0	0	0
T3	2695	0	0	0
T4	467	0	0	0
T5	7494	13	0	0
T6	306	0	0	0
T7	692	0	0	0
T8	729	0	0	0
T9	528	0	0	0
T10	254	0	0	0
T34	0	30	0	0
T49	0	9	0	0
T50	0	5	0	0
T51	0	11	0	0
T68	0	13	0	0
T73	0	7	0	0
T74	0	24	0	0
T76	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14670	0	0
T1	302151	269	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	72	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1132	0	0
T1	302151	25	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	11	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	29	0	0
T49	0	10	0	0
T50	0	6	0	0
T51	0	9	0	0
T68	0	8	0	0
T73	0	7	0	0
T74	0	22	0	0
T76	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14670	0	0
T1	302151	269	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	72	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1132	0	0
T1	302151	25	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	11	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	29	0	0
T49	0	10	0	0
T50	0	6	0	0
T51	0	9	0	0
T68	0	8	0	0
T73	0	7	0	0
T74	0	22	0	0
T76	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14738	0	0
T1	302151	270	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	77	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1190	0	0
T1	302151	25	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	16	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	27	0	0
T49	0	9	0	0
T50	0	7	0	0
T51	0	13	0	0
T68	0	12	0	0
T73	0	8	0	0
T74	0	24	0	0
T76	0	7	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14738	0	0
T1	302151	270	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	77	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1190	0	0
T1	302151	25	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	16	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	27	0	0
T49	0	9	0	0
T50	0	7	0	0
T51	0	13	0	0
T68	0	12	0	0
T73	0	8	0	0
T74	0	24	0	0
T76	0	7	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14791	0	0
T1	302151	265	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	70	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1254	0	0
T1	302151	21	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	9	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	28	0	0
T49	0	11	0	0
T50	0	8	0	0
T51	0	15	0	0
T68	0	9	0	0
T73	0	9	0	0
T74	0	23	0	0
T76	0	7	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	14791	0	0
T1	302151	265	0	0
T2	30065	32	0	0
T3	21045	36	0	0
T4	3748	4	0	0
T5	59596	70	0	0
T6	2458	0	0	0
T7	5551	19	0	0
T8	5822	0	0	0
T9	4233	10	0	0
T10	2040	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	1254	0	0
T1	302151	21	0	0
T2	30065	0	0	0
T3	21045	0	0	0
T4	3748	0	0	0
T5	59596	9	0	0
T6	2458	0	0	0
T7	5551	0	0	0
T8	5822	0	0	0
T9	4233	0	0	0
T10	2040	0	0	0
T34	0	28	0	0
T49	0	11	0	0
T50	0	8	0	0
T51	0	15	0	0
T68	0	9	0	0
T73	0	9	0	0
T74	0	23	0	0
T76	0	7	0	0