Unified Coverage Report :: Module :: rstmgr_leaf_rst

Module : rstmgr_leaf_rst

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_d0_spi_device	96.67	100.00	90.00			100.00
tb.dut.u_d0_spi_host0	96.67	100.00	90.00			100.00
tb.dut.u_d0_spi_host1	96.67	100.00	90.00			100.00
tb.dut.u_d0_usb	96.67	100.00	90.00			100.00
tb.dut.u_d0_i2c0	96.67	100.00	90.00			100.00
tb.dut.u_d0_i2c1	96.67	100.00	90.00			100.00
tb.dut.u_d0_i2c2	96.67	100.00	90.00			100.00
tb.dut.u_daon_por	100.00		100.00
tb.dut.u_daon_por_io	100.00		100.00
tb.dut.u_daon_por_io_div2	100.00		100.00
tb.dut.u_daon_por_io_div4	100.00		100.00
tb.dut.u_daon_por_usb	100.00		100.00
tb.dut.u_daon_lc	100.00		100.00
tb.dut.u_d0_lc	100.00		100.00
tb.dut.u_daon_lc_shadowed	100.00		100.00
tb.dut.u_d0_lc_shadowed	100.00		100.00
tb.dut.u_daon_lc_aon	100.00		100.00
tb.dut.u_daon_lc_io	100.00		100.00
tb.dut.u_d0_lc_io	100.00		100.00
tb.dut.u_daon_lc_io_div2	100.00		100.00
tb.dut.u_d0_lc_io_div2	100.00		100.00
tb.dut.u_daon_lc_usb	100.00		100.00
tb.dut.u_d0_lc_usb	100.00		100.00
tb.dut.u_d0_sys	100.00		100.00
tb.dut.u_daon_sys_io_div4	100.00		100.00
tb.dut.u_d0_usb_aon	100.00	100.00	100.00			100.00
tb.dut.u_daon_lc_io_div4
tb.dut.u_d0_lc_io_div4
tb.dut.u_daon_lc_io_div4_shadowed
tb.dut.u_d0_lc_io_div4_shadowed

---

Module Instance : tb.dut.u_d0_spi_device

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_usb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	90.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.29	100.00	96.43	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por_io

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por_io_div2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por_io_div4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por_usb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.47	100.00	100.00	82.35		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	82.35			82.35
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_io

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_io

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_usb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_usb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_sys

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_usb_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rst_chk.u_prim_rst_sync	100.00	100.00	100.00			100.00	100.00
gen_rst_chk.u_rst_chk	100.00			100.00
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_mubi4_sender	100.00	100.00				100.00	100.00
u_rst_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00
u_scanmode_sync	100.00	100.00					100.00

Line Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Line Coverage for Module self-instances :

SCORE	LINE
96.67	100.00

tb.dut.u_d0_spi_device

SCORE	LINE
96.67	100.00

tb.dut.u_d0_spi_host0

SCORE	LINE
96.67	100.00

tb.dut.u_d0_spi_host1

SCORE	LINE
96.67	100.00

tb.dut.u_d0_usb

SCORE	LINE
100.00	100.00

tb.dut.u_d0_usb_aon

SCORE	LINE
96.67	100.00

tb.dut.u_d0_i2c0

SCORE	LINE
96.67	100.00

tb.dut.u_d0_i2c1

SCORE	LINE
96.67	100.00

tb.dut.u_d0_i2c2

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=1 )
Cond Coverage for Module self-instances :

SCORE	COND
96.67	90.00

tb.dut.u_d0_spi_device

SCORE	COND
96.67	90.00

tb.dut.u_d0_spi_host0

SCORE	COND
96.67	90.00

tb.dut.u_d0_spi_host1

SCORE	COND
96.67	90.00

tb.dut.u_d0_usb

SCORE	COND
100.00	100.00

tb.dut.u_d0_usb_aon

SCORE	COND
96.67	90.00

tb.dut.u_d0_i2c0

SCORE	COND
96.67	90.00

tb.dut.u_d0_i2c1

SCORE	COND
96.67	90.00

tb.dut.u_d0_i2c2

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T9

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T9
1	1	1	Covered	T1,T5,T7

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T34,T74,T76

---

Cond Coverage for Module : rstmgr_leaf_rst ( parameter SecCheck=1,SecMaxSyncDelay=2,SwRstReq=0 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_daon_por

SCORE	COND
100.00	100.00

tb.dut.u_daon_por_io

SCORE	COND
100.00	100.00

tb.dut.u_daon_por_io_div2

SCORE	COND
100.00	100.00

tb.dut.u_daon_por_io_div4

SCORE	COND
100.00	100.00

tb.dut.u_daon_por_usb

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc

SCORE	COND
100.00	100.00

tb.dut.u_d0_lc

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc_shadowed

SCORE	COND
100.00	100.00

tb.dut.u_d0_lc_shadowed

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc_aon

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc_io

SCORE	COND
100.00	100.00

tb.dut.u_d0_lc_io

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc_io_div2

SCORE	COND
100.00	100.00

tb.dut.u_d0_lc_io_div2

SCORE	COND
100.00	100.00

tb.dut.u_daon_lc_usb

SCORE	COND
100.00	100.00

tb.dut.u_d0_lc_usb

SCORE	COND
100.00	100.00

tb.dut.u_d0_sys

SCORE	COND
100.00	100.00

tb.dut.u_daon_sys_io_div4

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

---

Branch Coverage for Module : rstmgr_leaf_rst

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T9
0	0	1	Covered	T1,T5,T7
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_device

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_spi_device

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T9
1	0	Covered	T1,T5,T7
1	1	Covered	T1,T5,T9

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T7
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T9
1	1	1	Covered	T1,T5,T7

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_spi_device

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T9
0	0	1	Covered	T1,T5,T7
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host0

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host0

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host0

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_spi_host1

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_spi_host1

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_spi_host1

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_usb

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_usb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T34
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_usb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c0

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_i2c0

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_i2c0

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c1

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_i2c1

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T11
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_i2c1

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_d0_i2c2

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_i2c2

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T23
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Not Covered

---

Branch Coverage for Instance : tb.dut.u_d0_i2c2

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3

Cond Coverage for Instance : tb.dut.u_daon_por

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_por_io

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_por_usb

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_lc

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc_aon

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc_io

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_lc_io

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_lc_usb

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_lc_usb

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_d0_sys

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

Line Coverage for Instance : tb.dut.u_d0_usb_aon

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_d0_usb_aon

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       70
 EXPRESSION (sw_rst_req_q && clr_sw_rst_req)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T23
1	0	Covered	T1,T5,T34
1	1	Covered	T1,T5,T34

 LINE       72
 EXPRESSION (((!sw_rst_req_q)) && ((!sw_rst_req_ni)) && ((!clr_sw_rst_req)))
             --------1--------    ---------2--------    ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T5,T34
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T34
1	1	1	Covered	T1,T5,T34

 LINE       104
 EXPRESSION (sw_rst_req_q | ((~sw_rst_req_ni)))
             ------1-----   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T34
1	0	Covered	T34,T74,T76

---

Branch Coverage for Instance : tb.dut.u_d0_usb_aon

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	68	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_leaf_rst.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((sw_rst_req_q && clr_sw_rst_req))
-3-:	72	if ((((!sw_rst_req_q) && (!sw_rst_req_ni)) && (!clr_sw_rst_req)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T34
0	0	1	Covered	T1,T5,T34
0	0	0	Covered	T1,T2,T3