Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12644123	6969	0	0
alert_regwen_rd_A	12644123	4511	0	0
cpu_regwen_rd_A	12644123	4796	0	0
sw_rst_ctrl_n_0_rd_A	12644123	9612	0	0
sw_rst_ctrl_n_1_rd_A	12644123	9290	0	0
sw_rst_ctrl_n_2_rd_A	12644123	9494	0	0
sw_rst_ctrl_n_3_rd_A	12644123	9339	0	0
sw_rst_ctrl_n_4_rd_A	12644123	9716	0	0
sw_rst_ctrl_n_5_rd_A	12644123	9526	0	0
sw_rst_ctrl_n_6_rd_A	12644123	9455	0	0
sw_rst_ctrl_n_7_rd_A	12644123	9678	0	0
sw_rst_regwen_0_rd_A	12644123	5502	0	0
sw_rst_regwen_1_rd_A	12644123	5501	0	0
sw_rst_regwen_2_rd_A	12644123	5450	0	0
sw_rst_regwen_3_rd_A	12644123	5577	0	0
sw_rst_regwen_4_rd_A	12644123	5358	0	0
sw_rst_regwen_5_rd_A	12644123	5426	0	0
sw_rst_regwen_6_rd_A	12644123	5503	0	0
sw_rst_regwen_7_rd_A	12644123	5466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	6969	0	0
T54	19841	2	0	0
T55	9723	2	0	0
T56	5117	143	0	0
T57	2632	146	0	0
T58	7075	213	0	0
T63	21999	4	0	0
T77	3817	311	0	0
T78	4323	198	0	0
T79	4378	22	0	0
T80	2614	130	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	4511	0	0
T1	270175	410	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	144	0	0
T38	0	67	0	0
T73	0	311	0	0
T84	0	188	0	0
T104	0	75	0	0
T105	0	21	0	0
T106	0	259	0	0
T107	0	195	0	0
T108	0	27	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	4796	0	0
T1	270175	361	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	134	0	0
T38	0	62	0	0
T73	0	306	0	0
T84	0	254	0	0
T104	0	76	0	0
T105	0	43	0	0
T106	0	286	0	0
T107	0	224	0	0
T108	0	32	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9612	0	0
T1	270175	688	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	37	0	0
T10	1712	0	0	0
T33	0	113	0	0
T38	0	43	0	0
T51	0	229	0	0
T73	0	425	0	0
T84	0	266	0	0
T109	0	10	0	0
T110	0	123	0	0
T111	0	107	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9290	0	0
T1	270175	672	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	19	0	0
T10	1712	0	0	0
T33	0	157	0	0
T38	0	29	0	0
T51	0	215	0	0
T73	0	326	0	0
T84	0	256	0	0
T109	0	9	0	0
T110	0	137	0	0
T111	0	166	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9494	0	0
T1	270175	710	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	16	0	0
T10	1712	0	0	0
T33	0	140	0	0
T38	0	44	0	0
T51	0	235	0	0
T73	0	365	0	0
T84	0	266	0	0
T109	0	8	0	0
T110	0	125	0	0
T111	0	135	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9339	0	0
T1	270175	666	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	26	0	0
T10	1712	0	0	0
T33	0	100	0	0
T38	0	40	0	0
T51	0	193	0	0
T73	0	350	0	0
T84	0	234	0	0
T109	0	12	0	0
T110	0	151	0	0
T111	0	164	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9716	0	0
T1	270175	605	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	21	0	0
T10	1712	0	0	0
T33	0	129	0	0
T38	0	60	0	0
T51	0	213	0	0
T73	0	370	0	0
T84	0	225	0	0
T109	0	13	0	0
T110	0	161	0	0
T111	0	126	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9526	0	0
T1	270175	649	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	18	0	0
T10	1712	0	0	0
T33	0	138	0	0
T38	0	72	0	0
T51	0	234	0	0
T73	0	351	0	0
T84	0	248	0	0
T109	0	18	0	0
T110	0	157	0	0
T111	0	119	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9455	0	0
T1	270175	657	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	34	0	0
T10	1712	0	0	0
T33	0	119	0	0
T38	0	58	0	0
T51	0	230	0	0
T73	0	340	0	0
T84	0	271	0	0
T109	0	12	0	0
T110	0	112	0	0
T111	0	109	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	9678	0	0
T1	270175	671	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	31	0	0
T10	1712	0	0	0
T33	0	110	0	0
T38	0	53	0	0
T51	0	190	0	0
T73	0	388	0	0
T84	0	277	0	0
T109	0	7	0	0
T110	0	109	0	0
T111	0	119	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5502	0	0
T1	270175	388	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	122	0	0
T38	0	50	0	0
T51	0	27	0	0
T73	0	330	0	0
T84	0	225	0	0
T104	0	69	0	0
T110	0	33	0	0
T111	0	32	0	0
T112	0	39	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5501	0	0
T1	270175	342	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	134	0	0
T38	0	39	0	0
T51	0	28	0	0
T73	0	326	0	0
T84	0	206	0	0
T104	0	68	0	0
T110	0	21	0	0
T111	0	25	0	0
T112	0	21	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5450	0	0
T1	270175	366	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	128	0	0
T38	0	50	0	0
T51	0	25	0	0
T73	0	278	0	0
T84	0	235	0	0
T104	0	66	0	0
T110	0	16	0	0
T111	0	32	0	0
T112	0	24	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5577	0	0
T1	270175	378	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	130	0	0
T38	0	51	0	0
T51	0	23	0	0
T73	0	369	0	0
T84	0	229	0	0
T104	0	67	0	0
T110	0	18	0	0
T111	0	27	0	0
T112	0	38	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5358	0	0
T1	270175	350	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	105	0	0
T38	0	63	0	0
T51	0	45	0	0
T73	0	316	0	0
T84	0	271	0	0
T104	0	88	0	0
T110	0	25	0	0
T111	0	32	0	0
T112	0	36	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5426	0	0
T1	270175	395	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	112	0	0
T38	0	50	0	0
T51	0	25	0	0
T73	0	281	0	0
T84	0	252	0	0
T104	0	100	0	0
T110	0	19	0	0
T111	0	44	0	0
T112	0	20	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5503	0	0
T1	270175	370	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	139	0	0
T38	0	60	0	0
T51	0	42	0	0
T73	0	302	0	0
T84	0	215	0	0
T104	0	68	0	0
T110	0	24	0	0
T111	0	34	0	0
T112	0	33	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12644123	5466	0	0
T1	270175	398	0	0
T2	25686	0	0	0
T3	16515	0	0	0
T4	3507	0	0	0
T5	52954	0	0	0
T6	2344	0	0	0
T7	4375	0	0	0
T8	5663	0	0	0
T9	3371	0	0	0
T10	1712	0	0	0
T33	0	96	0	0
T38	0	55	0	0
T51	0	38	0	0
T73	0	285	0	0
T84	0	218	0	0
T104	0	48	0	0
T110	0	8	0	0
T111	0	38	0	0
T112	0	24	0	0