RSTMGR Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.600s	257.941us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.940s	128.158us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	8.750s	2.030ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.590s	427.193us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.850s	189.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
		rstmgr_csr_aliasing	2.590s	427.193us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.980s	207.202us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	2.780s	535.905us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.610s	283.072us	50	50	100.00
V2	reset_info	rstmgr_reset	8.700s	2.485ms	50	50	100.00
V2	cpu_info	rstmgr_reset	8.700s	2.485ms	50	50	100.00
V2	alert_info	rstmgr_reset	8.700s	2.485ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	8.700s	2.485ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	51.290s	14.558ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.920s	109.995us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.690s	481.151us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.690s	481.151us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.940s	128.158us	5	5	100.00
		rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
		rstmgr_csr_aliasing	2.590s	427.193us	5	5	100.00
		rstmgr_same_csr_outstanding	1.650s	255.083us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.940s	128.158us	5	5	100.00
		rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
		rstmgr_csr_aliasing	2.590s	427.193us	5	5	100.00
		rstmgr_same_csr_outstanding	1.650s	255.083us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	28.800s	16.514ms	5	5	100.00
		rstmgr_tl_intg_err	3.610s	1.307ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	28.800s	16.514ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	28.800s	16.514ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.610s	1.307ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.310s	167.622us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	9.620s	2.381ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.180s	244.662us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	28.800s	16.514ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.930s	89.856us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.44	99.40	99.31	99.87	--	99.83	99.46	98.77

Past Results

• Latest
• rstmgr_cnsty_chk
• lint
• 2024.08.18_08.56.44
• 2024.08.17_07.39.50
• 2024.08.16_08.55.12
• 2024.08.15_05.55.38
• 2024.08.14_08.59.52