Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	574463	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

349387

1

T1

245

T2

23

T3

360

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	491468	1			T1	355		T2	27		T3	491
values[0x0]	215818	1			T1	157		T2	17		T3	230
values[0x1]	216564	1			T1	152		T2	13		T3	215

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	482371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

441479

1

T1

316

T2

29

T3

440

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2586	1			T1	4		T5	2		T8	11
valid_sources[0x01]	3261	1			T5	2		T8	14		T11	7
valid_sources[0x02]	3278	1			T5	2		T8	16		T11	8
valid_sources[0x03]	3773	1			T5	1		T8	11		T10	10
valid_sources[0x04]	6158	1			T1	6		T5	6		T8	10
valid_sources[0x05]	5139	1			T5	5		T8	6		T11	4
valid_sources[0x06]	2726	1			T5	3		T8	18		T11	8
valid_sources[0x07]	7141	1			T1	9		T5	6		T8	13
valid_sources[0x08]	6365	1			T1	11		T5	2		T8	15
valid_sources[0x09]	6051	1			T2	6		T5	3		T8	1
valid_sources[0x0a]	3076	1			T1	1		T5	2		T8	17
valid_sources[0x0b]	3213	1			T5	3		T8	18		T11	14
valid_sources[0x0c]	3027	1			T1	4		T5	6		T8	8
valid_sources[0x0d]	6293	1			T1	3		T5	9		T8	7
valid_sources[0x0e]	3327	1			T1	1		T5	7		T8	14
valid_sources[0x0f]	4048	1			T1	6		T5	5		T8	18
valid_sources[0x10]	4322	1			T1	5		T5	4		T8	22
valid_sources[0x11]	3213	1			T1	6		T5	5		T8	16
valid_sources[0x12]	3736	1			T1	14		T5	8		T8	23
valid_sources[0x13]	3022	1			T1	4		T5	10		T8	8
valid_sources[0x14]	3468	1			T1	1		T5	4		T8	8
valid_sources[0x15]	4599	1			T1	5		T5	3		T8	4
valid_sources[0x16]	2768	1			T5	2		T8	29		T11	7
valid_sources[0x17]	3407	1			T1	1		T5	9		T8	7
valid_sources[0x18]	3533	1			T1	6		T5	2		T8	5
valid_sources[0x19]	6119	1			T1	1		T2	2		T5	4
valid_sources[0x1a]	3088	1			T1	1		T5	8		T8	7
valid_sources[0x1b]	2986	1			T5	5		T8	9		T11	8
valid_sources[0x1c]	3490	1			T5	1		T8	17		T11	10
valid_sources[0x1d]	2837	1			T1	1		T5	1		T8	16
valid_sources[0x1e]	3620	1			T5	2		T8	2		T10	8
valid_sources[0x1f]	3892	1			T5	4		T8	13		T10	9
valid_sources[0x20]	3436	1			T8	16		T11	9		T12	18
valid_sources[0x21]	5834	1			T1	2		T5	1		T8	29
valid_sources[0x22]	3001	1			T5	4		T8	7		T11	8
valid_sources[0x23]	2518	1			T1	5		T5	1		T8	12
valid_sources[0x24]	3481	1			T1	5		T5	8		T8	3
valid_sources[0x25]	3556	1			T1	4		T2	4		T5	2
valid_sources[0x26]	3670	1			T5	3		T8	6		T11	6
valid_sources[0x27]	3548	1			T1	3		T5	1		T8	11
valid_sources[0x28]	2957	1			T5	3		T8	17		T11	12
valid_sources[0x29]	3888	1			T1	2		T5	3		T8	13
valid_sources[0x2a]	2848	1			T5	4		T8	5		T11	13
valid_sources[0x2b]	2951	1			T1	6		T5	4		T8	8
valid_sources[0x2c]	3467	1			T1	2		T5	6		T8	19
valid_sources[0x2d]	6219	1			T1	11		T5	5		T8	15
valid_sources[0x2e]	2586	1			T8	8		T11	10		T12	16
valid_sources[0x2f]	3875	1			T1	3		T2	1		T5	1
valid_sources[0x30]	3489	1			T1	1		T5	2		T7	70
valid_sources[0x31]	3591	1			T1	1		T5	1		T8	14
valid_sources[0x32]	3292	1			T1	3		T5	1		T8	17
valid_sources[0x33]	3329	1			T1	3		T5	3		T8	6
valid_sources[0x34]	3091	1			T1	17		T2	3		T5	2
valid_sources[0x35]	2838	1			T1	6		T5	5		T8	16
valid_sources[0x36]	6394	1			T1	4		T5	1		T8	3
valid_sources[0x37]	3581	1			T1	1		T5	4		T8	13
valid_sources[0x38]	4164	1			T1	3		T5	1		T8	9
valid_sources[0x39]	3561	1			T5	2		T8	19		T11	4
valid_sources[0x3a]	2936	1			T8	8		T11	9		T12	20
valid_sources[0x3b]	3085	1			T5	6		T8	15		T11	9
valid_sources[0x3c]	3277	1			T5	6		T8	12		T11	10
valid_sources[0x3d]	3178	1			T1	3		T5	2		T8	8
valid_sources[0x3e]	3964	1			T5	2		T8	11		T11	4
valid_sources[0x3f]	3025	1			T1	2		T4	4		T5	3
valid_sources[0x40]	3080	1			T1	3		T7	66		T8	21
valid_sources[0x41]	4282	1			T8	12		T11	8		T12	7
valid_sources[0x42]	2658	1			T5	5		T8	1		T11	9
valid_sources[0x43]	4274	1			T1	5		T5	4		T8	11
valid_sources[0x44]	3152	1			T5	3		T8	12		T11	13
valid_sources[0x45]	4739	1			T1	3		T5	1		T8	22
valid_sources[0x46]	3314	1			T8	4		T11	5		T12	10
valid_sources[0x47]	4870	1			T1	10		T5	4		T8	29
valid_sources[0x48]	3321	1			T1	1		T5	1		T8	20
valid_sources[0x49]	3187	1			T1	12		T5	4		T8	13
valid_sources[0x4a]	3367	1			T5	7		T8	22		T11	5
valid_sources[0x4b]	4232	1			T1	4		T5	1		T8	20
valid_sources[0x4c]	6341	1			T8	13		T11	9		T12	5
valid_sources[0x4d]	3101	1			T1	4		T5	1		T8	9
valid_sources[0x4e]	3542	1			T1	7		T5	3		T8	7
valid_sources[0x4f]	4292	1			T5	3		T8	3		T11	11
valid_sources[0x50]	3899	1			T5	2		T8	10		T11	12
valid_sources[0x51]	2758	1			T1	3		T5	3		T8	14
valid_sources[0x52]	3447	1			T5	5		T8	7		T11	10
valid_sources[0x53]	3247	1			T1	1		T5	2		T8	17
valid_sources[0x54]	3162	1			T8	14		T11	9		T12	6
valid_sources[0x55]	2658	1			T5	5		T8	10		T11	9
valid_sources[0x56]	2819	1			T1	4		T5	4		T8	13
valid_sources[0x57]	3093	1			T1	7		T5	3		T8	13
valid_sources[0x58]	2660	1			T1	9		T5	1		T8	10
valid_sources[0x59]	2827	1			T1	1		T5	3		T8	12
valid_sources[0x5a]	4551	1			T5	2		T8	8		T11	6
valid_sources[0x5b]	2833	1			T5	1		T8	23		T11	13
valid_sources[0x5c]	3829	1			T1	9		T5	3		T8	4
valid_sources[0x5d]	3433	1			T5	2		T8	16		T11	8
valid_sources[0x5e]	3111	1			T5	5		T8	13		T11	14
valid_sources[0x5f]	3552	1			T1	2		T5	2		T8	22
valid_sources[0x60]	3076	1			T1	2		T5	5		T8	7
valid_sources[0x61]	3224	1			T5	2		T8	4		T11	6
valid_sources[0x62]	3325	1			T5	6		T8	13		T11	10
valid_sources[0x63]	3307	1			T1	1		T2	2		T5	1
valid_sources[0x64]	2714	1			T5	2		T8	17		T11	13
valid_sources[0x65]	3409	1			T1	1		T5	4		T8	9
valid_sources[0x66]	2693	1			T5	2		T8	7		T11	5
valid_sources[0x67]	3022	1			T5	3		T8	31		T11	5
valid_sources[0x68]	3278	1			T1	10		T5	3		T8	9
valid_sources[0x69]	4074	1			T5	3		T8	1		T11	10
valid_sources[0x6a]	3259	1			T5	4		T8	15		T11	9
valid_sources[0x6b]	3314	1			T1	2		T5	5		T8	14
valid_sources[0x6c]	3305	1			T5	2		T8	21		T11	8
valid_sources[0x6d]	3234	1			T1	18		T5	1		T8	16
valid_sources[0x6e]	3123	1			T5	5		T8	21		T11	4
valid_sources[0x6f]	3006	1			T5	3		T8	7		T11	9
valid_sources[0x70]	3949	1			T1	1		T5	3		T8	7
valid_sources[0x71]	3151	1			T1	12		T8	20		T11	12
valid_sources[0x72]	3041	1			T5	3		T8	9		T11	7
valid_sources[0x73]	3212	1			T5	2		T8	14		T11	6
valid_sources[0x74]	3012	1			T5	5		T8	4		T11	4
valid_sources[0x75]	3246	1			T5	4		T8	6		T11	9
valid_sources[0x76]	2588	1			T1	2		T5	1		T8	5
valid_sources[0x77]	4130	1			T1	1		T5	2		T8	10
valid_sources[0x78]	6573	1			T5	5		T8	8		T11	4
valid_sources[0x79]	3337	1			T1	2		T2	3		T5	7
valid_sources[0x7a]	4159	1			T1	3		T5	1		T8	12
valid_sources[0x7b]	2862	1			T5	1		T8	6		T10	3
valid_sources[0x7c]	2995	1			T1	2		T5	3		T8	10
valid_sources[0x7d]	2944	1			T8	24		T11	7		T12	1
valid_sources[0x7e]	2842	1			T1	4		T5	5		T8	17
valid_sources[0x7f]	6593	1			T1	5		T8	9		T11	7
valid_sources[0x80]	3770	1			T5	5		T8	15		T11	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

231448

1

T1

168

T2

15

T3

248

values[0x0]

all_enables

biggest_size

76279

1

T1

49

T2

4

T3

80

values[0x1]

all_enables

biggest_size

41660

1

T1

28

T2

4

T3

32