Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T8,T9

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11053861	12216	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11053861	112594	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11053861	6421719	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11053861	180007	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11053861	12216	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11053861	112594	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11053861	6421719	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11053861	180007	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	12216	0	0
T2	1770	3	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	12	0	0
T8	42162	75	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0
T14	0	4	0	0
T15	0	9	0	0
T16	0	4	0	0
T17	0	75	0	0
T18	173195	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	112594	0	0
T2	1770	27	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	108	0	0
T8	42162	719	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	245	0	0
T12	0	704	0	0
T13	0	323	0	0
T14	0	38	0	0
T15	0	81	0	0
T16	0	37	0	0
T17	0	678	0	0
T18	173195	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	6421719	0	0
T1	7432	6818	0	0
T2	1770	1107	0	0
T3	3113	2500	0	0
T4	1878	1313	0	0
T5	9356	8761	0	0
T6	5104	578	0	0
T7	2121	1383	0	0
T8	42162	24814	0	0
T9	5073	563	0	0
T10	6078	5499	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	180007	0	0
T2	1770	39	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	166	0	0
T8	42162	1127	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	419	0	0
T12	0	1102	0	0
T13	0	510	0	0
T14	0	59	0	0
T15	0	139	0	0
T16	0	66	0	0
T17	0	1077	0	0
T18	173195	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	12216	0	0
T2	1770	3	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	12	0	0
T8	42162	75	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0
T14	0	4	0	0
T15	0	9	0	0
T16	0	4	0	0
T17	0	75	0	0
T18	173195	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	112594	0	0
T2	1770	27	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	108	0	0
T8	42162	719	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	245	0	0
T12	0	704	0	0
T13	0	323	0	0
T14	0	38	0	0
T15	0	81	0	0
T16	0	37	0	0
T17	0	678	0	0
T18	173195	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	6421719	0	0
T1	7432	6818	0	0
T2	1770	1107	0	0
T3	3113	2500	0	0
T4	1878	1313	0	0
T5	9356	8761	0	0
T6	5104	578	0	0
T7	2121	1383	0	0
T8	42162	24814	0	0
T9	5073	563	0	0
T10	6078	5499	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	180007	0	0
T2	1770	39	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	0	0	0
T6	5104	0	0	0
T7	2121	166	0	0
T8	42162	1127	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T11	0	419	0	0
T12	0	1102	0	0
T13	0	510	0	0
T14	0	59	0	0
T15	0	139	0	0
T16	0	66	0	0
T17	0	1077	0	0
T18	173195	0	0	0