Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T14
0	1	Covered	T11,T13,T14
1	0	Covered	T11,T13,T17

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T11,T13,T14
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51757947	8452	0	0
CascadeEffAonToRstPorAboveRise_A	51757947	8452	0	0
CascadeEffAonToRstPorIoAboveFall_A	49684909	8452	0	0
CascadeEffAonToRstPorIoAboveRise_A	49684909	8452	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24843413	8452	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24843413	8452	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12421546	8452	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12421546	8452	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24843561	8452	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24843561	8452	0	0
CascadeLcToLcAboveFall_A	51757947	20668	0	0
CascadeLcToLcAboveRise_A	51757947	20668	0	0
CascadeLcToLcAonAboveFall_A	1568189	20668	0	0
CascadeLcToLcAonAboveRise_A	1568189	20668	0	0
CascadeLcToLcShadowedAboveFall_A	51757947	20668	0	0
CascadeLcToLcShadowedAboveRise_A	51757947	20668	0	0
CascadePorToAonAboveFall_A	1568189	6885	0	0
CascadeSysToSysAboveFall_A	51757947	20668	0	0
CascadeSysToSysAboveRise_A	51757947	20668	0	0
ScanRstToAonRise_A	1568189	227	0	0
StablePorToAonRise_A	1568189	8452	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11053861	20668	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11053861	20668	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11053861	20668	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11053861	20668	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12421546	20668	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12421546	20668	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11053861	20668	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11053861	20668	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11053861	20668	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11053861	20668	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	8452	0	0
T1	31149	1	0	0
T2	8613	1	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	1	0	0
T8	189115	27	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	8452	0	0
T1	31149	1	0	0
T2	8613	1	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	1	0	0
T8	189115	27	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	8452	0	0
T1	29901	1	0	0
T2	8269	1	0	0
T3	12626	1	0	0
T4	7876	1	0	0
T5	37692	1	0	0
T6	23364	8	0	0
T7	11679	1	0	0
T8	181562	27	0	0
T9	23238	8	0	0
T10	24677	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	8452	0	0
T1	29901	1	0	0
T2	8269	1	0	0
T3	12626	1	0	0
T4	7876	1	0	0
T5	37692	1	0	0
T6	23364	8	0	0
T7	11679	1	0	0
T8	181562	27	0	0
T9	23238	8	0	0
T10	24677	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	8452	0	0
T1	14951	1	0	0
T2	4133	1	0	0
T3	6312	1	0	0
T4	3937	1	0	0
T5	18846	1	0	0
T6	11680	8	0	0
T7	5839	1	0	0
T8	90771	27	0	0
T9	11621	8	0	0
T10	12338	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	8452	0	0
T1	14951	1	0	0
T2	4133	1	0	0
T3	6312	1	0	0
T4	3937	1	0	0
T5	18846	1	0	0
T6	11680	8	0	0
T7	5839	1	0	0
T8	90771	27	0	0
T9	11621	8	0	0
T10	12338	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	8452	0	0
T1	7474	1	0	0
T2	2066	1	0	0
T3	3156	1	0	0
T4	1969	1	0	0
T5	9423	1	0	0
T6	5838	8	0	0
T7	2918	1	0	0
T8	45394	27	0	0
T9	5810	8	0	0
T10	6168	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	8452	0	0
T1	7474	1	0	0
T2	2066	1	0	0
T3	3156	1	0	0
T4	1969	1	0	0
T5	9423	1	0	0
T6	5838	8	0	0
T7	2918	1	0	0
T8	45394	27	0	0
T9	5810	8	0	0
T10	6168	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	8452	0	0
T1	14951	1	0	0
T2	4134	1	0	0
T3	6312	1	0	0
T4	3937	1	0	0
T5	18847	1	0	0
T6	11683	8	0	0
T7	5839	1	0	0
T8	90798	27	0	0
T9	11611	8	0	0
T10	12338	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	8452	0	0
T1	14951	1	0	0
T2	4134	1	0	0
T3	6312	1	0	0
T4	3937	1	0	0
T5	18847	1	0	0
T6	11683	8	0	0
T7	5839	1	0	0
T8	90798	27	0	0
T9	11611	8	0	0
T10	12338	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	20668	0	0
T1	934	1	0	0
T2	257	4	0	0
T3	394	1	0	0
T4	246	1	0	0
T5	1177	1	0	0
T6	731	8	0	0
T7	364	13	0	0
T8	5688	102	0	0
T9	729	8	0	0
T10	769	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	20668	0	0
T1	934	1	0	0
T2	257	4	0	0
T3	394	1	0	0
T4	246	1	0	0
T5	1177	1	0	0
T6	731	8	0	0
T7	364	13	0	0
T8	5688	102	0	0
T9	729	8	0	0
T10	769	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	6885	0	0
T1	934	1	0	0
T2	257	1	0	0
T3	394	1	0	0
T4	246	1	0	0
T5	1177	1	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	5688	27	0	0
T9	729	8	0	0
T10	769	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51757947	20668	0	0
T1	31149	1	0	0
T2	8613	4	0	0
T3	13152	1	0	0
T4	8205	1	0	0
T5	39263	1	0	0
T6	24348	8	0	0
T7	12166	13	0	0
T8	189115	102	0	0
T9	24202	8	0	0
T10	25707	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	227	0	0
T14	362	1	0	0
T15	390	0	0	0
T16	505	0	0	0
T17	5881	2	0	0
T19	234	0	0	0
T30	0	2	0	0
T33	0	3	0	0
T35	0	2	0	0
T45	408	0	0	0
T46	1094	0	0	0
T47	467	0	0	0
T48	729	0	0	0
T81	730	0	0	0
T88	0	6	0	0
T90	0	2	0	0
T94	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	8452	0	0
T1	934	1	0	0
T2	257	1	0	0
T3	394	1	0	0
T4	246	1	0	0
T5	1177	1	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	5688	27	0	0
T9	729	8	0	0
T10	769	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	20668	0	0
T1	7474	1	0	0
T2	2066	4	0	0
T3	3156	1	0	0
T4	1969	1	0	0
T5	9423	1	0	0
T6	5838	8	0	0
T7	2918	13	0	0
T8	45394	102	0	0
T9	5810	8	0	0
T10	6168	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	20668	0	0
T1	7474	1	0	0
T2	2066	4	0	0
T3	3156	1	0	0
T4	1969	1	0	0
T5	9423	1	0	0
T6	5838	8	0	0
T7	2918	13	0	0
T8	45394	102	0	0
T9	5810	8	0	0
T10	6168	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11053861	20668	0	0
T1	7432	1	0	0
T2	1770	4	0	0
T3	3113	1	0	0
T4	1878	1	0	0
T5	9356	1	0	0
T6	5104	8	0	0
T7	2121	13	0	0
T8	42162	102	0	0
T9	5073	8	0	0
T10	6078	1	0	0