Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T6,T7

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12421546	13008	0	0
gen_assertions[0].RstEnOn_A	12421546	963	0	0
gen_assertions[0].RstNOff_A	12421546	13008	0	0
gen_assertions[0].RstNOn_A	12421546	963	0	0
gen_assertions[1].RstEnOff_A	49684909	11868	0	0
gen_assertions[1].RstEnOn_A	49684909	976	0	0
gen_assertions[1].RstNOff_A	49684909	11868	0	0
gen_assertions[1].RstNOn_A	49684909	976	0	0
gen_assertions[2].RstEnOff_A	24843413	11879	0	0
gen_assertions[2].RstEnOn_A	24843413	916	0	0
gen_assertions[2].RstNOff_A	24843413	11879	0	0
gen_assertions[2].RstNOn_A	24843413	916	0	0
gen_assertions[3].RstEnOff_A	24843561	11907	0	0
gen_assertions[3].RstEnOn_A	24843561	939	0	0
gen_assertions[3].RstNOff_A	24843561	11907	0	0
gen_assertions[3].RstNOn_A	24843561	939	0	0
gen_assertions[4].RstEnOff_A	1568189	20484	0	0
gen_assertions[4].RstEnOn_A	1568189	1030	0	0
gen_assertions[4].RstNOff_A	1568189	20484	0	0
gen_assertions[4].RstNOn_A	1568189	1030	0	0
gen_assertions[5].RstEnOff_A	12421546	13235	0	0
gen_assertions[5].RstEnOn_A	12421546	1056	0	0
gen_assertions[5].RstNOff_A	12421546	13235	0	0
gen_assertions[5].RstNOn_A	12421546	1056	0	0
gen_assertions[6].RstEnOff_A	12421546	13300	0	0
gen_assertions[6].RstEnOn_A	12421546	1123	0	0
gen_assertions[6].RstNOff_A	12421546	13300	0	0
gen_assertions[6].RstNOn_A	12421546	1123	0	0
gen_assertions[7].RstEnOff_A	12421546	13327	0	0
gen_assertions[7].RstEnOn_A	12421546	1149	0	0
gen_assertions[7].RstNOff_A	12421546	13327	0	0
gen_assertions[7].RstNOn_A	12421546	1149	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13008	0	0
T2	2066	3	0	0
T3	3156	5	0	0
T4	1969	0	0	0
T5	9423	3	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	0	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0
T14	0	5	0	0
T15	0	9	0	0
T18	198223	0	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	963	0	0
T3	3156	5	0	0
T4	1969	0	0	0
T5	9423	3	0	0
T6	5838	0	0	0
T7	2918	9	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	0	0	0
T11	17013	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	198223	0	0	0
T30	0	7	0	0
T45	0	6	0	0
T46	0	4	0	0
T47	0	9	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13008	0	0
T2	2066	3	0	0
T3	3156	5	0	0
T4	1969	0	0	0
T5	9423	3	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	0	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0
T14	0	5	0	0
T15	0	9	0	0
T18	198223	0	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	963	0	0
T3	3156	5	0	0
T4	1969	0	0	0
T5	9423	3	0	0
T6	5838	0	0	0
T7	2918	9	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	0	0	0
T11	17013	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	198223	0	0	0
T30	0	7	0	0
T45	0	6	0	0
T46	0	4	0	0
T47	0	9	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	11868	0	0
T1	29901	2	0	0
T2	8269	3	0	0
T3	12626	7	0	0
T4	7876	0	0	0
T5	37692	2	0	0
T6	23364	0	0	0
T7	11679	11	0	0
T8	181562	66	0	0
T9	23238	0	0	0
T10	24677	2	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	976	0	0
T1	29901	2	0	0
T2	8269	0	0	0
T3	12626	7	0	0
T4	7876	0	0	0
T5	37692	2	0	0
T6	23364	0	0	0
T7	11679	4	0	0
T8	181562	0	0	0
T9	23238	0	0	0
T10	24677	2	0	0
T17	0	2	0	0
T30	0	8	0	0
T45	0	8	0	0
T46	0	8	0	0
T47	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	11868	0	0
T1	29901	2	0	0
T2	8269	3	0	0
T3	12626	7	0	0
T4	7876	0	0	0
T5	37692	2	0	0
T6	23364	0	0	0
T7	11679	11	0	0
T8	181562	66	0	0
T9	23238	0	0	0
T10	24677	2	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49684909	976	0	0
T1	29901	2	0	0
T2	8269	0	0	0
T3	12626	7	0	0
T4	7876	0	0	0
T5	37692	2	0	0
T6	23364	0	0	0
T7	11679	4	0	0
T8	181562	0	0	0
T9	23238	0	0	0
T10	24677	2	0	0
T17	0	2	0	0
T30	0	8	0	0
T45	0	8	0	0
T46	0	8	0	0
T47	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	11879	0	0
T1	14951	2	0	0
T2	4133	3	0	0
T3	6312	7	0	0
T4	3937	0	0	0
T5	18846	4	0	0
T6	11680	0	0	0
T7	5839	11	0	0
T8	90771	66	0	0
T9	11621	0	0	0
T10	12338	3	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	916	0	0
T1	14951	2	0	0
T2	4133	0	0	0
T3	6312	7	0	0
T4	3937	0	0	0
T5	18846	4	0	0
T6	11680	0	0	0
T7	5839	0	0	0
T8	90771	0	0	0
T9	11621	0	0	0
T10	12338	3	0	0
T17	0	2	0	0
T30	0	7	0	0
T33	0	6	0	0
T45	0	9	0	0
T46	0	7	0	0
T47	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	11879	0	0
T1	14951	2	0	0
T2	4133	3	0	0
T3	6312	7	0	0
T4	3937	0	0	0
T5	18846	4	0	0
T6	11680	0	0	0
T7	5839	11	0	0
T8	90771	66	0	0
T9	11621	0	0	0
T10	12338	3	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843413	916	0	0
T1	14951	2	0	0
T2	4133	0	0	0
T3	6312	7	0	0
T4	3937	0	0	0
T5	18846	4	0	0
T6	11680	0	0	0
T7	5839	0	0	0
T8	90771	0	0	0
T9	11621	0	0	0
T10	12338	3	0	0
T17	0	2	0	0
T30	0	7	0	0
T33	0	6	0	0
T45	0	9	0	0
T46	0	7	0	0
T47	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	11907	0	0
T1	14951	3	0	0
T2	4134	3	0	0
T3	6312	8	0	0
T4	3937	0	0	0
T5	18847	5	0	0
T6	11683	0	0	0
T7	5839	11	0	0
T8	90798	66	0	0
T9	11611	0	0	0
T10	12338	3	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	939	0	0
T1	14951	3	0	0
T2	4134	0	0	0
T3	6312	8	0	0
T4	3937	0	0	0
T5	18847	5	0	0
T6	11683	0	0	0
T7	5839	0	0	0
T8	90798	0	0	0
T9	11611	0	0	0
T10	12338	3	0	0
T14	0	1	0	0
T17	0	3	0	0
T30	0	7	0	0
T45	0	8	0	0
T46	0	10	0	0
T47	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	11907	0	0
T1	14951	3	0	0
T2	4134	3	0	0
T3	6312	8	0	0
T4	3937	0	0	0
T5	18847	5	0	0
T6	11683	0	0	0
T7	5839	11	0	0
T8	90798	66	0	0
T9	11611	0	0	0
T10	12338	3	0	0
T11	0	24	0	0
T12	0	66	0	0
T13	0	30	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24843561	939	0	0
T1	14951	3	0	0
T2	4134	0	0	0
T3	6312	8	0	0
T4	3937	0	0	0
T5	18847	5	0	0
T6	11683	0	0	0
T7	5839	0	0	0
T8	90798	0	0	0
T9	11611	0	0	0
T10	12338	3	0	0
T14	0	1	0	0
T17	0	3	0	0
T30	0	7	0	0
T45	0	8	0	0
T46	0	10	0	0
T47	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	20484	0	0
T1	934	5	0	0
T2	257	4	0	0
T3	394	9	0	0
T4	246	1	0	0
T5	1177	7	0	0
T6	731	3	0	0
T7	364	13	0	0
T8	5688	90	0	0
T9	729	2	0	0
T10	769	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	1030	0	0
T1	934	4	0	0
T2	257	0	0	0
T3	394	8	0	0
T4	246	0	0	0
T5	1177	6	0	0
T6	731	0	0	0
T7	364	0	0	0
T8	5688	0	0	0
T9	729	0	0	0
T10	769	4	0	0
T17	0	2	0	0
T30	0	7	0	0
T33	0	6	0	0
T45	0	9	0	0
T46	0	10	0	0
T47	0	12	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	20484	0	0
T1	934	5	0	0
T2	257	4	0	0
T3	394	9	0	0
T4	246	1	0	0
T5	1177	7	0	0
T6	731	3	0	0
T7	364	13	0	0
T8	5688	90	0	0
T9	729	2	0	0
T10	769	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1568189	1030	0	0
T1	934	4	0	0
T2	257	0	0	0
T3	394	8	0	0
T4	246	0	0	0
T5	1177	6	0	0
T6	731	0	0	0
T7	364	0	0	0
T8	5688	0	0	0
T9	729	0	0	0
T10	769	4	0	0
T17	0	2	0	0
T30	0	7	0	0
T33	0	6	0	0
T45	0	9	0	0
T46	0	10	0	0
T47	0	12	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13235	0	0
T1	7474	5	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1056	0	0
T1	7474	5	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T17	0	2	0	0
T30	0	6	0	0
T33	0	7	0	0
T45	0	11	0	0
T46	0	10	0	0
T47	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13235	0	0
T1	7474	5	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1056	0	0
T1	7474	5	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T17	0	2	0	0
T30	0	6	0	0
T33	0	7	0	0
T45	0	11	0	0
T46	0	10	0	0
T47	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13300	0	0
T1	7474	7	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1123	0	0
T1	7474	7	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T14	0	1	0	0
T17	0	3	0	0
T30	0	5	0	0
T45	0	10	0	0
T46	0	13	0	0
T47	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13300	0	0
T1	7474	7	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1123	0	0
T1	7474	7	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	8	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	6	0	0
T14	0	1	0	0
T17	0	3	0	0
T30	0	5	0	0
T45	0	10	0	0
T46	0	13	0	0
T47	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13327	0	0
T1	7474	7	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	9	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	7	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1149	0	0
T1	7474	7	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	9	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	7	0	0
T17	0	3	0	0
T30	0	5	0	0
T33	0	5	0	0
T45	0	11	0	0
T46	0	13	0	0
T47	0	11	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	13327	0	0
T1	7474	7	0	0
T2	2066	3	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	9	0	0
T6	5838	0	0	0
T7	2918	12	0	0
T8	45394	75	0	0
T9	5810	0	0	0
T10	6168	7	0	0
T11	0	27	0	0
T12	0	75	0	0
T13	0	35	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12421546	1149	0	0
T1	7474	7	0	0
T2	2066	0	0	0
T3	3156	9	0	0
T4	1969	0	0	0
T5	9423	9	0	0
T6	5838	0	0	0
T7	2918	0	0	0
T8	45394	0	0	0
T9	5810	0	0	0
T10	6168	7	0	0
T17	0	3	0	0
T30	0	5	0	0
T33	0	5	0	0
T45	0	11	0	0
T46	0	13	0	0
T47	0	11	0	0