Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11846977	9665	0	0
alert_regwen_rd_A	11846977	3856	0	0
cpu_regwen_rd_A	11846977	3728	0	0
sw_rst_ctrl_n_0_rd_A	11846977	8738	0	0
sw_rst_ctrl_n_1_rd_A	11846977	8569	0	0
sw_rst_ctrl_n_2_rd_A	11846977	8865	0	0
sw_rst_ctrl_n_3_rd_A	11846977	8691	0	0
sw_rst_ctrl_n_4_rd_A	11846977	8700	0	0
sw_rst_ctrl_n_5_rd_A	11846977	8716	0	0
sw_rst_ctrl_n_6_rd_A	11846977	8762	0	0
sw_rst_ctrl_n_7_rd_A	11846977	8725	0	0
sw_rst_regwen_0_rd_A	11846977	4590	0	0
sw_rst_regwen_1_rd_A	11846977	4172	0	0
sw_rst_regwen_2_rd_A	11846977	4462	0	0
sw_rst_regwen_3_rd_A	11846977	4468	0	0
sw_rst_regwen_4_rd_A	11846977	4381	0	0
sw_rst_regwen_5_rd_A	11846977	4536	0	0
sw_rst_regwen_6_rd_A	11846977	4348	0	0
sw_rst_regwen_7_rd_A	11846977	4541	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	9665	0	0
T69	11603	1	0	0
T70	4446	172	0	0
T72	4788	36	0	0
T73	4819	28	0	0
T74	20720	3	0	0
T82	2775	5	0	0
T83	4625	25	0	0
T84	4785	20	0	0
T85	4776	119	0	0
T86	4183	12	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	3856	0	0
T13	38233	29	0	0
T14	2572	0	0	0
T15	2652	0	0	0
T16	3662	0	0	0
T17	36807	0	0	0
T33	0	80	0	0
T35	0	59	0	0
T45	3212	0	0	0
T46	8745	0	0	0
T47	3704	0	0	0
T48	5663	0	0	0
T61	0	65	0	0
T81	5276	0	0	0
T90	0	70	0	0
T91	0	348	0	0
T117	0	68	0	0
T118	0	52	0	0
T119	0	72	0	0
T120	0	313	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	3728	0	0
T13	38233	43	0	0
T14	2572	0	0	0
T15	2652	0	0	0
T16	3662	0	0	0
T17	36807	0	0	0
T33	0	68	0	0
T35	0	57	0	0
T45	3212	0	0	0
T46	8745	0	0	0
T47	3704	0	0	0
T48	5663	0	0	0
T61	0	67	0	0
T81	5276	0	0	0
T90	0	70	0	0
T91	0	347	0	0
T117	0	85	0	0
T118	0	56	0	0
T119	0	77	0	0
T120	0	371	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8738	0	0
T1	7432	64	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	113	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	28	0	0
T33	0	109	0	0
T35	0	161	0	0
T61	0	92	0	0
T90	0	153	0	0
T121	0	151	0	0
T122	0	138	0	0
T123	0	159	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8569	0	0
T1	7432	69	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	112	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	26	0	0
T33	0	139	0	0
T35	0	153	0	0
T61	0	79	0	0
T90	0	177	0	0
T121	0	190	0	0
T122	0	103	0	0
T123	0	153	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8865	0	0
T1	7432	47	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	109	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	55	0	0
T33	0	126	0	0
T35	0	160	0	0
T61	0	76	0	0
T90	0	156	0	0
T121	0	170	0	0
T122	0	148	0	0
T123	0	139	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8691	0	0
T1	7432	69	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	144	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	38	0	0
T33	0	110	0	0
T35	0	165	0	0
T61	0	71	0	0
T90	0	213	0	0
T121	0	137	0	0
T122	0	129	0	0
T123	0	118	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8700	0	0
T1	7432	69	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	130	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	43	0	0
T33	0	91	0	0
T35	0	136	0	0
T61	0	64	0	0
T90	0	166	0	0
T121	0	143	0	0
T122	0	120	0	0
T123	0	161	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8716	0	0
T1	7432	63	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	161	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	28	0	0
T33	0	147	0	0
T35	0	151	0	0
T61	0	61	0	0
T90	0	213	0	0
T121	0	185	0	0
T122	0	116	0	0
T123	0	135	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8762	0	0
T1	7432	82	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	118	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	25	0	0
T33	0	84	0	0
T35	0	131	0	0
T61	0	93	0	0
T90	0	167	0	0
T121	0	189	0	0
T122	0	140	0	0
T123	0	139	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	8725	0	0
T1	7432	80	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	98	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	30	0	0
T33	0	138	0	0
T35	0	169	0	0
T61	0	60	0	0
T90	0	152	0	0
T121	0	169	0	0
T122	0	129	0	0
T123	0	183	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4590	0	0
T1	7432	17	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	29	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	39	0	0
T33	0	83	0	0
T35	0	73	0	0
T61	0	60	0	0
T90	0	54	0	0
T121	0	26	0	0
T122	0	25	0	0
T123	0	31	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4172	0	0
T1	7432	30	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	34	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	18	0	0
T33	0	52	0	0
T35	0	53	0	0
T61	0	64	0	0
T90	0	69	0	0
T121	0	29	0	0
T122	0	27	0	0
T123	0	28	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4462	0	0
T1	7432	14	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	36	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	37	0	0
T33	0	87	0	0
T35	0	51	0	0
T61	0	83	0	0
T90	0	78	0	0
T121	0	28	0	0
T122	0	38	0	0
T123	0	30	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4468	0	0
T1	7432	15	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	27	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	37	0	0
T33	0	50	0	0
T35	0	42	0	0
T61	0	74	0	0
T90	0	41	0	0
T121	0	27	0	0
T122	0	35	0	0
T123	0	29	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4381	0	0
T1	7432	13	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	24	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	44	0	0
T33	0	74	0	0
T35	0	43	0	0
T61	0	72	0	0
T90	0	84	0	0
T121	0	30	0	0
T122	0	25	0	0
T123	0	30	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4536	0	0
T1	7432	13	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	24	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	27	0	0
T33	0	70	0	0
T35	0	81	0	0
T61	0	67	0	0
T90	0	70	0	0
T121	0	38	0	0
T122	0	35	0	0
T123	0	44	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4348	0	0
T1	7432	11	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	27	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	46	0	0
T33	0	59	0	0
T35	0	53	0	0
T61	0	77	0	0
T90	0	75	0	0
T121	0	20	0	0
T122	0	32	0	0
T123	0	24	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846977	4541	0	0
T1	7432	31	0	0
T2	1770	0	0	0
T3	3113	0	0	0
T4	1878	0	0	0
T5	9356	33	0	0
T6	5104	0	0	0
T7	2121	0	0	0
T8	42162	0	0	0
T9	5073	0	0	0
T10	6078	0	0	0
T13	0	71	0	0
T33	0	70	0	0
T35	0	57	0	0
T61	0	59	0	0
T90	0	81	0	0
T121	0	23	0	0
T122	0	39	0	0
T123	0	39	0	0