Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	610798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

366113

1

T1

136

T3

76

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	521036	1			T1	186		T2	1		T3	99
values[0x0]	227631	1			T1	96		T3	54		T4	11
values[0x1]	228244	1			T1	97		T3	59		T4	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

464224

1

T1

178

T2

1

T3

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3456	1			T1	3		T10	2		T11	11
valid_sources[0x01]	3432	1			T11	2		T13	15		T66	2
valid_sources[0x02]	3858	1			T6	1		T11	13		T13	10
valid_sources[0x03]	4435	1			T10	1		T11	8		T13	11
valid_sources[0x04]	3985	1			T10	6		T11	13		T13	19
valid_sources[0x05]	4081	1			T10	3		T11	4		T13	18
valid_sources[0x06]	4128	1			T3	3		T6	1		T10	3
valid_sources[0x07]	3700	1			T10	5		T11	12		T13	18
valid_sources[0x08]	3192	1			T3	5		T10	5		T11	11
valid_sources[0x09]	3707	1			T3	4		T10	4		T11	10
valid_sources[0x0a]	4242	1			T10	4		T11	9		T13	8
valid_sources[0x0b]	3951	1			T1	10		T10	3		T11	10
valid_sources[0x0c]	3394	1			T5	6		T10	4		T11	5
valid_sources[0x0d]	3583	1			T6	1		T10	5		T11	14
valid_sources[0x0e]	3651	1			T10	5		T11	10		T13	7
valid_sources[0x0f]	5569	1			T3	2		T5	2		T11	15
valid_sources[0x10]	3258	1			T4	2		T10	4		T11	11
valid_sources[0x11]	3578	1			T4	1		T11	14		T12	7
valid_sources[0x12]	3458	1			T3	3		T10	2		T11	9
valid_sources[0x13]	3828	1			T3	1		T10	2		T11	12
valid_sources[0x14]	3630	1			T5	3		T10	5		T11	13
valid_sources[0x15]	3775	1			T3	2		T10	9		T11	10
valid_sources[0x16]	3560	1			T3	2		T6	1		T10	7
valid_sources[0x17]	3682	1			T4	2		T5	3		T6	2
valid_sources[0x18]	4560	1			T10	10		T11	10		T13	8
valid_sources[0x19]	3355	1			T1	11		T10	4		T11	8
valid_sources[0x1a]	4923	1			T5	1		T10	1		T11	9
valid_sources[0x1b]	3479	1			T1	4		T10	1		T11	3
valid_sources[0x1c]	3800	1			T3	1		T10	4		T11	13
valid_sources[0x1d]	3288	1			T1	11		T6	1		T10	1
valid_sources[0x1e]	3198	1			T6	1		T10	12		T11	9
valid_sources[0x1f]	3571	1			T11	6		T12	23		T13	16
valid_sources[0x20]	3608	1			T3	2		T6	1		T10	3
valid_sources[0x21]	3868	1			T3	5		T10	9		T11	11
valid_sources[0x22]	3847	1			T6	2		T10	2		T11	8
valid_sources[0x23]	3724	1			T6	1		T10	2		T11	6
valid_sources[0x24]	3600	1			T10	3		T11	8		T12	1
valid_sources[0x25]	6763	1			T5	5		T10	7		T11	11
valid_sources[0x26]	4636	1			T3	4		T11	12		T13	15
valid_sources[0x27]	3670	1			T10	3		T11	12		T12	4
valid_sources[0x28]	3714	1			T10	2		T11	11		T13	8
valid_sources[0x29]	3337	1			T1	6		T3	5		T4	1
valid_sources[0x2a]	3917	1			T10	2		T11	7		T13	1
valid_sources[0x2b]	3259	1			T6	4		T10	1		T11	12
valid_sources[0x2c]	3174	1			T10	1		T11	8		T13	7
valid_sources[0x2d]	3447	1			T3	1		T10	5		T11	7
valid_sources[0x2e]	3774	1			T2	1		T10	6		T11	12
valid_sources[0x2f]	3155	1			T10	2		T11	10		T12	4
valid_sources[0x30]	3288	1			T3	1		T6	2		T10	5
valid_sources[0x31]	4365	1			T10	4		T11	12		T13	19
valid_sources[0x32]	3593	1			T10	1		T11	6		T13	19
valid_sources[0x33]	3574	1			T6	3		T11	6		T13	11
valid_sources[0x34]	3707	1			T6	3		T10	5		T11	16
valid_sources[0x35]	3630	1			T10	3		T11	10		T12	12
valid_sources[0x36]	3502	1			T10	3		T11	11		T13	9
valid_sources[0x37]	3222	1			T3	8		T11	8		T13	13
valid_sources[0x38]	3829	1			T6	4		T10	3		T11	3
valid_sources[0x39]	3754	1			T11	8		T13	5		T22	1
valid_sources[0x3a]	7118	1			T6	1		T10	3		T11	4
valid_sources[0x3b]	3467	1			T6	2		T10	4		T11	13
valid_sources[0x3c]	4112	1			T10	3		T11	11		T12	8
valid_sources[0x3d]	3393	1			T3	1		T6	6		T10	1
valid_sources[0x3e]	4069	1			T3	3		T10	6		T11	11
valid_sources[0x3f]	3175	1			T4	1		T6	2		T10	1
valid_sources[0x40]	4526	1			T3	2		T6	2		T10	1
valid_sources[0x41]	3641	1			T10	3		T11	9		T13	15
valid_sources[0x42]	3192	1			T6	1		T10	5		T11	9
valid_sources[0x43]	3613	1			T3	2		T10	3		T11	11
valid_sources[0x44]	4173	1			T10	4		T11	5		T13	12
valid_sources[0x45]	3445	1			T3	6		T10	1		T11	4
valid_sources[0x46]	3629	1			T10	7		T11	7		T13	22
valid_sources[0x47]	7225	1			T10	2		T11	10		T13	9
valid_sources[0x48]	3566	1			T10	6		T11	8		T13	5
valid_sources[0x49]	3359	1			T11	9		T13	10		T66	6
valid_sources[0x4a]	3849	1			T11	10		T13	26		T66	2
valid_sources[0x4b]	3938	1			T6	3		T10	5		T11	11
valid_sources[0x4c]	3943	1			T10	4		T11	6		T13	9
valid_sources[0x4d]	3450	1			T10	3		T11	6		T13	17
valid_sources[0x4e]	4380	1			T11	5		T13	11		T22	1
valid_sources[0x4f]	3737	1			T3	2		T10	2		T11	12
valid_sources[0x50]	3771	1			T3	9		T6	1		T10	7
valid_sources[0x51]	3983	1			T10	9		T11	10		T12	3
valid_sources[0x52]	3665	1			T5	1		T6	5		T10	1
valid_sources[0x53]	3809	1			T10	2		T11	8		T13	17
valid_sources[0x54]	3634	1			T11	10		T13	2		T72	1
valid_sources[0x55]	3343	1			T6	1		T10	4		T11	10
valid_sources[0x56]	3817	1			T1	80		T3	3		T10	1
valid_sources[0x57]	3402	1			T10	5		T11	8		T13	13
valid_sources[0x58]	3423	1			T3	3		T10	3		T11	10
valid_sources[0x59]	3792	1			T7	1		T10	6		T11	13
valid_sources[0x5a]	3717	1			T10	1		T11	11		T13	20
valid_sources[0x5b]	3875	1			T3	2		T10	4		T11	2
valid_sources[0x5c]	3468	1			T1	6		T3	5		T10	4
valid_sources[0x5d]	3836	1			T3	7		T6	2		T10	1
valid_sources[0x5e]	3164	1			T3	5		T11	12		T13	21
valid_sources[0x5f]	3371	1			T10	5		T11	5		T13	11
valid_sources[0x60]	3710	1			T3	2		T10	1		T11	16
valid_sources[0x61]	6869	1			T6	2		T11	11		T13	14
valid_sources[0x62]	3569	1			T3	3		T10	3		T11	4
valid_sources[0x63]	3513	1			T10	2		T11	9		T12	12
valid_sources[0x64]	3388	1			T6	1		T10	2		T11	10
valid_sources[0x65]	3280	1			T10	2		T11	9		T13	21
valid_sources[0x66]	4092	1			T5	2		T10	1		T11	14
valid_sources[0x67]	3914	1			T6	5		T10	1		T11	13
valid_sources[0x68]	4643	1			T3	2		T5	12		T10	8
valid_sources[0x69]	3301	1			T10	1		T11	10		T13	3
valid_sources[0x6a]	3834	1			T3	1		T6	3		T10	8
valid_sources[0x6b]	3363	1			T4	1		T11	11		T13	5
valid_sources[0x6c]	3402	1			T4	2		T5	4		T10	2
valid_sources[0x6d]	3675	1			T1	1		T10	4		T11	7
valid_sources[0x6e]	3368	1			T3	1		T10	6		T11	7
valid_sources[0x6f]	3636	1			T1	25		T11	9		T13	7
valid_sources[0x70]	3839	1			T5	3		T10	1		T11	13
valid_sources[0x71]	3579	1			T10	1		T11	8		T13	14
valid_sources[0x72]	4001	1			T10	1		T11	2		T13	6
valid_sources[0x73]	3139	1			T10	5		T11	6		T12	1
valid_sources[0x74]	3528	1			T10	3		T11	7		T13	18
valid_sources[0x75]	4149	1			T10	1		T11	11		T13	9
valid_sources[0x76]	3853	1			T10	3		T11	11		T13	6
valid_sources[0x77]	3498	1			T10	5		T11	6		T13	17
valid_sources[0x78]	4052	1			T1	15		T3	6		T11	11
valid_sources[0x79]	3683	1			T10	1		T11	13		T13	18
valid_sources[0x7a]	3457	1			T3	4		T10	5		T11	15
valid_sources[0x7b]	2933	1			T6	2		T10	1		T11	8
valid_sources[0x7c]	3463	1			T10	1		T11	9		T13	8
valid_sources[0x7d]	5107	1			T3	6		T5	5		T10	7
valid_sources[0x7e]	3588	1			T6	2		T10	6		T11	7
valid_sources[0x7f]	3624	1			T6	1		T10	1		T11	8
valid_sources[0x80]	3392	1			T10	4		T11	9		T13	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

243508

1

T1

96

T3

50

T5

22

values[0x0]

all_enables

biggest_size

79862

1

T1

28

T3

18

T4

3

values[0x1]

all_enables

biggest_size

42743

1

T1

12

T3

8

T4

1