Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	54	54	100.00
Total Bits 0->1	27	27	100.00
Total Bits 1->0	27	27	100.00

Ports	5	5	100.00
Port Bits	54	54	100.00
Port Bits 0->1	27	27	100.00
Port Bits 1->0	27	27	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
oh_i[4:0]	Yes	Yes	*T4,*T57,*T81	Yes	T4,T57,T81	INPUT
oh_i[6:5]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[8:7]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	INPUT
oh_i[10:9]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[26:11]	Yes	Yes	*T1,*T8,T10	Yes	T1,T8,T10	INPUT
oh_i[27]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
err_o	Yes	Yes	T54,T74,T75	Yes	T54,T74,T75	OUTPUT

*Tests covering at least one bit in the range