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 LINE       1340
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T6,T8
1	1	0	Covered	T76,T98,T99
1	1	1	Covered	T1,T8,T10

 LINE       1343
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T98,T99
1	1	1	Covered	T1,T5,T6

 LINE       1346
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T79,T99
1	1	1	Covered	T1,T5,T6

 LINE       1349
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T79,T80
1	1	1	Covered	T1,T5,T6

 LINE       1352
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T80,T99
1	1	1	Covered	T1,T5,T6

 LINE       1355
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T98,T100
1	1	1	Covered	T1,T5,T6

 LINE       1358
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T77,T79
1	1	1	Covered	T1,T5,T6

 LINE       1361
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T76,T79,T98
1	1	1	Covered	T1,T5,T6

 LINE       1364
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T5,T6
1	1	0	Covered	T79,T98,T99
1	1	1	Covered	T1,T5,T6