Line Coverage for Module :
rstmgr_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 178 | 178 | 100.00 |
| ALWAYS | 70 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 223 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 238 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 254 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 430 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 551 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 877 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 909 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 941 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 973 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1005 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1037 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1069 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1101 | 1 | 1 | 100.00 |
| ALWAYS | 1215 | 29 | 29 | 100.00 |
| CONT_ASSIGN | 1246 | 1 | 1 | 100.00 |
| ALWAYS | 1250 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1284 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1287 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1290 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1292 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1296 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1298 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1299 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1301 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1304 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1306 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1309 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1311 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1312 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1319 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1322 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1324 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1325 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1327 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1328 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1330 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1331 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1333 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1337 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1339 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1340 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1342 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1343 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1345 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1346 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1348 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1349 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1351 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1352 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1354 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1355 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1357 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1358 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1360 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1361 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1363 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1364 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1366 | 1 | 1 | 100.00 |
| ALWAYS | 1370 | 29 | 29 | 100.00 |
| ALWAYS | 1403 | 38 | 38 | 100.00 |
| CONT_ASSIGN | 1536 | 0 | 0 | |
| CONT_ASSIGN | 1544 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1545 | 1 | 1 | 100.00 |
69 always_ff @(posedge clk_i or negedge rst_ni) begin
70 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
71 1/1 err_q <= '0;
Tests: T1 T2 T3
72 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
73 1/1 err_q <= 1'b1;
Tests: T54 T74 T75
74 end
MISSING_ELSE
75 end
76
77 // integrity error output is permanent and should be used for alert generation
78 // register errors are transactional
79 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T3 T4
80
81 // outgoing integrity generation
82 tlul_pkg::tl_d2h_t tl_o_pre;
83 tlul_rsp_intg_gen #(
84 .EnableRspIntgGen(1),
85 .EnableDataIntgGen(1)
86 ) u_rsp_intg_gen (
87 .tl_i(tl_o_pre),
88 .tl_o(tl_o)
89 );
90
91 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
92 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
93
94 tlul_adapter_reg #(
95 .RegAw(AW),
96 .RegDw(DW),
97 .EnableDataIntgGen(0)
98 ) u_reg_if (
99 .clk_i (clk_i),
100 .rst_ni (rst_ni),
101
102 .tl_i (tl_reg_h2d),
103 .tl_o (tl_reg_d2h),
104
105 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
106 .intg_error_o(),
107
108 .we_o (reg_we),
109 .re_o (reg_re),
110 .addr_o (reg_addr),
111 .wdata_o (reg_wdata),
112 .be_o (reg_be),
113 .busy_i (reg_busy),
114 .rdata_i (reg_rdata),
115 .error_i (reg_error)
116 );
117
118 // cdc oversampling signals
119
120 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
121 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T76 T77 T79
122
123 // Define SW related signals
124 // Format: <reg>_<field>_{wd|we|qs}
125 // or <reg>_{wd|we|qs} if field == 1 or 0
126 logic alert_test_we;
127 logic alert_test_fatal_fault_wd;
128 logic alert_test_fatal_cnsty_fault_wd;
129 logic reset_req_we;
130 logic [3:0] reset_req_qs;
131 logic [3:0] reset_req_wd;
132 logic reset_info_we;
133 logic reset_info_por_qs;
134 logic reset_info_por_wd;
135 logic reset_info_low_power_exit_qs;
136 logic reset_info_low_power_exit_wd;
137 logic reset_info_sw_reset_qs;
138 logic reset_info_sw_reset_wd;
139 logic [4:0] reset_info_hw_req_qs;
140 logic [4:0] reset_info_hw_req_wd;
141 logic alert_regwen_we;
142 logic alert_regwen_qs;
143 logic alert_regwen_wd;
144 logic alert_info_ctrl_we;
145 logic alert_info_ctrl_en_qs;
146 logic alert_info_ctrl_en_wd;
147 logic [3:0] alert_info_ctrl_index_qs;
148 logic [3:0] alert_info_ctrl_index_wd;
149 logic alert_info_attr_re;
150 logic [3:0] alert_info_attr_qs;
151 logic alert_info_re;
152 logic [31:0] alert_info_qs;
153 logic cpu_regwen_we;
154 logic cpu_regwen_qs;
155 logic cpu_regwen_wd;
156 logic cpu_info_ctrl_we;
157 logic cpu_info_ctrl_en_qs;
158 logic cpu_info_ctrl_en_wd;
159 logic [3:0] cpu_info_ctrl_index_qs;
160 logic [3:0] cpu_info_ctrl_index_wd;
161 logic cpu_info_attr_re;
162 logic [3:0] cpu_info_attr_qs;
163 logic cpu_info_re;
164 logic [31:0] cpu_info_qs;
165 logic sw_rst_regwen_0_we;
166 logic sw_rst_regwen_0_qs;
167 logic sw_rst_regwen_0_wd;
168 logic sw_rst_regwen_1_we;
169 logic sw_rst_regwen_1_qs;
170 logic sw_rst_regwen_1_wd;
171 logic sw_rst_regwen_2_we;
172 logic sw_rst_regwen_2_qs;
173 logic sw_rst_regwen_2_wd;
174 logic sw_rst_regwen_3_we;
175 logic sw_rst_regwen_3_qs;
176 logic sw_rst_regwen_3_wd;
177 logic sw_rst_regwen_4_we;
178 logic sw_rst_regwen_4_qs;
179 logic sw_rst_regwen_4_wd;
180 logic sw_rst_regwen_5_we;
181 logic sw_rst_regwen_5_qs;
182 logic sw_rst_regwen_5_wd;
183 logic sw_rst_regwen_6_we;
184 logic sw_rst_regwen_6_qs;
185 logic sw_rst_regwen_6_wd;
186 logic sw_rst_regwen_7_we;
187 logic sw_rst_regwen_7_qs;
188 logic sw_rst_regwen_7_wd;
189 logic sw_rst_ctrl_n_0_we;
190 logic sw_rst_ctrl_n_0_qs;
191 logic sw_rst_ctrl_n_0_wd;
192 logic sw_rst_ctrl_n_1_we;
193 logic sw_rst_ctrl_n_1_qs;
194 logic sw_rst_ctrl_n_1_wd;
195 logic sw_rst_ctrl_n_2_we;
196 logic sw_rst_ctrl_n_2_qs;
197 logic sw_rst_ctrl_n_2_wd;
198 logic sw_rst_ctrl_n_3_we;
199 logic sw_rst_ctrl_n_3_qs;
200 logic sw_rst_ctrl_n_3_wd;
201 logic sw_rst_ctrl_n_4_we;
202 logic sw_rst_ctrl_n_4_qs;
203 logic sw_rst_ctrl_n_4_wd;
204 logic sw_rst_ctrl_n_5_we;
205 logic sw_rst_ctrl_n_5_qs;
206 logic sw_rst_ctrl_n_5_wd;
207 logic sw_rst_ctrl_n_6_we;
208 logic sw_rst_ctrl_n_6_qs;
209 logic sw_rst_ctrl_n_6_wd;
210 logic sw_rst_ctrl_n_7_we;
211 logic sw_rst_ctrl_n_7_qs;
212 logic sw_rst_ctrl_n_7_wd;
213 logic err_code_reg_intg_err_qs;
214 logic err_code_reset_consistency_err_qs;
215 logic err_code_fsm_err_qs;
216 // Define register CDC handling.
217 // CDC handling is done on a per-reg instead of per-field boundary.
218
219 // Register instances
220 // R[alert_test]: V(True)
221 logic alert_test_qe;
222 logic [1:0] alert_test_flds_we;
223 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T4 T57 T81
224 // F[fatal_fault]: 0:0
225 prim_subreg_ext #(
226 .DW (1)
227 ) u_alert_test_fatal_fault (
228 .re (1'b0),
229 .we (alert_test_we),
230 .wd (alert_test_fatal_fault_wd),
231 .d ('0),
232 .qre (),
233 .qe (alert_test_flds_we[0]),
234 .q (reg2hw.alert_test.fatal_fault.q),
235 .ds (),
236 .qs ()
237 );
238 1/1 assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;
Tests: T4 T57 T81
239
240 // F[fatal_cnsty_fault]: 1:1
241 prim_subreg_ext #(
242 .DW (1)
243 ) u_alert_test_fatal_cnsty_fault (
244 .re (1'b0),
245 .we (alert_test_we),
246 .wd (alert_test_fatal_cnsty_fault_wd),
247 .d ('0),
248 .qre (),
249 .qe (alert_test_flds_we[1]),
250 .q (reg2hw.alert_test.fatal_cnsty_fault.q),
251 .ds (),
252 .qs ()
253 );
254 1/1 assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe;
Tests: T4 T57 T81
255
256
257 // R[reset_req]: V(False)
258 prim_subreg #(
259 .DW (4),
260 .SwAccess(prim_subreg_pkg::SwAccessRW),
261 .RESVAL (4'h9),
262 .Mubi (1'b1)
263 ) u_reset_req (
264 .clk_i (clk_i),
265 .rst_ni (rst_ni),
266
267 // from register interface
268 .we (reset_req_we),
269 .wd (reset_req_wd),
270
271 // from internal hardware
272 .de (hw2reg.reset_req.de),
273 .d (hw2reg.reset_req.d),
274
275 // to internal hardware
276 .qe (),
277 .q (reg2hw.reset_req.q),
278 .ds (),
279
280 // to register interface (read)
281 .qs (reset_req_qs)
282 );
283
284
285 // R[reset_info]: V(False)
286 // F[por]: 0:0
287 prim_subreg #(
288 .DW (1),
289 .SwAccess(prim_subreg_pkg::SwAccessW1C),
290 .RESVAL (1'h1),
291 .Mubi (1'b0)
292 ) u_reset_info_por (
293 // sync clock and reset required for this register
294 .clk_i (clk_por_i),
295 .rst_ni (rst_por_ni),
296
297 // from register interface
298 .we (reset_info_we),
299 .wd (reset_info_por_wd),
300
301 // from internal hardware
302 .de (1'b0),
303 .d ('0),
304
305 // to internal hardware
306 .qe (),
307 .q (),
308 .ds (),
309
310 // to register interface (read)
311 .qs (reset_info_por_qs)
312 );
313
314 // F[low_power_exit]: 1:1
315 prim_subreg #(
316 .DW (1),
317 .SwAccess(prim_subreg_pkg::SwAccessW1C),
318 .RESVAL (1'h0),
319 .Mubi (1'b0)
320 ) u_reset_info_low_power_exit (
321 // sync clock and reset required for this register
322 .clk_i (clk_por_i),
323 .rst_ni (rst_por_ni),
324
325 // from register interface
326 .we (reset_info_we),
327 .wd (reset_info_low_power_exit_wd),
328
329 // from internal hardware
330 .de (hw2reg.reset_info.low_power_exit.de),
331 .d (hw2reg.reset_info.low_power_exit.d),
332
333 // to internal hardware
334 .qe (),
335 .q (),
336 .ds (),
337
338 // to register interface (read)
339 .qs (reset_info_low_power_exit_qs)
340 );
341
342 // F[sw_reset]: 2:2
343 prim_subreg #(
344 .DW (1),
345 .SwAccess(prim_subreg_pkg::SwAccessW1C),
346 .RESVAL (1'h0),
347 .Mubi (1'b0)
348 ) u_reset_info_sw_reset (
349 // sync clock and reset required for this register
350 .clk_i (clk_por_i),
351 .rst_ni (rst_por_ni),
352
353 // from register interface
354 .we (reset_info_we),
355 .wd (reset_info_sw_reset_wd),
356
357 // from internal hardware
358 .de (hw2reg.reset_info.sw_reset.de),
359 .d (hw2reg.reset_info.sw_reset.d),
360
361 // to internal hardware
362 .qe (),
363 .q (reg2hw.reset_info.sw_reset.q),
364 .ds (),
365
366 // to register interface (read)
367 .qs (reset_info_sw_reset_qs)
368 );
369
370 // F[hw_req]: 7:3
371 prim_subreg #(
372 .DW (5),
373 .SwAccess(prim_subreg_pkg::SwAccessW1C),
374 .RESVAL (5'h0),
375 .Mubi (1'b0)
376 ) u_reset_info_hw_req (
377 // sync clock and reset required for this register
378 .clk_i (clk_por_i),
379 .rst_ni (rst_por_ni),
380
381 // from register interface
382 .we (reset_info_we),
383 .wd (reset_info_hw_req_wd),
384
385 // from internal hardware
386 .de (hw2reg.reset_info.hw_req.de),
387 .d (hw2reg.reset_info.hw_req.d),
388
389 // to internal hardware
390 .qe (),
391 .q (reg2hw.reset_info.hw_req.q),
392 .ds (),
393
394 // to register interface (read)
395 .qs (reset_info_hw_req_qs)
396 );
397
398
399 // R[alert_regwen]: V(False)
400 prim_subreg #(
401 .DW (1),
402 .SwAccess(prim_subreg_pkg::SwAccessW0C),
403 .RESVAL (1'h1),
404 .Mubi (1'b0)
405 ) u_alert_regwen (
406 .clk_i (clk_i),
407 .rst_ni (rst_ni),
408
409 // from register interface
410 .we (alert_regwen_we),
411 .wd (alert_regwen_wd),
412
413 // from internal hardware
414 .de (1'b0),
415 .d ('0),
416
417 // to internal hardware
418 .qe (),
419 .q (),
420 .ds (),
421
422 // to register interface (read)
423 .qs (alert_regwen_qs)
424 );
425
426
427 // R[alert_info_ctrl]: V(False)
428 // Create REGWEN-gated WE signal
429 logic alert_info_ctrl_gated_we;
430 1/1 assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs;
Tests: T1 T3 T5
431 // F[en]: 0:0
432 prim_subreg #(
433 .DW (1),
434 .SwAccess(prim_subreg_pkg::SwAccessRW),
435 .RESVAL (1'h0),
436 .Mubi (1'b0)
437 ) u_alert_info_ctrl_en (
438 // sync clock and reset required for this register
439 .clk_i (clk_por_i),
440 .rst_ni (rst_por_ni),
441
442 // from register interface
443 .we (alert_info_ctrl_gated_we),
444 .wd (alert_info_ctrl_en_wd),
445
446 // from internal hardware
447 .de (hw2reg.alert_info_ctrl.en.de),
448 .d (hw2reg.alert_info_ctrl.en.d),
449
450 // to internal hardware
451 .qe (),
452 .q (reg2hw.alert_info_ctrl.en.q),
453 .ds (),
454
455 // to register interface (read)
456 .qs (alert_info_ctrl_en_qs)
457 );
458
459 // F[index]: 7:4
460 prim_subreg #(
461 .DW (4),
462 .SwAccess(prim_subreg_pkg::SwAccessRW),
463 .RESVAL (4'h0),
464 .Mubi (1'b0)
465 ) u_alert_info_ctrl_index (
466 // sync clock and reset required for this register
467 .clk_i (clk_por_i),
468 .rst_ni (rst_por_ni),
469
470 // from register interface
471 .we (alert_info_ctrl_gated_we),
472 .wd (alert_info_ctrl_index_wd),
473
474 // from internal hardware
475 .de (1'b0),
476 .d ('0),
477
478 // to internal hardware
479 .qe (),
480 .q (reg2hw.alert_info_ctrl.index.q),
481 .ds (),
482
483 // to register interface (read)
484 .qs (alert_info_ctrl_index_qs)
485 );
486
487
488 // R[alert_info_attr]: V(True)
489 prim_subreg_ext #(
490 .DW (4)
491 ) u_alert_info_attr (
492 .re (alert_info_attr_re),
493 .we (1'b0),
494 .wd ('0),
495 .d (hw2reg.alert_info_attr.d),
496 .qre (),
497 .qe (),
498 .q (),
499 .ds (),
500 .qs (alert_info_attr_qs)
501 );
502
503
504 // R[alert_info]: V(True)
505 prim_subreg_ext #(
506 .DW (32)
507 ) u_alert_info (
508 .re (alert_info_re),
509 .we (1'b0),
510 .wd ('0),
511 .d (hw2reg.alert_info.d),
512 .qre (),
513 .qe (),
514 .q (),
515 .ds (),
516 .qs (alert_info_qs)
517 );
518
519
520 // R[cpu_regwen]: V(False)
521 prim_subreg #(
522 .DW (1),
523 .SwAccess(prim_subreg_pkg::SwAccessW0C),
524 .RESVAL (1'h1),
525 .Mubi (1'b0)
526 ) u_cpu_regwen (
527 .clk_i (clk_i),
528 .rst_ni (rst_ni),
529
530 // from register interface
531 .we (cpu_regwen_we),
532 .wd (cpu_regwen_wd),
533
534 // from internal hardware
535 .de (1'b0),
536 .d ('0),
537
538 // to internal hardware
539 .qe (),
540 .q (),
541 .ds (),
542
543 // to register interface (read)
544 .qs (cpu_regwen_qs)
545 );
546
547
548 // R[cpu_info_ctrl]: V(False)
549 // Create REGWEN-gated WE signal
550 logic cpu_info_ctrl_gated_we;
551 1/1 assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs;
Tests: T1 T3 T5
552 // F[en]: 0:0
553 prim_subreg #(
554 .DW (1),
555 .SwAccess(prim_subreg_pkg::SwAccessRW),
556 .RESVAL (1'h0),
557 .Mubi (1'b0)
558 ) u_cpu_info_ctrl_en (
559 // sync clock and reset required for this register
560 .clk_i (clk_por_i),
561 .rst_ni (rst_por_ni),
562
563 // from register interface
564 .we (cpu_info_ctrl_gated_we),
565 .wd (cpu_info_ctrl_en_wd),
566
567 // from internal hardware
568 .de (hw2reg.cpu_info_ctrl.en.de),
569 .d (hw2reg.cpu_info_ctrl.en.d),
570
571 // to internal hardware
572 .qe (),
573 .q (reg2hw.cpu_info_ctrl.en.q),
574 .ds (),
575
576 // to register interface (read)
577 .qs (cpu_info_ctrl_en_qs)
578 );
579
580 // F[index]: 7:4
581 prim_subreg #(
582 .DW (4),
583 .SwAccess(prim_subreg_pkg::SwAccessRW),
584 .RESVAL (4'h0),
585 .Mubi (1'b0)
586 ) u_cpu_info_ctrl_index (
587 // sync clock and reset required for this register
588 .clk_i (clk_por_i),
589 .rst_ni (rst_por_ni),
590
591 // from register interface
592 .we (cpu_info_ctrl_gated_we),
593 .wd (cpu_info_ctrl_index_wd),
594
595 // from internal hardware
596 .de (1'b0),
597 .d ('0),
598
599 // to internal hardware
600 .qe (),
601 .q (reg2hw.cpu_info_ctrl.index.q),
602 .ds (),
603
604 // to register interface (read)
605 .qs (cpu_info_ctrl_index_qs)
606 );
607
608
609 // R[cpu_info_attr]: V(True)
610 prim_subreg_ext #(
611 .DW (4)
612 ) u_cpu_info_attr (
613 .re (cpu_info_attr_re),
614 .we (1'b0),
615 .wd ('0),
616 .d (hw2reg.cpu_info_attr.d),
617 .qre (),
618 .qe (),
619 .q (),
620 .ds (),
621 .qs (cpu_info_attr_qs)
622 );
623
624
625 // R[cpu_info]: V(True)
626 prim_subreg_ext #(
627 .DW (32)
628 ) u_cpu_info (
629 .re (cpu_info_re),
630 .we (1'b0),
631 .wd ('0),
632 .d (hw2reg.cpu_info.d),
633 .qre (),
634 .qe (),
635 .q (),
636 .ds (),
637 .qs (cpu_info_qs)
638 );
639
640
641 // Subregister 0 of Multireg sw_rst_regwen
642 // R[sw_rst_regwen_0]: V(False)
643 prim_subreg #(
644 .DW (1),
645 .SwAccess(prim_subreg_pkg::SwAccessW0C),
646 .RESVAL (1'h1),
647 .Mubi (1'b0)
648 ) u_sw_rst_regwen_0 (
649 .clk_i (clk_i),
650 .rst_ni (rst_ni),
651
652 // from register interface
653 .we (sw_rst_regwen_0_we),
654 .wd (sw_rst_regwen_0_wd),
655
656 // from internal hardware
657 .de (1'b0),
658 .d ('0),
659
660 // to internal hardware
661 .qe (),
662 .q (),
663 .ds (),
664
665 // to register interface (read)
666 .qs (sw_rst_regwen_0_qs)
667 );
668
669
670 // Subregister 1 of Multireg sw_rst_regwen
671 // R[sw_rst_regwen_1]: V(False)
672 prim_subreg #(
673 .DW (1),
674 .SwAccess(prim_subreg_pkg::SwAccessW0C),
675 .RESVAL (1'h1),
676 .Mubi (1'b0)
677 ) u_sw_rst_regwen_1 (
678 .clk_i (clk_i),
679 .rst_ni (rst_ni),
680
681 // from register interface
682 .we (sw_rst_regwen_1_we),
683 .wd (sw_rst_regwen_1_wd),
684
685 // from internal hardware
686 .de (1'b0),
687 .d ('0),
688
689 // to internal hardware
690 .qe (),
691 .q (),
692 .ds (),
693
694 // to register interface (read)
695 .qs (sw_rst_regwen_1_qs)
696 );
697
698
699 // Subregister 2 of Multireg sw_rst_regwen
700 // R[sw_rst_regwen_2]: V(False)
701 prim_subreg #(
702 .DW (1),
703 .SwAccess(prim_subreg_pkg::SwAccessW0C),
704 .RESVAL (1'h1),
705 .Mubi (1'b0)
706 ) u_sw_rst_regwen_2 (
707 .clk_i (clk_i),
708 .rst_ni (rst_ni),
709
710 // from register interface
711 .we (sw_rst_regwen_2_we),
712 .wd (sw_rst_regwen_2_wd),
713
714 // from internal hardware
715 .de (1'b0),
716 .d ('0),
717
718 // to internal hardware
719 .qe (),
720 .q (),
721 .ds (),
722
723 // to register interface (read)
724 .qs (sw_rst_regwen_2_qs)
725 );
726
727
728 // Subregister 3 of Multireg sw_rst_regwen
729 // R[sw_rst_regwen_3]: V(False)
730 prim_subreg #(
731 .DW (1),
732 .SwAccess(prim_subreg_pkg::SwAccessW0C),
733 .RESVAL (1'h1),
734 .Mubi (1'b0)
735 ) u_sw_rst_regwen_3 (
736 .clk_i (clk_i),
737 .rst_ni (rst_ni),
738
739 // from register interface
740 .we (sw_rst_regwen_3_we),
741 .wd (sw_rst_regwen_3_wd),
742
743 // from internal hardware
744 .de (1'b0),
745 .d ('0),
746
747 // to internal hardware
748 .qe (),
749 .q (),
750 .ds (),
751
752 // to register interface (read)
753 .qs (sw_rst_regwen_3_qs)
754 );
755
756
757 // Subregister 4 of Multireg sw_rst_regwen
758 // R[sw_rst_regwen_4]: V(False)
759 prim_subreg #(
760 .DW (1),
761 .SwAccess(prim_subreg_pkg::SwAccessW0C),
762 .RESVAL (1'h1),
763 .Mubi (1'b0)
764 ) u_sw_rst_regwen_4 (
765 .clk_i (clk_i),
766 .rst_ni (rst_ni),
767
768 // from register interface
769 .we (sw_rst_regwen_4_we),
770 .wd (sw_rst_regwen_4_wd),
771
772 // from internal hardware
773 .de (1'b0),
774 .d ('0),
775
776 // to internal hardware
777 .qe (),
778 .q (),
779 .ds (),
780
781 // to register interface (read)
782 .qs (sw_rst_regwen_4_qs)
783 );
784
785
786 // Subregister 5 of Multireg sw_rst_regwen
787 // R[sw_rst_regwen_5]: V(False)
788 prim_subreg #(
789 .DW (1),
790 .SwAccess(prim_subreg_pkg::SwAccessW0C),
791 .RESVAL (1'h1),
792 .Mubi (1'b0)
793 ) u_sw_rst_regwen_5 (
794 .clk_i (clk_i),
795 .rst_ni (rst_ni),
796
797 // from register interface
798 .we (sw_rst_regwen_5_we),
799 .wd (sw_rst_regwen_5_wd),
800
801 // from internal hardware
802 .de (1'b0),
803 .d ('0),
804
805 // to internal hardware
806 .qe (),
807 .q (),
808 .ds (),
809
810 // to register interface (read)
811 .qs (sw_rst_regwen_5_qs)
812 );
813
814
815 // Subregister 6 of Multireg sw_rst_regwen
816 // R[sw_rst_regwen_6]: V(False)
817 prim_subreg #(
818 .DW (1),
819 .SwAccess(prim_subreg_pkg::SwAccessW0C),
820 .RESVAL (1'h1),
821 .Mubi (1'b0)
822 ) u_sw_rst_regwen_6 (
823 .clk_i (clk_i),
824 .rst_ni (rst_ni),
825
826 // from register interface
827 .we (sw_rst_regwen_6_we),
828 .wd (sw_rst_regwen_6_wd),
829
830 // from internal hardware
831 .de (1'b0),
832 .d ('0),
833
834 // to internal hardware
835 .qe (),
836 .q (),
837 .ds (),
838
839 // to register interface (read)
840 .qs (sw_rst_regwen_6_qs)
841 );
842
843
844 // Subregister 7 of Multireg sw_rst_regwen
845 // R[sw_rst_regwen_7]: V(False)
846 prim_subreg #(
847 .DW (1),
848 .SwAccess(prim_subreg_pkg::SwAccessW0C),
849 .RESVAL (1'h1),
850 .Mubi (1'b0)
851 ) u_sw_rst_regwen_7 (
852 .clk_i (clk_i),
853 .rst_ni (rst_ni),
854
855 // from register interface
856 .we (sw_rst_regwen_7_we),
857 .wd (sw_rst_regwen_7_wd),
858
859 // from internal hardware
860 .de (1'b0),
861 .d ('0),
862
863 // to internal hardware
864 .qe (),
865 .q (),
866 .ds (),
867
868 // to register interface (read)
869 .qs (sw_rst_regwen_7_qs)
870 );
871
872
873 // Subregister 0 of Multireg sw_rst_ctrl_n
874 // R[sw_rst_ctrl_n_0]: V(False)
875 // Create REGWEN-gated WE signal
876 logic sw_rst_ctrl_n_0_gated_we;
877 1/1 assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs;
Tests: T1 T5 T6
878 prim_subreg #(
879 .DW (1),
880 .SwAccess(prim_subreg_pkg::SwAccessRW),
881 .RESVAL (1'h1),
882 .Mubi (1'b0)
883 ) u_sw_rst_ctrl_n_0 (
884 .clk_i (clk_i),
885 .rst_ni (rst_ni),
886
887 // from register interface
888 .we (sw_rst_ctrl_n_0_gated_we),
889 .wd (sw_rst_ctrl_n_0_wd),
890
891 // from internal hardware
892 .de (1'b0),
893 .d ('0),
894
895 // to internal hardware
896 .qe (),
897 .q (reg2hw.sw_rst_ctrl_n[0].q),
898 .ds (),
899
900 // to register interface (read)
901 .qs (sw_rst_ctrl_n_0_qs)
902 );
903
904
905 // Subregister 1 of Multireg sw_rst_ctrl_n
906 // R[sw_rst_ctrl_n_1]: V(False)
907 // Create REGWEN-gated WE signal
908 logic sw_rst_ctrl_n_1_gated_we;
909 1/1 assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs;
Tests: T1 T5 T6
910 prim_subreg #(
911 .DW (1),
912 .SwAccess(prim_subreg_pkg::SwAccessRW),
913 .RESVAL (1'h1),
914 .Mubi (1'b0)
915 ) u_sw_rst_ctrl_n_1 (
916 .clk_i (clk_i),
917 .rst_ni (rst_ni),
918
919 // from register interface
920 .we (sw_rst_ctrl_n_1_gated_we),
921 .wd (sw_rst_ctrl_n_1_wd),
922
923 // from internal hardware
924 .de (1'b0),
925 .d ('0),
926
927 // to internal hardware
928 .qe (),
929 .q (reg2hw.sw_rst_ctrl_n[1].q),
930 .ds (),
931
932 // to register interface (read)
933 .qs (sw_rst_ctrl_n_1_qs)
934 );
935
936
937 // Subregister 2 of Multireg sw_rst_ctrl_n
938 // R[sw_rst_ctrl_n_2]: V(False)
939 // Create REGWEN-gated WE signal
940 logic sw_rst_ctrl_n_2_gated_we;
941 1/1 assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs;
Tests: T1 T5 T6
942 prim_subreg #(
943 .DW (1),
944 .SwAccess(prim_subreg_pkg::SwAccessRW),
945 .RESVAL (1'h1),
946 .Mubi (1'b0)
947 ) u_sw_rst_ctrl_n_2 (
948 .clk_i (clk_i),
949 .rst_ni (rst_ni),
950
951 // from register interface
952 .we (sw_rst_ctrl_n_2_gated_we),
953 .wd (sw_rst_ctrl_n_2_wd),
954
955 // from internal hardware
956 .de (1'b0),
957 .d ('0),
958
959 // to internal hardware
960 .qe (),
961 .q (reg2hw.sw_rst_ctrl_n[2].q),
962 .ds (),
963
964 // to register interface (read)
965 .qs (sw_rst_ctrl_n_2_qs)
966 );
967
968
969 // Subregister 3 of Multireg sw_rst_ctrl_n
970 // R[sw_rst_ctrl_n_3]: V(False)
971 // Create REGWEN-gated WE signal
972 logic sw_rst_ctrl_n_3_gated_we;
973 1/1 assign sw_rst_ctrl_n_3_gated_we = sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs;
Tests: T1 T5 T6
974 prim_subreg #(
975 .DW (1),
976 .SwAccess(prim_subreg_pkg::SwAccessRW),
977 .RESVAL (1'h1),
978 .Mubi (1'b0)
979 ) u_sw_rst_ctrl_n_3 (
980 .clk_i (clk_i),
981 .rst_ni (rst_ni),
982
983 // from register interface
984 .we (sw_rst_ctrl_n_3_gated_we),
985 .wd (sw_rst_ctrl_n_3_wd),
986
987 // from internal hardware
988 .de (1'b0),
989 .d ('0),
990
991 // to internal hardware
992 .qe (),
993 .q (reg2hw.sw_rst_ctrl_n[3].q),
994 .ds (),
995
996 // to register interface (read)
997 .qs (sw_rst_ctrl_n_3_qs)
998 );
999
1000
1001 // Subregister 4 of Multireg sw_rst_ctrl_n
1002 // R[sw_rst_ctrl_n_4]: V(False)
1003 // Create REGWEN-gated WE signal
1004 logic sw_rst_ctrl_n_4_gated_we;
1005 1/1 assign sw_rst_ctrl_n_4_gated_we = sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs;
Tests: T1 T5 T6
1006 prim_subreg #(
1007 .DW (1),
1008 .SwAccess(prim_subreg_pkg::SwAccessRW),
1009 .RESVAL (1'h1),
1010 .Mubi (1'b0)
1011 ) u_sw_rst_ctrl_n_4 (
1012 .clk_i (clk_i),
1013 .rst_ni (rst_ni),
1014
1015 // from register interface
1016 .we (sw_rst_ctrl_n_4_gated_we),
1017 .wd (sw_rst_ctrl_n_4_wd),
1018
1019 // from internal hardware
1020 .de (1'b0),
1021 .d ('0),
1022
1023 // to internal hardware
1024 .qe (),
1025 .q (reg2hw.sw_rst_ctrl_n[4].q),
1026 .ds (),
1027
1028 // to register interface (read)
1029 .qs (sw_rst_ctrl_n_4_qs)
1030 );
1031
1032
1033 // Subregister 5 of Multireg sw_rst_ctrl_n
1034 // R[sw_rst_ctrl_n_5]: V(False)
1035 // Create REGWEN-gated WE signal
1036 logic sw_rst_ctrl_n_5_gated_we;
1037 1/1 assign sw_rst_ctrl_n_5_gated_we = sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs;
Tests: T1 T5 T6
1038 prim_subreg #(
1039 .DW (1),
1040 .SwAccess(prim_subreg_pkg::SwAccessRW),
1041 .RESVAL (1'h1),
1042 .Mubi (1'b0)
1043 ) u_sw_rst_ctrl_n_5 (
1044 .clk_i (clk_i),
1045 .rst_ni (rst_ni),
1046
1047 // from register interface
1048 .we (sw_rst_ctrl_n_5_gated_we),
1049 .wd (sw_rst_ctrl_n_5_wd),
1050
1051 // from internal hardware
1052 .de (1'b0),
1053 .d ('0),
1054
1055 // to internal hardware
1056 .qe (),
1057 .q (reg2hw.sw_rst_ctrl_n[5].q),
1058 .ds (),
1059
1060 // to register interface (read)
1061 .qs (sw_rst_ctrl_n_5_qs)
1062 );
1063
1064
1065 // Subregister 6 of Multireg sw_rst_ctrl_n
1066 // R[sw_rst_ctrl_n_6]: V(False)
1067 // Create REGWEN-gated WE signal
1068 logic sw_rst_ctrl_n_6_gated_we;
1069 1/1 assign sw_rst_ctrl_n_6_gated_we = sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs;
Tests: T1 T5 T6
1070 prim_subreg #(
1071 .DW (1),
1072 .SwAccess(prim_subreg_pkg::SwAccessRW),
1073 .RESVAL (1'h1),
1074 .Mubi (1'b0)
1075 ) u_sw_rst_ctrl_n_6 (
1076 .clk_i (clk_i),
1077 .rst_ni (rst_ni),
1078
1079 // from register interface
1080 .we (sw_rst_ctrl_n_6_gated_we),
1081 .wd (sw_rst_ctrl_n_6_wd),
1082
1083 // from internal hardware
1084 .de (1'b0),
1085 .d ('0),
1086
1087 // to internal hardware
1088 .qe (),
1089 .q (reg2hw.sw_rst_ctrl_n[6].q),
1090 .ds (),
1091
1092 // to register interface (read)
1093 .qs (sw_rst_ctrl_n_6_qs)
1094 );
1095
1096
1097 // Subregister 7 of Multireg sw_rst_ctrl_n
1098 // R[sw_rst_ctrl_n_7]: V(False)
1099 // Create REGWEN-gated WE signal
1100 logic sw_rst_ctrl_n_7_gated_we;
1101 1/1 assign sw_rst_ctrl_n_7_gated_we = sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs;
Tests: T1 T5 T6
1102 prim_subreg #(
1103 .DW (1),
1104 .SwAccess(prim_subreg_pkg::SwAccessRW),
1105 .RESVAL (1'h1),
1106 .Mubi (1'b0)
1107 ) u_sw_rst_ctrl_n_7 (
1108 .clk_i (clk_i),
1109 .rst_ni (rst_ni),
1110
1111 // from register interface
1112 .we (sw_rst_ctrl_n_7_gated_we),
1113 .wd (sw_rst_ctrl_n_7_wd),
1114
1115 // from internal hardware
1116 .de (1'b0),
1117 .d ('0),
1118
1119 // to internal hardware
1120 .qe (),
1121 .q (reg2hw.sw_rst_ctrl_n[7].q),
1122 .ds (),
1123
1124 // to register interface (read)
1125 .qs (sw_rst_ctrl_n_7_qs)
1126 );
1127
1128
1129 // R[err_code]: V(False)
1130 // F[reg_intg_err]: 0:0
1131 prim_subreg #(
1132 .DW (1),
1133 .SwAccess(prim_subreg_pkg::SwAccessRO),
1134 .RESVAL (1'h0),
1135 .Mubi (1'b0)
1136 ) u_err_code_reg_intg_err (
1137 .clk_i (clk_i),
1138 .rst_ni (rst_ni),
1139
1140 // from register interface
1141 .we (1'b0),
1142 .wd ('0),
1143
1144 // from internal hardware
1145 .de (hw2reg.err_code.reg_intg_err.de),
1146 .d (hw2reg.err_code.reg_intg_err.d),
1147
1148 // to internal hardware
1149 .qe (),
1150 .q (reg2hw.err_code.reg_intg_err.q),
1151 .ds (),
1152
1153 // to register interface (read)
1154 .qs (err_code_reg_intg_err_qs)
1155 );
1156
1157 // F[reset_consistency_err]: 1:1
1158 prim_subreg #(
1159 .DW (1),
1160 .SwAccess(prim_subreg_pkg::SwAccessRO),
1161 .RESVAL (1'h0),
1162 .Mubi (1'b0)
1163 ) u_err_code_reset_consistency_err (
1164 .clk_i (clk_i),
1165 .rst_ni (rst_ni),
1166
1167 // from register interface
1168 .we (1'b0),
1169 .wd ('0),
1170
1171 // from internal hardware
1172 .de (hw2reg.err_code.reset_consistency_err.de),
1173 .d (hw2reg.err_code.reset_consistency_err.d),
1174
1175 // to internal hardware
1176 .qe (),
1177 .q (reg2hw.err_code.reset_consistency_err.q),
1178 .ds (),
1179
1180 // to register interface (read)
1181 .qs (err_code_reset_consistency_err_qs)
1182 );
1183
1184 // F[fsm_err]: 2:2
1185 prim_subreg #(
1186 .DW (1),
1187 .SwAccess(prim_subreg_pkg::SwAccessRO),
1188 .RESVAL (1'h0),
1189 .Mubi (1'b0)
1190 ) u_err_code_fsm_err (
1191 .clk_i (clk_i),
1192 .rst_ni (rst_ni),
1193
1194 // from register interface
1195 .we (1'b0),
1196 .wd ('0),
1197
1198 // from internal hardware
1199 .de (hw2reg.err_code.fsm_err.de),
1200 .d (hw2reg.err_code.fsm_err.d),
1201
1202 // to internal hardware
1203 .qe (),
1204 .q (reg2hw.err_code.fsm_err.q),
1205 .ds (),
1206
1207 // to register interface (read)
1208 .qs (err_code_fsm_err_qs)
1209 );
1210
1211
1212
1213 logic [27:0] addr_hit;
1214 always_comb begin
1215 1/1 addr_hit = '0;
Tests: T1 T2 T3
1216 1/1 addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1217 1/1 addr_hit[ 1] = (reg_addr == RSTMGR_RESET_REQ_OFFSET);
Tests: T1 T2 T3
1218 1/1 addr_hit[ 2] = (reg_addr == RSTMGR_RESET_INFO_OFFSET);
Tests: T1 T2 T3
1219 1/1 addr_hit[ 3] = (reg_addr == RSTMGR_ALERT_REGWEN_OFFSET);
Tests: T1 T2 T3
1220 1/1 addr_hit[ 4] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET);
Tests: T1 T2 T3
1221 1/1 addr_hit[ 5] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET);
Tests: T1 T2 T3
1222 1/1 addr_hit[ 6] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET);
Tests: T1 T2 T3
1223 1/1 addr_hit[ 7] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET);
Tests: T1 T2 T3
1224 1/1 addr_hit[ 8] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET);
Tests: T1 T2 T3
1225 1/1 addr_hit[ 9] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET);
Tests: T1 T2 T3
1226 1/1 addr_hit[10] = (reg_addr == RSTMGR_CPU_INFO_OFFSET);
Tests: T1 T2 T3
1227 1/1 addr_hit[11] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET);
Tests: T1 T2 T3
1228 1/1 addr_hit[12] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET);
Tests: T1 T2 T3
1229 1/1 addr_hit[13] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET);
Tests: T1 T2 T3
1230 1/1 addr_hit[14] = (reg_addr == RSTMGR_SW_RST_REGWEN_3_OFFSET);
Tests: T1 T2 T3
1231 1/1 addr_hit[15] = (reg_addr == RSTMGR_SW_RST_REGWEN_4_OFFSET);
Tests: T1 T2 T3
1232 1/1 addr_hit[16] = (reg_addr == RSTMGR_SW_RST_REGWEN_5_OFFSET);
Tests: T1 T2 T3
1233 1/1 addr_hit[17] = (reg_addr == RSTMGR_SW_RST_REGWEN_6_OFFSET);
Tests: T1 T2 T3
1234 1/1 addr_hit[18] = (reg_addr == RSTMGR_SW_RST_REGWEN_7_OFFSET);
Tests: T1 T2 T3
1235 1/1 addr_hit[19] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET);
Tests: T1 T2 T3
1236 1/1 addr_hit[20] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET);
Tests: T1 T2 T3
1237 1/1 addr_hit[21] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET);
Tests: T1 T2 T3
1238 1/1 addr_hit[22] = (reg_addr == RSTMGR_SW_RST_CTRL_N_3_OFFSET);
Tests: T1 T2 T3
1239 1/1 addr_hit[23] = (reg_addr == RSTMGR_SW_RST_CTRL_N_4_OFFSET);
Tests: T1 T2 T3
1240 1/1 addr_hit[24] = (reg_addr == RSTMGR_SW_RST_CTRL_N_5_OFFSET);
Tests: T1 T2 T3
1241 1/1 addr_hit[25] = (reg_addr == RSTMGR_SW_RST_CTRL_N_6_OFFSET);
Tests: T1 T2 T3
1242 1/1 addr_hit[26] = (reg_addr == RSTMGR_SW_RST_CTRL_N_7_OFFSET);
Tests: T1 T2 T3
1243 1/1 addr_hit[27] = (reg_addr == RSTMGR_ERR_CODE_OFFSET);
Tests: T1 T2 T3
1244 end
1245
1246 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1247
1248 // Check sub-word write is permitted
1249 always_comb begin
1250 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1251 ((addr_hit[ 0] & (|(RSTMGR_PERMIT[ 0] & ~reg_be))) |
1252 (addr_hit[ 1] & (|(RSTMGR_PERMIT[ 1] & ~reg_be))) |
1253 (addr_hit[ 2] & (|(RSTMGR_PERMIT[ 2] & ~reg_be))) |
1254 (addr_hit[ 3] & (|(RSTMGR_PERMIT[ 3] & ~reg_be))) |
1255 (addr_hit[ 4] & (|(RSTMGR_PERMIT[ 4] & ~reg_be))) |
1256 (addr_hit[ 5] & (|(RSTMGR_PERMIT[ 5] & ~reg_be))) |
1257 (addr_hit[ 6] & (|(RSTMGR_PERMIT[ 6] & ~reg_be))) |
1258 (addr_hit[ 7] & (|(RSTMGR_PERMIT[ 7] & ~reg_be))) |
1259 (addr_hit[ 8] & (|(RSTMGR_PERMIT[ 8] & ~reg_be))) |
1260 (addr_hit[ 9] & (|(RSTMGR_PERMIT[ 9] & ~reg_be))) |
1261 (addr_hit[10] & (|(RSTMGR_PERMIT[10] & ~reg_be))) |
1262 (addr_hit[11] & (|(RSTMGR_PERMIT[11] & ~reg_be))) |
1263 (addr_hit[12] & (|(RSTMGR_PERMIT[12] & ~reg_be))) |
1264 (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))) |
1265 (addr_hit[14] & (|(RSTMGR_PERMIT[14] & ~reg_be))) |
1266 (addr_hit[15] & (|(RSTMGR_PERMIT[15] & ~reg_be))) |
1267 (addr_hit[16] & (|(RSTMGR_PERMIT[16] & ~reg_be))) |
1268 (addr_hit[17] & (|(RSTMGR_PERMIT[17] & ~reg_be))) |
1269 (addr_hit[18] & (|(RSTMGR_PERMIT[18] & ~reg_be))) |
1270 (addr_hit[19] & (|(RSTMGR_PERMIT[19] & ~reg_be))) |
1271 (addr_hit[20] & (|(RSTMGR_PERMIT[20] & ~reg_be))) |
1272 (addr_hit[21] & (|(RSTMGR_PERMIT[21] & ~reg_be))) |
1273 (addr_hit[22] & (|(RSTMGR_PERMIT[22] & ~reg_be))) |
1274 (addr_hit[23] & (|(RSTMGR_PERMIT[23] & ~reg_be))) |
1275 (addr_hit[24] & (|(RSTMGR_PERMIT[24] & ~reg_be))) |
1276 (addr_hit[25] & (|(RSTMGR_PERMIT[25] & ~reg_be))) |
1277 (addr_hit[26] & (|(RSTMGR_PERMIT[26] & ~reg_be))) |
1278 (addr_hit[27] & (|(RSTMGR_PERMIT[27] & ~reg_be)))));
1279 end
1280
1281 // Generate write-enables
1282 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1283
1284 1/1 assign alert_test_fatal_fault_wd = reg_wdata[0];
Tests: T1 T2 T3
1285
1286 1/1 assign alert_test_fatal_cnsty_fault_wd = reg_wdata[1];
Tests: T1 T2 T3
1287 1/1 assign reset_req_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1288
1289 1/1 assign reset_req_wd = reg_wdata[3:0];
Tests: T1 T2 T3
1290 1/1 assign reset_info_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1291
1292 1/1 assign reset_info_por_wd = reg_wdata[0];
Tests: T1 T2 T3
1293
1294 1/1 assign reset_info_low_power_exit_wd = reg_wdata[1];
Tests: T1 T2 T3
1295
1296 1/1 assign reset_info_sw_reset_wd = reg_wdata[2];
Tests: T1 T2 T3
1297
1298 1/1 assign reset_info_hw_req_wd = reg_wdata[7:3];
Tests: T1 T2 T3
1299 1/1 assign alert_regwen_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1300
1301 1/1 assign alert_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1302 1/1 assign alert_info_ctrl_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1303
1304 1/1 assign alert_info_ctrl_en_wd = reg_wdata[0];
Tests: T1 T2 T3
1305
1306 1/1 assign alert_info_ctrl_index_wd = reg_wdata[7:4];
Tests: T1 T2 T3
1307 1/1 assign alert_info_attr_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
1308 1/1 assign alert_info_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
1309 1/1 assign cpu_regwen_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1310
1311 1/1 assign cpu_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
1312 1/1 assign cpu_info_ctrl_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1313
1314 1/1 assign cpu_info_ctrl_en_wd = reg_wdata[0];
Tests: T1 T2 T3
1315
1316 1/1 assign cpu_info_ctrl_index_wd = reg_wdata[7:4];
Tests: T1 T2 T3
1317 1/1 assign cpu_info_attr_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
1318 1/1 assign cpu_info_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
1319 1/1 assign sw_rst_regwen_0_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1320
1321 1/1 assign sw_rst_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1322 1/1 assign sw_rst_regwen_1_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1323
1324 1/1 assign sw_rst_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1325 1/1 assign sw_rst_regwen_2_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
1326
1327 1/1 assign sw_rst_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
1328 1/1 assign sw_rst_regwen_3_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
1329
1330 1/1 assign sw_rst_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
1331 1/1 assign sw_rst_regwen_4_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
1332
1333 1/1 assign sw_rst_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
1334 1/1 assign sw_rst_regwen_5_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
1335
1336 1/1 assign sw_rst_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
1337 1/1 assign sw_rst_regwen_6_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
1338
1339 1/1 assign sw_rst_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
1340 1/1 assign sw_rst_regwen_7_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
1341
1342 1/1 assign sw_rst_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
1343 1/1 assign sw_rst_ctrl_n_0_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
1344
1345 1/1 assign sw_rst_ctrl_n_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1346 1/1 assign sw_rst_ctrl_n_1_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
1347
1348 1/1 assign sw_rst_ctrl_n_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1349 1/1 assign sw_rst_ctrl_n_2_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
1350
1351 1/1 assign sw_rst_ctrl_n_2_wd = reg_wdata[0];
Tests: T1 T2 T3
1352 1/1 assign sw_rst_ctrl_n_3_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
1353
1354 1/1 assign sw_rst_ctrl_n_3_wd = reg_wdata[0];
Tests: T1 T2 T3
1355 1/1 assign sw_rst_ctrl_n_4_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
1356
1357 1/1 assign sw_rst_ctrl_n_4_wd = reg_wdata[0];
Tests: T1 T2 T3
1358 1/1 assign sw_rst_ctrl_n_5_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
1359
1360 1/1 assign sw_rst_ctrl_n_5_wd = reg_wdata[0];
Tests: T1 T2 T3
1361 1/1 assign sw_rst_ctrl_n_6_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
1362
1363 1/1 assign sw_rst_ctrl_n_6_wd = reg_wdata[0];
Tests: T1 T2 T3
1364 1/1 assign sw_rst_ctrl_n_7_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
1365
1366 1/1 assign sw_rst_ctrl_n_7_wd = reg_wdata[0];
Tests: T1 T2 T3
1367
1368 // Assign write-enables to checker logic vector.
1369 always_comb begin
1370 1/1 reg_we_check = '0;
Tests: T1 T3 T4
1371 1/1 reg_we_check[0] = alert_test_we;
Tests: T1 T3 T4
1372 1/1 reg_we_check[1] = reset_req_we;
Tests: T1 T3 T4
1373 1/1 reg_we_check[2] = reset_info_we;
Tests: T1 T3 T4
1374 1/1 reg_we_check[3] = alert_regwen_we;
Tests: T1 T3 T4
1375 1/1 reg_we_check[4] = alert_info_ctrl_gated_we;
Tests: T1 T3 T4
1376 1/1 reg_we_check[5] = 1'b0;
Tests: T1 T3 T4
1377 1/1 reg_we_check[6] = 1'b0;
Tests: T1 T3 T4
1378 1/1 reg_we_check[7] = cpu_regwen_we;
Tests: T1 T3 T4
1379 1/1 reg_we_check[8] = cpu_info_ctrl_gated_we;
Tests: T1 T3 T4
1380 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T3 T4
1381 1/1 reg_we_check[10] = 1'b0;
Tests: T1 T3 T4
1382 1/1 reg_we_check[11] = sw_rst_regwen_0_we;
Tests: T1 T3 T4
1383 1/1 reg_we_check[12] = sw_rst_regwen_1_we;
Tests: T1 T3 T4
1384 1/1 reg_we_check[13] = sw_rst_regwen_2_we;
Tests: T1 T3 T4
1385 1/1 reg_we_check[14] = sw_rst_regwen_3_we;
Tests: T1 T3 T4
1386 1/1 reg_we_check[15] = sw_rst_regwen_4_we;
Tests: T1 T3 T4
1387 1/1 reg_we_check[16] = sw_rst_regwen_5_we;
Tests: T1 T3 T4
1388 1/1 reg_we_check[17] = sw_rst_regwen_6_we;
Tests: T1 T3 T4
1389 1/1 reg_we_check[18] = sw_rst_regwen_7_we;
Tests: T1 T3 T4
1390 1/1 reg_we_check[19] = sw_rst_ctrl_n_0_gated_we;
Tests: T1 T3 T4
1391 1/1 reg_we_check[20] = sw_rst_ctrl_n_1_gated_we;
Tests: T1 T3 T4
1392 1/1 reg_we_check[21] = sw_rst_ctrl_n_2_gated_we;
Tests: T1 T3 T4
1393 1/1 reg_we_check[22] = sw_rst_ctrl_n_3_gated_we;
Tests: T1 T3 T4
1394 1/1 reg_we_check[23] = sw_rst_ctrl_n_4_gated_we;
Tests: T1 T3 T4
1395 1/1 reg_we_check[24] = sw_rst_ctrl_n_5_gated_we;
Tests: T1 T3 T4
1396 1/1 reg_we_check[25] = sw_rst_ctrl_n_6_gated_we;
Tests: T1 T3 T4
1397 1/1 reg_we_check[26] = sw_rst_ctrl_n_7_gated_we;
Tests: T1 T3 T4
1398 1/1 reg_we_check[27] = 1'b0;
Tests: T1 T3 T4
1399 end
1400
1401 // Read data return
1402 always_comb begin
1403 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1404 1/1 unique case (1'b1)
Tests: T1 T2 T3
1405 addr_hit[0]: begin
1406 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1407 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1408 end
1409
1410 addr_hit[1]: begin
1411 1/1 reg_rdata_next[3:0] = reset_req_qs;
Tests: T1 T2 T3
1412 end
1413
1414 addr_hit[2]: begin
1415 1/1 reg_rdata_next[0] = reset_info_por_qs;
Tests: T1 T2 T3
1416 1/1 reg_rdata_next[1] = reset_info_low_power_exit_qs;
Tests: T1 T2 T3
1417 1/1 reg_rdata_next[2] = reset_info_sw_reset_qs;
Tests: T1 T2 T3
1418 1/1 reg_rdata_next[7:3] = reset_info_hw_req_qs;
Tests: T1 T2 T3
1419 end
1420
1421 addr_hit[3]: begin
1422 1/1 reg_rdata_next[0] = alert_regwen_qs;
Tests: T1 T2 T3
1423 end
1424
1425 addr_hit[4]: begin
1426 1/1 reg_rdata_next[0] = alert_info_ctrl_en_qs;
Tests: T1 T2 T3
1427 1/1 reg_rdata_next[7:4] = alert_info_ctrl_index_qs;
Tests: T1 T2 T3
1428 end
1429
1430 addr_hit[5]: begin
1431 1/1 reg_rdata_next[3:0] = alert_info_attr_qs;
Tests: T1 T2 T3
1432 end
1433
1434 addr_hit[6]: begin
1435 1/1 reg_rdata_next[31:0] = alert_info_qs;
Tests: T1 T2 T3
1436 end
1437
1438 addr_hit[7]: begin
1439 1/1 reg_rdata_next[0] = cpu_regwen_qs;
Tests: T1 T2 T3
1440 end
1441
1442 addr_hit[8]: begin
1443 1/1 reg_rdata_next[0] = cpu_info_ctrl_en_qs;
Tests: T1 T2 T3
1444 1/1 reg_rdata_next[7:4] = cpu_info_ctrl_index_qs;
Tests: T1 T2 T3
1445 end
1446
1447 addr_hit[9]: begin
1448 1/1 reg_rdata_next[3:0] = cpu_info_attr_qs;
Tests: T1 T2 T3
1449 end
1450
1451 addr_hit[10]: begin
1452 1/1 reg_rdata_next[31:0] = cpu_info_qs;
Tests: T1 T2 T3
1453 end
1454
1455 addr_hit[11]: begin
1456 1/1 reg_rdata_next[0] = sw_rst_regwen_0_qs;
Tests: T1 T2 T3
1457 end
1458
1459 addr_hit[12]: begin
1460 1/1 reg_rdata_next[0] = sw_rst_regwen_1_qs;
Tests: T1 T2 T3
1461 end
1462
1463 addr_hit[13]: begin
1464 1/1 reg_rdata_next[0] = sw_rst_regwen_2_qs;
Tests: T1 T2 T3
1465 end
1466
1467 addr_hit[14]: begin
1468 1/1 reg_rdata_next[0] = sw_rst_regwen_3_qs;
Tests: T1 T2 T3
1469 end
1470
1471 addr_hit[15]: begin
1472 1/1 reg_rdata_next[0] = sw_rst_regwen_4_qs;
Tests: T1 T2 T3
1473 end
1474
1475 addr_hit[16]: begin
1476 1/1 reg_rdata_next[0] = sw_rst_regwen_5_qs;
Tests: T1 T2 T3
1477 end
1478
1479 addr_hit[17]: begin
1480 1/1 reg_rdata_next[0] = sw_rst_regwen_6_qs;
Tests: T1 T2 T3
1481 end
1482
1483 addr_hit[18]: begin
1484 1/1 reg_rdata_next[0] = sw_rst_regwen_7_qs;
Tests: T1 T2 T3
1485 end
1486
1487 addr_hit[19]: begin
1488 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_0_qs;
Tests: T1 T2 T3
1489 end
1490
1491 addr_hit[20]: begin
1492 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_1_qs;
Tests: T1 T2 T3
1493 end
1494
1495 addr_hit[21]: begin
1496 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_2_qs;
Tests: T1 T2 T3
1497 end
1498
1499 addr_hit[22]: begin
1500 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_3_qs;
Tests: T1 T2 T3
1501 end
1502
1503 addr_hit[23]: begin
1504 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_4_qs;
Tests: T1 T2 T3
1505 end
1506
1507 addr_hit[24]: begin
1508 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_5_qs;
Tests: T1 T2 T3
1509 end
1510
1511 addr_hit[25]: begin
1512 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_6_qs;
Tests: T1 T2 T3
1513 end
1514
1515 addr_hit[26]: begin
1516 1/1 reg_rdata_next[0] = sw_rst_ctrl_n_7_qs;
Tests: T1 T2 T3
1517 end
1518
1519 addr_hit[27]: begin
1520 1/1 reg_rdata_next[0] = err_code_reg_intg_err_qs;
Tests: T1 T2 T3
1521 1/1 reg_rdata_next[1] = err_code_reset_consistency_err_qs;
Tests: T1 T2 T3
1522 1/1 reg_rdata_next[2] = err_code_fsm_err_qs;
Tests: T1 T2 T3
1523 end
1524
1525 default: begin
1526 reg_rdata_next = '1;
1527 end
1528 endcase
1529 end
1530
1531 // shadow busy
1532 logic shadow_busy;
1533 assign shadow_busy = 1'b0;
1534
1535 // register busy
1536 unreachable assign reg_busy = shadow_busy;
1537
1538 // Unused signal tieoff
1539
1540 // wdata / byte enable are not always fully used
1541 // add a blanket unused statement to handle lint waivers
1542 logic unused_wdata;
1543 logic unused_be;
1544 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1545 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
rstmgr_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 329 | 329 | 100.00 |
| Logical | 329 | 329 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Module :
rstmgr_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
34 |
34 |
100.00 |
| TERNARY |
1246 |
2 |
2 |
100.00 |
| IF |
70 |
3 |
3 |
100.00 |
| CASE |
1404 |
29 |
29 |
100.00 |
1246 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
70 if (!rst_ni) begin
-1-
71 err_q <= '0;
==>
72 end else if (intg_err || reg_we_err) begin
-2-
73 err_q <= 1'b1;
==>
74 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T54,T74,T75 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1404 unique case (1'b1)
-1-
1405 addr_hit[0]: begin
1406 reg_rdata_next[0] = '0;
==>
1407 reg_rdata_next[1] = '0;
1408 end
1409
1410 addr_hit[1]: begin
1411 reg_rdata_next[3:0] = reset_req_qs;
==>
1412 end
1413
1414 addr_hit[2]: begin
1415 reg_rdata_next[0] = reset_info_por_qs;
==>
1416 reg_rdata_next[1] = reset_info_low_power_exit_qs;
1417 reg_rdata_next[2] = reset_info_sw_reset_qs;
1418 reg_rdata_next[7:3] = reset_info_hw_req_qs;
1419 end
1420
1421 addr_hit[3]: begin
1422 reg_rdata_next[0] = alert_regwen_qs;
==>
1423 end
1424
1425 addr_hit[4]: begin
1426 reg_rdata_next[0] = alert_info_ctrl_en_qs;
==>
1427 reg_rdata_next[7:4] = alert_info_ctrl_index_qs;
1428 end
1429
1430 addr_hit[5]: begin
1431 reg_rdata_next[3:0] = alert_info_attr_qs;
==>
1432 end
1433
1434 addr_hit[6]: begin
1435 reg_rdata_next[31:0] = alert_info_qs;
==>
1436 end
1437
1438 addr_hit[7]: begin
1439 reg_rdata_next[0] = cpu_regwen_qs;
==>
1440 end
1441
1442 addr_hit[8]: begin
1443 reg_rdata_next[0] = cpu_info_ctrl_en_qs;
==>
1444 reg_rdata_next[7:4] = cpu_info_ctrl_index_qs;
1445 end
1446
1447 addr_hit[9]: begin
1448 reg_rdata_next[3:0] = cpu_info_attr_qs;
==>
1449 end
1450
1451 addr_hit[10]: begin
1452 reg_rdata_next[31:0] = cpu_info_qs;
==>
1453 end
1454
1455 addr_hit[11]: begin
1456 reg_rdata_next[0] = sw_rst_regwen_0_qs;
==>
1457 end
1458
1459 addr_hit[12]: begin
1460 reg_rdata_next[0] = sw_rst_regwen_1_qs;
==>
1461 end
1462
1463 addr_hit[13]: begin
1464 reg_rdata_next[0] = sw_rst_regwen_2_qs;
==>
1465 end
1466
1467 addr_hit[14]: begin
1468 reg_rdata_next[0] = sw_rst_regwen_3_qs;
==>
1469 end
1470
1471 addr_hit[15]: begin
1472 reg_rdata_next[0] = sw_rst_regwen_4_qs;
==>
1473 end
1474
1475 addr_hit[16]: begin
1476 reg_rdata_next[0] = sw_rst_regwen_5_qs;
==>
1477 end
1478
1479 addr_hit[17]: begin
1480 reg_rdata_next[0] = sw_rst_regwen_6_qs;
==>
1481 end
1482
1483 addr_hit[18]: begin
1484 reg_rdata_next[0] = sw_rst_regwen_7_qs;
==>
1485 end
1486
1487 addr_hit[19]: begin
1488 reg_rdata_next[0] = sw_rst_ctrl_n_0_qs;
==>
1489 end
1490
1491 addr_hit[20]: begin
1492 reg_rdata_next[0] = sw_rst_ctrl_n_1_qs;
==>
1493 end
1494
1495 addr_hit[21]: begin
1496 reg_rdata_next[0] = sw_rst_ctrl_n_2_qs;
==>
1497 end
1498
1499 addr_hit[22]: begin
1500 reg_rdata_next[0] = sw_rst_ctrl_n_3_qs;
==>
1501 end
1502
1503 addr_hit[23]: begin
1504 reg_rdata_next[0] = sw_rst_ctrl_n_4_qs;
==>
1505 end
1506
1507 addr_hit[24]: begin
1508 reg_rdata_next[0] = sw_rst_ctrl_n_5_qs;
==>
1509 end
1510
1511 addr_hit[25]: begin
1512 reg_rdata_next[0] = sw_rst_ctrl_n_6_qs;
==>
1513 end
1514
1515 addr_hit[26]: begin
1516 reg_rdata_next[0] = sw_rst_ctrl_n_7_qs;
==>
1517 end
1518
1519 addr_hit[27]: begin
1520 reg_rdata_next[0] = err_code_reg_intg_err_qs;
==>
1521 reg_rdata_next[1] = err_code_reset_consistency_err_qs;
1522 reg_rdata_next[2] = err_code_fsm_err_qs;
1523 end
1524
1525 default: begin
1526 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| addr_hit[13] |
Covered |
T1,T2,T3 |
| addr_hit[14] |
Covered |
T1,T2,T3 |
| addr_hit[15] |
Covered |
T1,T2,T3 |
| addr_hit[16] |
Covered |
T1,T2,T3 |
| addr_hit[17] |
Covered |
T1,T2,T3 |
| addr_hit[18] |
Covered |
T1,T2,T3 |
| addr_hit[19] |
Covered |
T1,T2,T3 |
| addr_hit[20] |
Covered |
T1,T2,T3 |
| addr_hit[21] |
Covered |
T1,T2,T3 |
| addr_hit[22] |
Covered |
T1,T2,T3 |
| addr_hit[23] |
Covered |
T1,T2,T3 |
| addr_hit[24] |
Covered |
T1,T2,T3 |
| addr_hit[25] |
Covered |
T1,T2,T3 |
| addr_hit[26] |
Covered |
T1,T2,T3 |
| addr_hit[27] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rstmgr_reg_top
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11838790 |
968139 |
0 |
0 |
| T1 |
2730 |
379 |
0 |
0 |
| T2 |
3005 |
1 |
0 |
0 |
| T3 |
3427 |
212 |
0 |
0 |
| T4 |
1538 |
19 |
0 |
0 |
| T5 |
1794 |
84 |
0 |
0 |
| T6 |
2637 |
113 |
0 |
0 |
| T7 |
2819 |
1 |
0 |
0 |
| T8 |
2679 |
379 |
0 |
0 |
| T9 |
5310 |
0 |
0 |
0 |
| T10 |
6499 |
760 |
0 |
0 |
| T11 |
0 |
2366 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11838790 |
968023 |
0 |
0 |
| T1 |
2730 |
379 |
0 |
0 |
| T2 |
3005 |
1 |
0 |
0 |
| T3 |
3427 |
212 |
0 |
0 |
| T4 |
1538 |
19 |
0 |
0 |
| T5 |
1794 |
81 |
0 |
0 |
| T6 |
2637 |
113 |
0 |
0 |
| T7 |
2819 |
1 |
0 |
0 |
| T8 |
2679 |
379 |
0 |
0 |
| T9 |
5310 |
0 |
0 |
0 |
| T10 |
6499 |
760 |
0 |
0 |
| T11 |
0 |
2366 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11838790 |
518841 |
0 |
0 |
| T1 |
2730 |
186 |
0 |
0 |
| T2 |
3005 |
1 |
0 |
0 |
| T3 |
3427 |
99 |
0 |
0 |
| T4 |
1538 |
0 |
0 |
0 |
| T5 |
1794 |
38 |
0 |
0 |
| T6 |
2637 |
54 |
0 |
0 |
| T7 |
2819 |
1 |
0 |
0 |
| T8 |
2679 |
186 |
0 |
0 |
| T9 |
5310 |
0 |
0 |
0 |
| T10 |
6499 |
403 |
0 |
0 |
| T11 |
0 |
1366 |
0 |
0 |
| T12 |
0 |
99 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
11838790 |
449182 |
0 |
0 |
| T1 |
2730 |
193 |
0 |
0 |
| T2 |
3005 |
0 |
0 |
0 |
| T3 |
3427 |
113 |
0 |
0 |
| T4 |
1538 |
19 |
0 |
0 |
| T5 |
1794 |
43 |
0 |
0 |
| T6 |
2637 |
59 |
0 |
0 |
| T7 |
2819 |
0 |
0 |
0 |
| T8 |
2679 |
193 |
0 |
0 |
| T9 |
5310 |
0 |
0 |
0 |
| T10 |
6499 |
357 |
0 |
0 |
| T11 |
0 |
1000 |
0 |
0 |
| T12 |
0 |
113 |
0 |
0 |
| T57 |
0 |
14 |
0 |
0 |
