Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7983

1

T5

16

T11

8

T23

35

auto[1]

11233

1

T2

4

T3

4

T5

1

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5954	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6460	1			T1	1		T2	2		T3	2
reset_info_cp[2]	3000	1			T2	1		T3	1		T9	1
reset_info_cp[4]	3885	1			T2	1		T3	1		T9	1
reset_info_cp[8]	122	1			T5	1		T11	1		T24	2
reset_info_cp[16]	103	1			T5	1		T11	1		T23	1
reset_info_cp[32]	110	1			T23	1		T27	1		T28	1
reset_info_cp[64]	110	1			T51	1		T36	1		T43	1
reset_info_cp[128]	92	1			T5	1		T51	1		T26	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3022	1			T23	6		T49	6		T51	19
reset_info_cp[1]	auto[1]	2818	1			T2	1		T3	1		T9	1
reset_info_cp[2]	auto[0]	899	1			T23	5		T49	3		T38	3
reset_info_cp[2]	auto[1]	2101	1			T2	1		T3	1		T9	1
reset_info_cp[4]	auto[0]	1365	1			T23	12		T49	4		T38	2
reset_info_cp[4]	auto[1]	2520	1			T2	1		T3	1		T9	1
reset_info_cp[8]	auto[0]	51	1			T5	1		T24	2		T98	1
reset_info_cp[8]	auto[1]	71	1			T11	1		T38	1		T43	1
reset_info_cp[16]	auto[0]	42	1			T5	1		T11	1		T23	1
reset_info_cp[16]	auto[1]	61	1			T53	1		T26	1		T38	1
reset_info_cp[32]	auto[0]	49	1			T23	1		T100	1		T102	2
reset_info_cp[32]	auto[1]	61	1			T27	1		T28	1		T132	1
reset_info_cp[64]	auto[0]	39	1			T36	1		T106	1		T142	1
reset_info_cp[64]	auto[1]	71	1			T51	1		T43	1		T28	4
reset_info_cp[128]	auto[0]	41	1			T5	1		T108	2		T110	1
reset_info_cp[128]	auto[1]	51	1			T51	1		T26	1		T27	1