| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T535 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.1166811879 | Aug 23 06:05:44 AM UTC 24 | Aug 23 06:06:08 AM UTC 24 | 7175126602 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3947853401 | Aug 23 06:05:48 AM UTC 24 | Aug 23 06:06:08 AM UTC 24 | 5149912831 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.3922212098 | Aug 23 06:05:40 AM UTC 24 | Aug 23 06:06:09 AM UTC 24 | 9069317351 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3653062405 | Aug 23 06:05:50 AM UTC 24 | Aug 23 06:06:09 AM UTC 24 | 4629605189 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.3596982354 | Aug 23 06:05:33 AM UTC 24 | Aug 23 06:06:23 AM UTC 24 | 14656437635 ps | ||
| T61 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.512822093 | Aug 23 12:23:51 PM UTC 24 | Aug 23 12:23:55 PM UTC 24 | 373822548 ps | ||
| T62 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.369504169 | Aug 23 12:23:52 PM UTC 24 | Aug 23 12:23:56 PM UTC 24 | 774997623 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3801711770 | Aug 23 12:23:54 PM UTC 24 | Aug 23 12:23:56 PM UTC 24 | 96647807 ps | ||
| T64 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.1840115872 | Aug 23 12:23:54 PM UTC 24 | Aug 23 12:23:56 PM UTC 24 | 79745191 ps | ||
| T65 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.996474257 | Aug 23 12:23:57 PM UTC 24 | Aug 23 12:23:59 PM UTC 24 | 193276124 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.470190467 | Aug 23 12:23:57 PM UTC 24 | Aug 23 12:23:59 PM UTC 24 | 239787204 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1824290042 | Aug 23 12:23:57 PM UTC 24 | Aug 23 12:23:59 PM UTC 24 | 258329194 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2918117981 | Aug 23 12:23:58 PM UTC 24 | Aug 23 12:24:00 PM UTC 24 | 161397133 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1576318068 | Aug 23 12:23:58 PM UTC 24 | Aug 23 12:24:00 PM UTC 24 | 470918432 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.3655191832 | Aug 23 12:24:00 PM UTC 24 | Aug 23 12:24:02 PM UTC 24 | 61904435 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3900474841 | Aug 23 12:24:00 PM UTC 24 | Aug 23 12:24:02 PM UTC 24 | 115610237 ps | ||
| T141 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1591104159 | Aug 23 12:23:57 PM UTC 24 | Aug 23 12:24:02 PM UTC 24 | 1025369130 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1080665555 | Aug 23 12:24:00 PM UTC 24 | Aug 23 12:24:03 PM UTC 24 | 162706674 ps | ||
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| T70 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2258683661 | Aug 23 12:24:01 PM UTC 24 | Aug 23 12:24:04 PM UTC 24 | 139112038 ps | ||
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| T544 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4199833678 | Aug 23 12:24:02 PM UTC 24 | Aug 23 12:24:04 PM UTC 24 | 102779204 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2081316510 | Aug 23 12:24:03 PM UTC 24 | Aug 23 12:24:05 PM UTC 24 | 80739320 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2504676599 | Aug 23 12:24:00 PM UTC 24 | Aug 23 12:24:05 PM UTC 24 | 1008870053 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.15864985 | Aug 23 12:24:03 PM UTC 24 | Aug 23 12:24:05 PM UTC 24 | 104822786 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3641131235 | Aug 23 12:24:02 PM UTC 24 | Aug 23 12:24:06 PM UTC 24 | 937663852 ps | ||
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| T547 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3690402988 | Aug 23 12:24:05 PM UTC 24 | Aug 23 12:24:06 PM UTC 24 | 118405138 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.121629865 | Aug 23 12:24:04 PM UTC 24 | Aug 23 12:24:07 PM UTC 24 | 188693524 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4218970401 | Aug 23 12:24:05 PM UTC 24 | Aug 23 12:24:07 PM UTC 24 | 425235877 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1325279146 | Aug 23 12:24:06 PM UTC 24 | Aug 23 12:24:08 PM UTC 24 | 98897994 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1786785321 | Aug 23 12:24:06 PM UTC 24 | Aug 23 12:24:08 PM UTC 24 | 132816185 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2636480926 | Aug 23 12:24:02 PM UTC 24 | Aug 23 12:24:08 PM UTC 24 | 1165333569 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3073287808 | Aug 23 12:24:06 PM UTC 24 | Aug 23 12:24:08 PM UTC 24 | 233157503 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.3352402920 | Aug 23 12:24:04 PM UTC 24 | Aug 23 12:24:09 PM UTC 24 | 482665538 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3059722662 | Aug 23 12:24:07 PM UTC 24 | Aug 23 12:24:09 PM UTC 24 | 92819469 ps | ||
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| T118 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.368655230 | Aug 23 12:24:08 PM UTC 24 | Aug 23 12:24:10 PM UTC 24 | 77027481 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2120315116 | Aug 23 12:24:07 PM UTC 24 | Aug 23 12:24:11 PM UTC 24 | 341198969 ps | ||
| T140 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1531370889 | Aug 23 12:24:07 PM UTC 24 | Aug 23 12:24:11 PM UTC 24 | 779545113 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2244182375 | Aug 23 12:24:08 PM UTC 24 | Aug 23 12:24:11 PM UTC 24 | 207106178 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1277144892 | Aug 23 12:24:08 PM UTC 24 | Aug 23 12:24:11 PM UTC 24 | 153400559 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.1325810208 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:11 PM UTC 24 | 61442267 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3136474553 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:12 PM UTC 24 | 140958039 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2797715266 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:12 PM UTC 24 | 99530123 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2310258182 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:12 PM UTC 24 | 107413939 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2655014567 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:12 PM UTC 24 | 113443513 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3982051935 | Aug 23 12:24:08 PM UTC 24 | Aug 23 12:24:12 PM UTC 24 | 271659054 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.186406747 | Aug 23 12:24:11 PM UTC 24 | Aug 23 12:24:13 PM UTC 24 | 86771689 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4100606752 | Aug 23 12:24:11 PM UTC 24 | Aug 23 12:24:13 PM UTC 24 | 131814836 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3120201152 | Aug 23 12:24:05 PM UTC 24 | Aug 23 12:24:13 PM UTC 24 | 1551242482 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.4055343423 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:21 PM UTC 24 | 71745656 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2266029846 | Aug 23 12:24:10 PM UTC 24 | Aug 23 12:24:14 PM UTC 24 | 867741606 ps | ||
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| T562 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.40414161 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:14 PM UTC 24 | 90953304 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1187169871 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:14 PM UTC 24 | 181480940 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.33654805 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:14 PM UTC 24 | 76896947 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2990110336 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:14 PM UTC 24 | 149361856 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1043038319 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:15 PM UTC 24 | 167198180 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.4269440770 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:15 PM UTC 24 | 228027634 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1599609691 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:15 PM UTC 24 | 224901859 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1436530932 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:15 PM UTC 24 | 444701351 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3582379065 | Aug 23 12:24:14 PM UTC 24 | Aug 23 12:24:15 PM UTC 24 | 70731716 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1904194042 | Aug 23 12:24:14 PM UTC 24 | Aug 23 12:24:16 PM UTC 24 | 57777006 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.677593101 | Aug 23 12:24:12 PM UTC 24 | Aug 23 12:24:16 PM UTC 24 | 925494785 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3806656537 | Aug 23 12:24:14 PM UTC 24 | Aug 23 12:24:16 PM UTC 24 | 202079310 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2571511500 | Aug 23 12:24:14 PM UTC 24 | Aug 23 12:24:16 PM UTC 24 | 510002381 ps | ||
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| T592 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2557152317 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:21 PM UTC 24 | 107913824 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1167807311 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:21 PM UTC 24 | 124193161 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1367252075 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:21 PM UTC 24 | 137034711 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3275617851 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:22 PM UTC 24 | 126357809 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1027894000 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:22 PM UTC 24 | 168656364 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.656933019 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:22 PM UTC 24 | 405326879 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2854206088 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:22 PM UTC 24 | 264738242 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1527593792 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:23 PM UTC 24 | 795211648 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2117370334 | Aug 23 12:24:19 PM UTC 24 | Aug 23 12:24:23 PM UTC 24 | 484535895 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2291239373 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:23 PM UTC 24 | 70118943 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1983863756 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:24 PM UTC 24 | 107649543 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2670538415 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:24 PM UTC 24 | 65526298 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3786219898 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:24 PM UTC 24 | 124577352 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2102841605 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:24 PM UTC 24 | 137953902 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.943010128 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:25 PM UTC 24 | 527156381 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2319951145 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:25 PM UTC 24 | 70446315 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.957442322 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:25 PM UTC 24 | 122499255 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3922457290 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:25 PM UTC 24 | 132315217 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.4208611560 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 432001532 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.2379052754 | Aug 23 12:24:24 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 78160819 ps | ||
| T139 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.588031253 | Aug 23 12:24:21 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 957991512 ps | ||
| T610 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3693091635 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 123119550 ps | ||
| T611 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3977511975 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 174998806 ps | ||
| T612 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2030946296 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:26 PM UTC 24 | 125665907 ps | ||
| T613 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.579795586 | Aug 23 12:24:23 PM UTC 24 | Aug 23 12:24:27 PM UTC 24 | 794542165 ps | ||
| T614 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2196419230 | Aug 23 12:24:24 PM UTC 24 | Aug 23 12:24:28 PM UTC 24 | 492651579 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2174112076 | Aug 23 12:24:24 PM UTC 24 | Aug 23 12:24:28 PM UTC 24 | 938914380 ps | ||
| T615 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.739424492 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:29 PM UTC 24 | 57910094 ps | ||
| T616 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4101543331 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:29 PM UTC 24 | 115873960 ps | ||
| T617 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3565705177 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:29 PM UTC 24 | 124905635 ps | ||
| T618 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1147537870 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:29 PM UTC 24 | 109530794 ps | ||
| T619 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2200789391 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:29 PM UTC 24 | 168873056 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1253559133 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:30 PM UTC 24 | 469202492 ps | ||
| T620 | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1842461436 | Aug 23 12:24:26 PM UTC 24 | Aug 23 12:24:30 PM UTC 24 | 332042453 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2270378388 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 107943578 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:47 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270378388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.2270378388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1424451969 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 451289717 ps |
| CPU time | 2.21 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:46 AM UTC 24 |
| Peak memory | 209060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424451969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.1424451969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.2092557022 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 630002538 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:49 AM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092557022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.2092557022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.996474257 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 193276124 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 12:23:57 PM UTC 24 |
| Finished | Aug 23 12:23:59 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=996474257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_wi th_rand_reset.996474257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.1150474249 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 8406436930 ps |
| CPU time | 11.58 seconds |
| Started | Aug 23 06:03:46 AM UTC 24 |
| Finished | Aug 23 06:03:59 AM UTC 24 |
| Peak memory | 241776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150474249 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.1150474249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.3134513764 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1273199531 ps |
| CPU time | 4.92 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:51 AM UTC 24 |
| Peak memory | 241980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134513764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3134513764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.3641131235 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 937663852 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 12:24:02 PM UTC 24 |
| Finished | Aug 23 12:24:06 PM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641131235 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.3641131235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4195467782 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 7991850639 ps |
| CPU time | 32.2 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:04:18 AM UTC 24 |
| Peak memory | 218108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195467782 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4195467782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.3352402920 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 482665538 ps |
| CPU time | 3.08 seconds |
| Started | Aug 23 12:24:04 PM UTC 24 |
| Finished | Aug 23 12:24:09 PM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352402920 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3352402920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.2829450701 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1950506023 ps |
| CPU time | 7.03 seconds |
| Started | Aug 23 06:03:47 AM UTC 24 |
| Finished | Aug 23 06:03:55 AM UTC 24 |
| Peak memory | 242364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829450701 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2829450701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2598703028 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 154831418 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:45 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598703028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2598703028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.803473715 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 77276304 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:46 AM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803473715 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.803473715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.2702430243 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 6720248761 ps |
| CPU time | 20.16 seconds |
| Started | Aug 23 06:03:54 AM UTC 24 |
| Finished | Aug 23 06:04:15 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702430243 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2702430243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.3595536411 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1273920334 ps |
| CPU time | 5.44 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:50 AM UTC 24 |
| Peak memory | 241900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595536411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3595536411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.656933019 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 405326879 ps |
| CPU time | 1.47 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:22 PM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656933019 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.656933019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3170856604 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 266900379 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:46 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170856604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.3170856604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.3020728328 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2268928817 ps |
| CPU time | 6.88 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:27 AM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020728328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3020728328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.1840115872 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 79745191 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 12:23:54 PM UTC 24 |
| Finished | Aug 23 12:23:56 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840115872 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1840115872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.3203420342 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 220693911 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 06:03:42 AM UTC 24 |
| Finished | Aug 23 06:03:44 AM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203420342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.3203420342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.512822093 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 373822548 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 12:23:51 PM UTC 24 |
| Finished | Aug 23 12:23:55 PM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512822093 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.512822093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2174112076 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 938914380 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 12:24:24 PM UTC 24 |
| Finished | Aug 23 12:24:28 PM UTC 24 |
| Peak memory | 208776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174112076 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.2174112076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1253559133 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 469202492 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:30 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253559133 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1253559133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1824290042 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 258329194 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 12:23:57 PM UTC 24 |
| Finished | Aug 23 12:23:59 PM UTC 24 |
| Peak memory | 207688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824290042 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1824290042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.1591104159 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1025369130 ps |
| CPU time | 4.73 seconds |
| Started | Aug 23 12:23:57 PM UTC 24 |
| Finished | Aug 23 12:24:02 PM UTC 24 |
| Peak memory | 225036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591104159 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.1591104159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3801711770 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 96647807 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 12:23:54 PM UTC 24 |
| Finished | Aug 23 12:23:56 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801711770 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3801711770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.470190467 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 239787204 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 12:23:57 PM UTC 24 |
| Finished | Aug 23 12:23:59 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470190467 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.470190467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.369504169 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 774997623 ps |
| CPU time | 2.46 seconds |
| Started | Aug 23 12:23:52 PM UTC 24 |
| Finished | Aug 23 12:23:56 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369504169 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.369504169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1080665555 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 162706674 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 12:24:00 PM UTC 24 |
| Finished | Aug 23 12:24:03 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080665555 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1080665555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2504676599 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1008870053 ps |
| CPU time | 4.17 seconds |
| Started | Aug 23 12:24:00 PM UTC 24 |
| Finished | Aug 23 12:24:05 PM UTC 24 |
| Peak memory | 225032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504676599 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2504676599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3900474841 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 115610237 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 12:24:00 PM UTC 24 |
| Finished | Aug 23 12:24:02 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900474841 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3900474841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2320603240 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 194404599 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 12:24:01 PM UTC 24 |
| Finished | Aug 23 12:24:03 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2320603240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.2320603240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.3655191832 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 61904435 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 12:24:00 PM UTC 24 |
| Finished | Aug 23 12:24:02 PM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655191832 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3655191832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.4165444020 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 245618603 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 12:24:01 PM UTC 24 |
| Finished | Aug 23 12:24:04 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165444020 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.4165444020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2918117981 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 161397133 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 12:23:58 PM UTC 24 |
| Finished | Aug 23 12:24:00 PM UTC 24 |
| Peak memory | 207844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918117981 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2918117981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.1576318068 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 470918432 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 12:23:58 PM UTC 24 |
| Finished | Aug 23 12:24:00 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576318068 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.1576318068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1035898424 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 166900968 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:18 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1035898424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_ with_rand_reset.1035898424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2734278282 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 61832639 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:17 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734278282 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2734278282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.1178348808 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 134162055 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:18 PM UTC 24 |
| Peak memory | 207840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178348808 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.1178348808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1492435044 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 318148899 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:18 PM UTC 24 |
| Peak memory | 217548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492435044 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1492435044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1195498757 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 424032275 ps |
| CPU time | 1.59 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:18 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195498757 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1195498757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.381208375 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 207356738 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:19 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=381208375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_w ith_rand_reset.381208375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1765408470 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 81038634 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:19 PM UTC 24 |
| Peak memory | 207380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765408470 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1765408470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.836129337 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 212571162 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:20 PM UTC 24 |
| Peak memory | 207320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836129337 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.836129337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1337923072 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 124071474 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:20 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337923072 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1337923072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2409995608 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 429411565 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:20 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409995608 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.2409995608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1027894000 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 168656364 ps |
| CPU time | 1.37 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:22 PM UTC 24 |
| Peak memory | 217660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1027894000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_ with_rand_reset.1027894000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.3748801426 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 75539243 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:19 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748801426 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.3748801426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.335621469 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 155649689 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:20 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335621469 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.335621469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2130433448 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 236784151 ps |
| CPU time | 2.86 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 222016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130433448 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2130433448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.687045721 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 491995034 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 12:24:17 PM UTC 24 |
| Finished | Aug 23 12:24:20 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687045721 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.687045721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2557152317 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 107913824 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2557152317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.2557152317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.4055343423 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 71745656 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055343423 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.4055343423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.1167807311 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 124193161 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 207840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167807311 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.1167807311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2854206088 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 264738242 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:22 PM UTC 24 |
| Peak memory | 217636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854206088 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2854206088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1527593792 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 795211648 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:23 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527593792 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.1527593792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1367252075 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 137034711 ps |
| CPU time | 0.9 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 216892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1367252075 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.1367252075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3545850409 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 63454169 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:21 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545850409 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3545850409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.3275617851 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 126357809 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:22 PM UTC 24 |
| Peak memory | 207040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275617851 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.3275617851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2117370334 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 484535895 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 12:24:19 PM UTC 24 |
| Finished | Aug 23 12:24:23 PM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117370334 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.2117370334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1983863756 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 107649543 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:24 PM UTC 24 |
| Peak memory | 207532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1983863756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.1983863756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2291239373 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 70118943 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:23 PM UTC 24 |
| Peak memory | 207308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291239373 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2291239373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3786219898 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 124577352 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:24 PM UTC 24 |
| Peak memory | 207840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786219898 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3786219898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.4208611560 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 432001532 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 225084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208611560 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.4208611560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.588031253 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 957991512 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588031253 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.588031253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3922457290 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 132315217 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:25 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3922457290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.3922457290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2670538415 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 65526298 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:24 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670538415 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2670538415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.957442322 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 122499255 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:25 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957442322 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.957442322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2102841605 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 137953902 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:24 PM UTC 24 |
| Peak memory | 225156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102841605 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2102841605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.943010128 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 527156381 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 12:24:21 PM UTC 24 |
| Finished | Aug 23 12:24:25 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943010128 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.943010128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3977511975 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 174998806 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3977511975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.3977511975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2319951145 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 70446315 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:25 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319951145 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2319951145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3693091635 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 123119550 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693091635 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.3693091635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2030946296 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 125665907 ps |
| CPU time | 1.59 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030946296 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2030946296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.579795586 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 794542165 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 12:24:23 PM UTC 24 |
| Finished | Aug 23 12:24:27 PM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579795586 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.579795586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4101543331 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 115873960 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:29 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4101543331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_ with_rand_reset.4101543331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.2379052754 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 78160819 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 12:24:24 PM UTC 24 |
| Finished | Aug 23 12:24:26 PM UTC 24 |
| Peak memory | 207716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379052754 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2379052754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.3565705177 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 124905635 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:29 PM UTC 24 |
| Peak memory | 207748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565705177 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.3565705177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2196419230 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 492651579 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 12:24:24 PM UTC 24 |
| Finished | Aug 23 12:24:28 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196419230 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2196419230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2200789391 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 168873056 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:29 PM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2200789391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.2200789391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.739424492 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 57910094 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:29 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739424492 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.739424492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.1147537870 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 109530794 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:29 PM UTC 24 |
| Peak memory | 207796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147537870 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.1147537870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1842461436 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 332042453 ps |
| CPU time | 2.17 seconds |
| Started | Aug 23 12:24:26 PM UTC 24 |
| Finished | Aug 23 12:24:30 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842461436 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1842461436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.15864985 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 104822786 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 12:24:03 PM UTC 24 |
| Finished | Aug 23 12:24:05 PM UTC 24 |
| Peak memory | 207652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15864985 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.15864985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2636480926 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1165333569 ps |
| CPU time | 4.91 seconds |
| Started | Aug 23 12:24:02 PM UTC 24 |
| Finished | Aug 23 12:24:08 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636480926 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2636480926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.4199833678 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 102779204 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 12:24:02 PM UTC 24 |
| Finished | Aug 23 12:24:04 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199833678 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.4199833678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.121629865 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 188693524 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 12:24:04 PM UTC 24 |
| Finished | Aug 23 12:24:07 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=121629865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_wi th_rand_reset.121629865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.927446180 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 69489690 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 12:24:02 PM UTC 24 |
| Finished | Aug 23 12:24:04 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927446180 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.927446180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2081316510 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 80739320 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 12:24:03 PM UTC 24 |
| Finished | Aug 23 12:24:05 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081316510 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2081316510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2258683661 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 139112038 ps |
| CPU time | 1.61 seconds |
| Started | Aug 23 12:24:01 PM UTC 24 |
| Finished | Aug 23 12:24:04 PM UTC 24 |
| Peak memory | 219708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258683661 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2258683661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3073287808 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 233157503 ps |
| CPU time | 1.47 seconds |
| Started | Aug 23 12:24:06 PM UTC 24 |
| Finished | Aug 23 12:24:08 PM UTC 24 |
| Peak memory | 207732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073287808 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3073287808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.3120201152 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 1551242482 ps |
| CPU time | 7.36 seconds |
| Started | Aug 23 12:24:05 PM UTC 24 |
| Finished | Aug 23 12:24:13 PM UTC 24 |
| Peak memory | 208780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120201152 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.3120201152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3690402988 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 118405138 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 12:24:05 PM UTC 24 |
| Finished | Aug 23 12:24:06 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690402988 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3690402988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.1786785321 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 132816185 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 12:24:06 PM UTC 24 |
| Finished | Aug 23 12:24:08 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1786785321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.1786785321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.3235114156 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 56200300 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 12:24:05 PM UTC 24 |
| Finished | Aug 23 12:24:06 PM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235114156 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.3235114156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1325279146 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 98897994 ps |
| CPU time | 1 seconds |
| Started | Aug 23 12:24:06 PM UTC 24 |
| Finished | Aug 23 12:24:08 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325279146 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1325279146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.4218970401 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 425235877 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 12:24:05 PM UTC 24 |
| Finished | Aug 23 12:24:07 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218970401 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.4218970401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1277144892 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 153400559 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 12:24:08 PM UTC 24 |
| Finished | Aug 23 12:24:11 PM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277144892 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1277144892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3982051935 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 271659054 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 12:24:08 PM UTC 24 |
| Finished | Aug 23 12:24:12 PM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982051935 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3982051935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3059722662 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 92819469 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 12:24:07 PM UTC 24 |
| Finished | Aug 23 12:24:09 PM UTC 24 |
| Peak memory | 207780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059722662 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3059722662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2244182375 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 207106178 ps |
| CPU time | 1.41 seconds |
| Started | Aug 23 12:24:08 PM UTC 24 |
| Finished | Aug 23 12:24:11 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2244182375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.2244182375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.4191178055 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 68787257 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 12:24:07 PM UTC 24 |
| Finished | Aug 23 12:24:09 PM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191178055 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.4191178055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.368655230 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 77027481 ps |
| CPU time | 0.9 seconds |
| Started | Aug 23 12:24:08 PM UTC 24 |
| Finished | Aug 23 12:24:10 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368655230 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.368655230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2120315116 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 341198969 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 12:24:07 PM UTC 24 |
| Finished | Aug 23 12:24:11 PM UTC 24 |
| Peak memory | 225220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120315116 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2120315116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1531370889 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 779545113 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 12:24:07 PM UTC 24 |
| Finished | Aug 23 12:24:11 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531370889 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1531370889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3136474553 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 140958039 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:12 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3136474553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.3136474553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.1325810208 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 61442267 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:11 PM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325810208 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.1325810208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2310258182 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 107413939 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:12 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310258182 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.2310258182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2797715266 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 99530123 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:12 PM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797715266 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2797715266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2165751697 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 930946611 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165751697 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.2165751697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1187169871 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 181480940 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 207712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1187169871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.1187169871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.186406747 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 86771689 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 12:24:11 PM UTC 24 |
| Finished | Aug 23 12:24:13 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186406747 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.186406747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4100606752 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 131814836 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 12:24:11 PM UTC 24 |
| Finished | Aug 23 12:24:13 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100606752 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.4100606752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2655014567 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 113443513 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:12 PM UTC 24 |
| Peak memory | 207796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655014567 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2655014567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2266029846 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 867741606 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 12:24:10 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266029846 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.2266029846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.1043038319 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 167198180 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:15 PM UTC 24 |
| Peak memory | 217640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1043038319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.1043038319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.40414161 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 90953304 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40414161 -assert nopostproc +UVM_TESTNAME=rstmgr_ base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.40414161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2990110336 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 149361856 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990110336 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2990110336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.4269440770 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 228027634 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:15 PM UTC 24 |
| Peak memory | 219680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269440770 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.4269440770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.677593101 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 925494785 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:16 PM UTC 24 |
| Peak memory | 208856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677593101 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.677593101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3806656537 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 202079310 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 12:24:14 PM UTC 24 |
| Finished | Aug 23 12:24:16 PM UTC 24 |
| Peak memory | 217468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3806656537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.3806656537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.33654805 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 76896947 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:14 PM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33654805 -assert nopostproc +UVM_TESTNAME=rstmgr_ base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.33654805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3582379065 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 70731716 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 12:24:14 PM UTC 24 |
| Finished | Aug 23 12:24:15 PM UTC 24 |
| Peak memory | 207776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582379065 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3582379065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.1599609691 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 224901859 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:15 PM UTC 24 |
| Peak memory | 217624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599609691 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.1599609691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.1436530932 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 444701351 ps |
| CPU time | 1.66 seconds |
| Started | Aug 23 12:24:12 PM UTC 24 |
| Finished | Aug 23 12:24:15 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436530932 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.1436530932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.3596509732 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 220828554 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:17 PM UTC 24 |
| Peak memory | 217568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3596509732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w ith_rand_reset.3596509732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1904194042 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 57777006 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 12:24:14 PM UTC 24 |
| Finished | Aug 23 12:24:16 PM UTC 24 |
| Peak memory | 207584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904194042 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1904194042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1192790184 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 237906449 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 12:24:15 PM UTC 24 |
| Finished | Aug 23 12:24:18 PM UTC 24 |
| Peak memory | 207728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192790184 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.1192790184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3258272700 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 357910427 ps |
| CPU time | 2.59 seconds |
| Started | Aug 23 12:24:14 PM UTC 24 |
| Finished | Aug 23 12:24:17 PM UTC 24 |
| Peak memory | 225320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258272700 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3258272700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2571511500 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 510002381 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 12:24:14 PM UTC 24 |
| Finished | Aug 23 12:24:16 PM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571511500 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.2571511500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2360371929 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 302615667 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:45 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360371929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2360371929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.3015322781 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1403840449 ps |
| CPU time | 4.74 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:03:49 AM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015322781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3015322781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2864917844 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 16799585935 ps |
| CPU time | 24.96 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:04:10 AM UTC 24 |
| Peak memory | 241872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864917844 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2864917844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.784237246 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 112946095 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 06:03:42 AM UTC 24 |
| Finished | Aug 23 06:03:44 AM UTC 24 |
| Peak memory | 208216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784237246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.784237246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.1528296283 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 9018277738 ps |
| CPU time | 31.89 seconds |
| Started | Aug 23 06:03:43 AM UTC 24 |
| Finished | Aug 23 06:04:17 AM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528296283 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1528296283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1537943038 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 71372879 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:03:46 AM UTC 24 |
| Finished | Aug 23 06:03:48 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537943038 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1537943038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.552330138 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 301158293 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:47 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552330138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.552330138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.370164843 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 166000101 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:46 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370164843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.370164843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.783035644 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 144449571 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:47 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783035644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.783035644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.958115328 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 368618161 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:48 AM UTC 24 |
| Peak memory | 208084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958115328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.958115328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1349824215 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 167910436 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 06:03:45 AM UTC 24 |
| Finished | Aug 23 06:03:47 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349824215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1349824215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1796629989 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 82111343 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:04:17 AM UTC 24 |
| Finished | Aug 23 06:04:19 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796629989 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1796629989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.301382348 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1266419342 ps |
| CPU time | 5.54 seconds |
| Started | Aug 23 06:04:16 AM UTC 24 |
| Finished | Aug 23 06:04:23 AM UTC 24 |
| Peak memory | 242392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301382348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.301382348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2849222613 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 301860871 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 06:04:16 AM UTC 24 |
| Finished | Aug 23 06:04:19 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849222613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2849222613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.360185409 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 189872802 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 06:04:15 AM UTC 24 |
| Finished | Aug 23 06:04:17 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360185409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.360185409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2064824080 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1667253762 ps |
| CPU time | 5.4 seconds |
| Started | Aug 23 06:04:15 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064824080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2064824080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.891074347 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 103648069 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 06:04:16 AM UTC 24 |
| Finished | Aug 23 06:04:18 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891074347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.891074347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.868022647 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 225857964 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 06:04:15 AM UTC 24 |
| Finished | Aug 23 06:04:17 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868022647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.868022647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.3723423390 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 14362065934 ps |
| CPU time | 44.42 seconds |
| Started | Aug 23 06:04:17 AM UTC 24 |
| Finished | Aug 23 06:05:03 AM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723423390 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.3723423390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.947836907 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 285444925 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 06:04:16 AM UTC 24 |
| Finished | Aug 23 06:04:19 AM UTC 24 |
| Peak memory | 208320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947836907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.947836907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.965866448 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 144656924 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 06:04:15 AM UTC 24 |
| Finished | Aug 23 06:04:17 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965866448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.965866448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3157049970 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 61898728 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157049970 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.3157049970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3913149155 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 301910478 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 237404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913149155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3913149155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.1214818238 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 173981730 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 06:04:18 AM UTC 24 |
| Finished | Aug 23 06:04:20 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214818238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.1214818238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.859939109 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1424370339 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 06:04:18 AM UTC 24 |
| Finished | Aug 23 06:04:24 AM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859939109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.859939109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.743298773 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 100987403 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743298773 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.743298773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.3279825382 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 249664846 ps |
| CPU time | 1.41 seconds |
| Started | Aug 23 06:04:18 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279825382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.3279825382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.3449069738 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3644805940 ps |
| CPU time | 15.65 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 208556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449069738 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.3449069738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.253381103 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 334784954 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:22 AM UTC 24 |
| Peak memory | 207224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253381103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.253381103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2775752351 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 236664934 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 06:04:18 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775752351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2775752351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.2170851643 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 68695570 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:04:22 AM UTC 24 |
| Finished | Aug 23 06:04:24 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170851643 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2170851643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.639792573 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1961380554 ps |
| CPU time | 6.68 seconds |
| Started | Aug 23 06:04:22 AM UTC 24 |
| Finished | Aug 23 06:04:30 AM UTC 24 |
| Peak memory | 242164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639792573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.639792573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2838608955 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 301400955 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:04:22 AM UTC 24 |
| Finished | Aug 23 06:04:24 AM UTC 24 |
| Peak memory | 236624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838608955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2838608955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.2277990558 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 190121892 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 06:04:20 AM UTC 24 |
| Finished | Aug 23 06:04:23 AM UTC 24 |
| Peak memory | 207800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277990558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2277990558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.351533034 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 915251422 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 06:04:20 AM UTC 24 |
| Finished | Aug 23 06:04:26 AM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351533034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.351533034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2839418310 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 147537017 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:04:22 AM UTC 24 |
| Finished | Aug 23 06:04:24 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839418310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2839418310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3940992851 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 188289384 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 06:04:19 AM UTC 24 |
| Finished | Aug 23 06:04:22 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940992851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3940992851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1829279352 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3449723606 ps |
| CPU time | 11.5 seconds |
| Started | Aug 23 06:04:22 AM UTC 24 |
| Finished | Aug 23 06:04:35 AM UTC 24 |
| Peak memory | 217652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829279352 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1829279352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.287480263 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 135910678 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 06:04:20 AM UTC 24 |
| Finished | Aug 23 06:04:24 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287480263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.287480263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2963824368 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 97458071 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 06:04:20 AM UTC 24 |
| Finished | Aug 23 06:04:23 AM UTC 24 |
| Peak memory | 207904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963824368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2963824368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1126590088 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 94455224 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:04:24 AM UTC 24 |
| Finished | Aug 23 06:04:26 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126590088 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1126590088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3369255610 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2246597586 ps |
| CPU time | 6.92 seconds |
| Started | Aug 23 06:04:24 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 241904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369255610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3369255610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.529982553 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 303623085 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:04:24 AM UTC 24 |
| Finished | Aug 23 06:04:26 AM UTC 24 |
| Peak memory | 237528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529982553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.529982553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.1037152101 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 118244359 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:23 AM UTC 24 |
| Finished | Aug 23 06:04:25 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037152101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.1037152101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.2702281163 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1452955118 ps |
| CPU time | 4.91 seconds |
| Started | Aug 23 06:04:23 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702281163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2702281163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.1338131427 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 104941777 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 06:04:24 AM UTC 24 |
| Finished | Aug 23 06:04:26 AM UTC 24 |
| Peak memory | 208136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338131427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.1338131427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.1232119974 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 243897746 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 06:04:23 AM UTC 24 |
| Finished | Aug 23 06:04:25 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232119974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1232119974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1840173772 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 9100066682 ps |
| CPU time | 29.8 seconds |
| Started | Aug 23 06:04:24 AM UTC 24 |
| Finished | Aug 23 06:04:55 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840173772 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1840173772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3832102057 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 386235790 ps |
| CPU time | 2.14 seconds |
| Started | Aug 23 06:04:23 AM UTC 24 |
| Finished | Aug 23 06:04:26 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832102057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3832102057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.1495566939 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 230577543 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 06:04:23 AM UTC 24 |
| Finished | Aug 23 06:04:25 AM UTC 24 |
| Peak memory | 207868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495566939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1495566939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.574900794 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 68701702 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:04:27 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574900794 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.574900794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3884915349 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1263914183 ps |
| CPU time | 5.18 seconds |
| Started | Aug 23 06:04:26 AM UTC 24 |
| Finished | Aug 23 06:04:33 AM UTC 24 |
| Peak memory | 240572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884915349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3884915349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2661781487 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 302696261 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:26 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 237592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661781487 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2661781487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.3649062180 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 97361147 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:25 AM UTC 24 |
| Finished | Aug 23 06:04:27 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649062180 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3649062180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1360786576 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1888831458 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 06:04:25 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360786576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1360786576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.2242855946 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 168747082 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 06:04:26 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 205936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242855946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.2242855946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.953733587 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 120952836 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:25 AM UTC 24 |
| Finished | Aug 23 06:04:27 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953733587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.953733587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.429291161 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 9924480301 ps |
| CPU time | 30.32 seconds |
| Started | Aug 23 06:04:26 AM UTC 24 |
| Finished | Aug 23 06:04:58 AM UTC 24 |
| Peak memory | 220216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429291161 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.429291161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.4162960428 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 307525272 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 06:04:26 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162960428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.4162960428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3859467168 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 276359144 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 06:04:25 AM UTC 24 |
| Finished | Aug 23 06:04:28 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859467168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3859467168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.1347537214 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 86115128 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347537214 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.1347537214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.1968893091 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2232181783 ps |
| CPU time | 7.76 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:39 AM UTC 24 |
| Peak memory | 241468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968893091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1968893091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.4081198464 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 304330367 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 236916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081198464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.4081198464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3287857577 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 95206710 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:28 AM UTC 24 |
| Finished | Aug 23 06:04:29 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287857577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3287857577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1913537471 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 876329773 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 06:04:29 AM UTC 24 |
| Finished | Aug 23 06:04:34 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913537471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1913537471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2136421521 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 170958009 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 207896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136421521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2136421521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.1783915849 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 256483646 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 06:04:28 AM UTC 24 |
| Finished | Aug 23 06:04:30 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783915849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1783915849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.4014714032 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1631329246 ps |
| CPU time | 5.41 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014714032 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.4014714032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.2700880395 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 153856213 ps |
| CPU time | 1.62 seconds |
| Started | Aug 23 06:04:29 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700880395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2700880395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.2630103355 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 80111254 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:04:29 AM UTC 24 |
| Finished | Aug 23 06:04:31 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630103355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2630103355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.2958854649 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 77025563 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:04:33 AM UTC 24 |
| Finished | Aug 23 06:04:35 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958854649 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2958854649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.1093182182 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2456501144 ps |
| CPU time | 7.69 seconds |
| Started | Aug 23 06:04:32 AM UTC 24 |
| Finished | Aug 23 06:04:41 AM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093182182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.1093182182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2344613810 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 303610369 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:32 AM UTC 24 |
| Finished | Aug 23 06:04:34 AM UTC 24 |
| Peak memory | 237328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344613810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.2344613810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.1371138083 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 106240996 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:04:31 AM UTC 24 |
| Finished | Aug 23 06:04:33 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371138083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1371138083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.636256784 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 978200246 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 06:04:31 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636256784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.636256784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3805977451 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 151942587 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 06:04:32 AM UTC 24 |
| Finished | Aug 23 06:04:34 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805977451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3805977451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3675302432 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 114659123 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:04:30 AM UTC 24 |
| Finished | Aug 23 06:04:32 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675302432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3675302432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3110149380 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2505547586 ps |
| CPU time | 8.04 seconds |
| Started | Aug 23 06:04:32 AM UTC 24 |
| Finished | Aug 23 06:04:42 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110149380 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3110149380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.840375643 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 365541554 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 06:04:31 AM UTC 24 |
| Finished | Aug 23 06:04:34 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840375643 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.840375643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3105841685 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 161194542 ps |
| CPU time | 1 seconds |
| Started | Aug 23 06:04:31 AM UTC 24 |
| Finished | Aug 23 06:04:33 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105841685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3105841685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.3395802931 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 86827100 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:36 AM UTC 24 |
| Finished | Aug 23 06:04:38 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395802931 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3395802931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.1247862254 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1968288998 ps |
| CPU time | 6.64 seconds |
| Started | Aug 23 06:04:35 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 241328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247862254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1247862254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3515591993 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 302999651 ps |
| CPU time | 1 seconds |
| Started | Aug 23 06:04:35 AM UTC 24 |
| Finished | Aug 23 06:04:37 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515591993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3515591993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.4173031781 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 152540842 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 06:04:33 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173031781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.4173031781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.2323896165 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1377010115 ps |
| CPU time | 4.77 seconds |
| Started | Aug 23 06:04:33 AM UTC 24 |
| Finished | Aug 23 06:04:40 AM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323896165 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.2323896165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1737968401 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 184443927 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:04:35 AM UTC 24 |
| Finished | Aug 23 06:04:37 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737968401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1737968401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.209590946 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 199702542 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 06:04:33 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209590946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.209590946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.1095331278 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4633618851 ps |
| CPU time | 14.04 seconds |
| Started | Aug 23 06:04:36 AM UTC 24 |
| Finished | Aug 23 06:04:51 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095331278 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1095331278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1565793377 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 368534581 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 06:04:35 AM UTC 24 |
| Finished | Aug 23 06:04:38 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565793377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1565793377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3309888215 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 163359882 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 06:04:33 AM UTC 24 |
| Finished | Aug 23 06:04:36 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309888215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3309888215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.4114423879 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 63906168 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 06:04:38 AM UTC 24 |
| Finished | Aug 23 06:04:40 AM UTC 24 |
| Peak memory | 207344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114423879 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4114423879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.126045209 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2236962227 ps |
| CPU time | 8.35 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:47 AM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126045209 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.126045209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3341675900 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 302246498 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 06:04:38 AM UTC 24 |
| Finished | Aug 23 06:04:40 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341675900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3341675900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2979075313 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 81205317 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:39 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979075313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2979075313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2799402267 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 931208925 ps |
| CPU time | 3.83 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:42 AM UTC 24 |
| Peak memory | 209196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799402267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2799402267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3097064192 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 153166317 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:39 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097064192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3097064192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.2128892596 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 125827031 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:04:36 AM UTC 24 |
| Finished | Aug 23 06:04:38 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128892596 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2128892596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.4010005392 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4246524956 ps |
| CPU time | 17.74 seconds |
| Started | Aug 23 06:04:38 AM UTC 24 |
| Finished | Aug 23 06:04:57 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010005392 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4010005392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.4045636554 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 152568176 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:40 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045636554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.4045636554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.900759181 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 265124085 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 06:04:37 AM UTC 24 |
| Finished | Aug 23 06:04:39 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900759181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.900759181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3104561059 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 67827417 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:04:42 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104561059 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3104561059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.83024512 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1272043271 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 06:04:40 AM UTC 24 |
| Finished | Aug 23 06:04:46 AM UTC 24 |
| Peak memory | 241896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83024512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.83024512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.617529227 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 302452088 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 06:04:40 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617529227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.617529227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.3231951637 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 89778008 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:04:39 AM UTC 24 |
| Finished | Aug 23 06:04:41 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231951637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.3231951637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.661217224 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1830294440 ps |
| CPU time | 6.71 seconds |
| Started | Aug 23 06:04:39 AM UTC 24 |
| Finished | Aug 23 06:04:47 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661217224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.661217224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3131767860 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 174454857 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 06:04:40 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 208084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131767860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3131767860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.3834454130 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 251898226 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 06:04:38 AM UTC 24 |
| Finished | Aug 23 06:04:41 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834454130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.3834454130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.879357125 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 818699818 ps |
| CPU time | 3.5 seconds |
| Started | Aug 23 06:04:40 AM UTC 24 |
| Finished | Aug 23 06:04:45 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879357125 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.879357125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.40375551 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 111832797 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 06:04:40 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 208052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40375551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.40375551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.1366086734 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 101278239 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 06:04:39 AM UTC 24 |
| Finished | Aug 23 06:04:41 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366086734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.1366086734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1537666767 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 68487470 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:03:48 AM UTC 24 |
| Finished | Aug 23 06:03:50 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537666767 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1537666767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2986423539 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 302123902 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:03:48 AM UTC 24 |
| Finished | Aug 23 06:03:50 AM UTC 24 |
| Peak memory | 237504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986423539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2986423539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.4251583198 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 217792336 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 06:03:46 AM UTC 24 |
| Finished | Aug 23 06:03:48 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251583198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4251583198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.2580355843 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 849403998 ps |
| CPU time | 3.7 seconds |
| Started | Aug 23 06:03:47 AM UTC 24 |
| Finished | Aug 23 06:03:52 AM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580355843 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.2580355843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.231936428 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 8296978972 ps |
| CPU time | 14.08 seconds |
| Started | Aug 23 06:03:48 AM UTC 24 |
| Finished | Aug 23 06:04:03 AM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231936428 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.231936428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1865118749 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 108194577 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 06:03:47 AM UTC 24 |
| Finished | Aug 23 06:03:49 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865118749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1865118749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.73134606 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 196532897 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 06:03:46 AM UTC 24 |
| Finished | Aug 23 06:03:48 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73134606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.73134606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1348499685 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5390444363 ps |
| CPU time | 16.22 seconds |
| Started | Aug 23 06:03:48 AM UTC 24 |
| Finished | Aug 23 06:04:06 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348499685 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1348499685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.1844921708 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 139907398 ps |
| CPU time | 1.57 seconds |
| Started | Aug 23 06:03:47 AM UTC 24 |
| Finished | Aug 23 06:03:50 AM UTC 24 |
| Peak memory | 207476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844921708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1844921708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2281361695 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 117117858 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 06:03:47 AM UTC 24 |
| Finished | Aug 23 06:03:49 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281361695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2281361695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.13324971 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 57827459 ps |
| CPU time | 0.61 seconds |
| Started | Aug 23 06:04:44 AM UTC 24 |
| Finished | Aug 23 06:04:46 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13324971 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.13324971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3178046632 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1965704311 ps |
| CPU time | 6.84 seconds |
| Started | Aug 23 06:04:43 AM UTC 24 |
| Finished | Aug 23 06:04:51 AM UTC 24 |
| Peak memory | 242300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178046632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3178046632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.4145779201 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 302150805 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:04:43 AM UTC 24 |
| Finished | Aug 23 06:04:45 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145779201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.4145779201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.463944090 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 120823972 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:42 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463944090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.463944090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.462979578 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1814417379 ps |
| CPU time | 6.47 seconds |
| Started | Aug 23 06:04:42 AM UTC 24 |
| Finished | Aug 23 06:04:49 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462979578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.462979578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2466651573 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 101869553 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 06:04:43 AM UTC 24 |
| Finished | Aug 23 06:04:45 AM UTC 24 |
| Peak memory | 208132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466651573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2466651573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.1076280913 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 254481392 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 06:04:42 AM UTC 24 |
| Finished | Aug 23 06:04:44 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076280913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1076280913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.807477769 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4047107988 ps |
| CPU time | 14.75 seconds |
| Started | Aug 23 06:04:44 AM UTC 24 |
| Finished | Aug 23 06:05:00 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807477769 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.807477769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.2537775390 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 420910028 ps |
| CPU time | 2.16 seconds |
| Started | Aug 23 06:04:43 AM UTC 24 |
| Finished | Aug 23 06:04:46 AM UTC 24 |
| Peak memory | 208700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537775390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.2537775390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3766365944 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 77613178 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:04:42 AM UTC 24 |
| Finished | Aug 23 06:04:43 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766365944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3766365944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.1043299447 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 66697972 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:46 AM UTC 24 |
| Finished | Aug 23 06:04:48 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043299447 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1043299447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.634054090 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1272881021 ps |
| CPU time | 5.33 seconds |
| Started | Aug 23 06:04:46 AM UTC 24 |
| Finished | Aug 23 06:04:53 AM UTC 24 |
| Peak memory | 242080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634054090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.634054090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.275165327 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 302999349 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:46 AM UTC 24 |
| Finished | Aug 23 06:04:48 AM UTC 24 |
| Peak memory | 237024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275165327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.275165327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.951769861 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 158121348 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 06:04:44 AM UTC 24 |
| Finished | Aug 23 06:04:46 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951769861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.951769861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.652675834 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 660752779 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 06:04:44 AM UTC 24 |
| Finished | Aug 23 06:04:48 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652675834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.652675834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.1061750745 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 153915509 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:04:45 AM UTC 24 |
| Finished | Aug 23 06:04:47 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061750745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.1061750745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.3613409256 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 246659502 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 06:04:44 AM UTC 24 |
| Finished | Aug 23 06:04:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613409256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3613409256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2211722029 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2966299345 ps |
| CPU time | 11.69 seconds |
| Started | Aug 23 06:04:46 AM UTC 24 |
| Finished | Aug 23 06:04:59 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211722029 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2211722029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2784614531 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 137456022 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 06:04:45 AM UTC 24 |
| Finished | Aug 23 06:04:48 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784614531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2784614531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.1105640337 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 219944109 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 06:04:45 AM UTC 24 |
| Finished | Aug 23 06:04:47 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105640337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1105640337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1754753450 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 65152172 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:04:49 AM UTC 24 |
| Finished | Aug 23 06:04:50 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754753450 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1754753450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.900875267 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1966913003 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 06:04:49 AM UTC 24 |
| Finished | Aug 23 06:04:57 AM UTC 24 |
| Peak memory | 241284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900875267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.900875267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.4277037892 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 302455625 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 06:04:49 AM UTC 24 |
| Finished | Aug 23 06:04:51 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277037892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.4277037892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2607915358 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 162207821 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 06:04:47 AM UTC 24 |
| Finished | Aug 23 06:04:49 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607915358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2607915358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.3556508904 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1305911238 ps |
| CPU time | 4.55 seconds |
| Started | Aug 23 06:04:47 AM UTC 24 |
| Finished | Aug 23 06:04:53 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556508904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3556508904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.1243060303 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 152487219 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 06:04:49 AM UTC 24 |
| Finished | Aug 23 06:04:51 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243060303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.1243060303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.918673648 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 123817366 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:04:47 AM UTC 24 |
| Finished | Aug 23 06:04:49 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918673648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.918673648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.1112566835 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 8947644358 ps |
| CPU time | 29.07 seconds |
| Started | Aug 23 06:04:49 AM UTC 24 |
| Finished | Aug 23 06:05:19 AM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112566835 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1112566835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.4267968386 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 293874982 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 06:04:48 AM UTC 24 |
| Finished | Aug 23 06:04:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267968386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.4267968386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.3849214112 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 88579357 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 06:04:48 AM UTC 24 |
| Finished | Aug 23 06:04:49 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849214112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3849214112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.1097183807 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 72981871 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:04:52 AM UTC 24 |
| Finished | Aug 23 06:04:54 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097183807 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1097183807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3829172985 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1264576881 ps |
| CPU time | 5.14 seconds |
| Started | Aug 23 06:04:51 AM UTC 24 |
| Finished | Aug 23 06:04:57 AM UTC 24 |
| Peak memory | 241672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829172985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3829172985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.2634020809 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 302202419 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:04:51 AM UTC 24 |
| Finished | Aug 23 06:04:53 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634020809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.2634020809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.4235895743 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 203083888 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:04:50 AM UTC 24 |
| Finished | Aug 23 06:04:52 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235895743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.4235895743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.1362256067 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1081617642 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 06:04:50 AM UTC 24 |
| Finished | Aug 23 06:04:55 AM UTC 24 |
| Peak memory | 209020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362256067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1362256067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.3168080649 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 101202487 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 06:04:51 AM UTC 24 |
| Finished | Aug 23 06:04:53 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168080649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.3168080649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.1842928964 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 126527030 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:04:50 AM UTC 24 |
| Finished | Aug 23 06:04:52 AM UTC 24 |
| Peak memory | 207488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842928964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1842928964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.2327406762 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1750868703 ps |
| CPU time | 5.73 seconds |
| Started | Aug 23 06:04:51 AM UTC 24 |
| Finished | Aug 23 06:04:58 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327406762 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2327406762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.795040253 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 125246039 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 06:04:51 AM UTC 24 |
| Finished | Aug 23 06:04:53 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795040253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.795040253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.4190303939 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 243866887 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 06:04:50 AM UTC 24 |
| Finished | Aug 23 06:04:52 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190303939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4190303939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.2986313560 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 104541557 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:04:55 AM UTC 24 |
| Finished | Aug 23 06:04:56 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986313560 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.2986313560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.3875271315 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2265301192 ps |
| CPU time | 6.82 seconds |
| Started | Aug 23 06:04:53 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 242392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875271315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3875271315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.306550300 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 301620087 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:04:55 AM UTC 24 |
| Finished | Aug 23 06:04:57 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306550300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.306550300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.3672061459 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 133782945 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:04:52 AM UTC 24 |
| Finished | Aug 23 06:04:54 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672061459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.3672061459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.527588000 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 997994738 ps |
| CPU time | 4.29 seconds |
| Started | Aug 23 06:04:53 AM UTC 24 |
| Finished | Aug 23 06:04:59 AM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527588000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.527588000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.642318719 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 101409254 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 06:04:53 AM UTC 24 |
| Finished | Aug 23 06:04:55 AM UTC 24 |
| Peak memory | 208072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642318719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.642318719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3651514993 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 195415317 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 06:04:52 AM UTC 24 |
| Finished | Aug 23 06:04:54 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651514993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3651514993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.2628078397 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2879677160 ps |
| CPU time | 11.39 seconds |
| Started | Aug 23 06:04:55 AM UTC 24 |
| Finished | Aug 23 06:05:07 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628078397 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2628078397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.1167066140 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 371288968 ps |
| CPU time | 2.06 seconds |
| Started | Aug 23 06:04:53 AM UTC 24 |
| Finished | Aug 23 06:04:56 AM UTC 24 |
| Peak memory | 208496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167066140 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1167066140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.713881133 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 136498610 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:04:53 AM UTC 24 |
| Finished | Aug 23 06:04:55 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713881133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.713881133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3536967673 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 81698371 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:04:58 AM UTC 24 |
| Finished | Aug 23 06:05:00 AM UTC 24 |
| Peak memory | 208016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536967673 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3536967673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.123241641 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1963750420 ps |
| CPU time | 7.01 seconds |
| Started | Aug 23 06:04:57 AM UTC 24 |
| Finished | Aug 23 06:05:05 AM UTC 24 |
| Peak memory | 241732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123241641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.123241641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.487822507 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 301243140 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 06:04:57 AM UTC 24 |
| Finished | Aug 23 06:04:59 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487822507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.487822507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2616555103 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 201023528 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 06:04:56 AM UTC 24 |
| Finished | Aug 23 06:04:57 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616555103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2616555103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.85836696 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 942923321 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 06:04:56 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85836696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.85836696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3795555839 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 149449745 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 06:04:57 AM UTC 24 |
| Finished | Aug 23 06:04:59 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795555839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3795555839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.4275730247 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 197114131 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 06:04:56 AM UTC 24 |
| Finished | Aug 23 06:04:58 AM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275730247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.4275730247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.1705950305 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4775739106 ps |
| CPU time | 15.06 seconds |
| Started | Aug 23 06:04:58 AM UTC 24 |
| Finished | Aug 23 06:05:14 AM UTC 24 |
| Peak memory | 218044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705950305 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.1705950305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.4134317104 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 379992632 ps |
| CPU time | 2.07 seconds |
| Started | Aug 23 06:04:56 AM UTC 24 |
| Finished | Aug 23 06:04:59 AM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134317104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.4134317104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.4250641173 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 232981243 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 06:04:56 AM UTC 24 |
| Finished | Aug 23 06:04:58 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250641173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4250641173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.1431268013 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 70188179 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431268013 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.1431268013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.349828929 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1263379825 ps |
| CPU time | 5.28 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 241644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349828929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.349828929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2858007967 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 301695611 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858007967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2858007967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.358367985 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 208739913 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 06:04:58 AM UTC 24 |
| Finished | Aug 23 06:05:00 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358367985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.358367985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.1717725469 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 906254763 ps |
| CPU time | 4.11 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717725469 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1717725469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.430107302 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 166989392 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430107302 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.430107302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3203960674 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 115332598 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:04:58 AM UTC 24 |
| Finished | Aug 23 06:05:00 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203960674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3203960674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.1900425648 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 11566950365 ps |
| CPU time | 35.22 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900425648 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1900425648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.4139833840 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 134444124 ps |
| CPU time | 1.47 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:02 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139833840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.4139833840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.1707803625 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 130482950 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:04:59 AM UTC 24 |
| Finished | Aug 23 06:05:01 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707803625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1707803625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.1211201249 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 77565481 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211201249 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.1211201249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.2421445663 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1970249374 ps |
| CPU time | 6.11 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 241572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421445663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2421445663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.665646011 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 302487056 ps |
| CPU time | 1 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665646011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.665646011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1699819398 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 184946989 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:05:01 AM UTC 24 |
| Finished | Aug 23 06:05:02 AM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699819398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1699819398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.1871161719 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 747236535 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 06:05:01 AM UTC 24 |
| Finished | Aug 23 06:05:05 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871161719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1871161719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2785848107 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 102902106 ps |
| CPU time | 0.88 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785848107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2785848107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.3637566493 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 199272901 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 06:05:01 AM UTC 24 |
| Finished | Aug 23 06:05:03 AM UTC 24 |
| Peak memory | 207960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637566493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3637566493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.1015777451 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 11065207863 ps |
| CPU time | 33.61 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015777451 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.1015777451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.831739404 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 244026477 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 06:05:01 AM UTC 24 |
| Finished | Aug 23 06:05:03 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831739404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.831739404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.2975212073 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 120067558 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 06:05:01 AM UTC 24 |
| Finished | Aug 23 06:05:03 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975212073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2975212073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1859620842 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 71566424 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859620842 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1859620842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2694249043 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1988841579 ps |
| CPU time | 6.29 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:12 AM UTC 24 |
| Peak memory | 242380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694249043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2694249043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.400882904 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 301613163 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400882904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.400882904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.3434545605 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 115539668 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434545605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3434545605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.1875682644 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1471090916 ps |
| CPU time | 5.3 seconds |
| Started | Aug 23 06:05:03 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 209148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875682644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1875682644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.782807736 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 175272286 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782807736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.782807736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.788306847 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 188899016 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 06:05:02 AM UTC 24 |
| Finished | Aug 23 06:05:04 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788306847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.788306847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2548884207 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1820378385 ps |
| CPU time | 6.1 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548884207 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2548884207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.825500867 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 399160982 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 06:05:03 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825500867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.825500867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.678499874 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 90606267 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 06:05:03 AM UTC 24 |
| Finished | Aug 23 06:05:05 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678499874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.678499874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.1717324182 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 73608868 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:08 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717324182 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.1717324182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.1448417352 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1273627816 ps |
| CPU time | 5.33 seconds |
| Started | Aug 23 06:05:06 AM UTC 24 |
| Finished | Aug 23 06:05:12 AM UTC 24 |
| Peak memory | 242056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448417352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.1448417352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3941347393 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 305539802 ps |
| CPU time | 1 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941347393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3941347393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.859899287 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 106487337 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859899287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.859899287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.731493996 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1220999198 ps |
| CPU time | 5.33 seconds |
| Started | Aug 23 06:05:05 AM UTC 24 |
| Finished | Aug 23 06:05:12 AM UTC 24 |
| Peak memory | 209080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731493996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.731493996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.4174580810 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 145565345 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:05:06 AM UTC 24 |
| Finished | Aug 23 06:05:08 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174580810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.4174580810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.3537164896 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 127996200 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 06:05:04 AM UTC 24 |
| Finished | Aug 23 06:05:06 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537164896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3537164896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.566116895 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 7213845830 ps |
| CPU time | 23.15 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:31 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566116895 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.566116895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1226456350 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 118916273 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 06:05:06 AM UTC 24 |
| Finished | Aug 23 06:05:08 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226456350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1226456350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3554865496 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 120988114 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 06:05:05 AM UTC 24 |
| Finished | Aug 23 06:05:07 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554865496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3554865496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1533744669 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 66532823 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:03:52 AM UTC 24 |
| Finished | Aug 23 06:03:53 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533744669 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1533744669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.842269245 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1271533729 ps |
| CPU time | 5.06 seconds |
| Started | Aug 23 06:03:51 AM UTC 24 |
| Finished | Aug 23 06:03:57 AM UTC 24 |
| Peak memory | 242340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842269245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.842269245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.1758650947 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 301868092 ps |
| CPU time | 1.14 seconds |
| Started | Aug 23 06:03:51 AM UTC 24 |
| Finished | Aug 23 06:03:53 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758650947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.1758650947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.278791756 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 88202365 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:03:49 AM UTC 24 |
| Finished | Aug 23 06:03:51 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278791756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.278791756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.1560049476 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1352924040 ps |
| CPU time | 4.86 seconds |
| Started | Aug 23 06:03:49 AM UTC 24 |
| Finished | Aug 23 06:03:55 AM UTC 24 |
| Peak memory | 209160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560049476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.1560049476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.47047216 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 16514160023 ps |
| CPU time | 28.93 seconds |
| Started | Aug 23 06:03:51 AM UTC 24 |
| Finished | Aug 23 06:04:21 AM UTC 24 |
| Peak memory | 241820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47047216 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.47047216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.872505283 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 141780298 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:03:50 AM UTC 24 |
| Finished | Aug 23 06:03:52 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872505283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.872505283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.780160468 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 201161250 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 06:03:48 AM UTC 24 |
| Finished | Aug 23 06:03:51 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780160468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.780160468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.416498071 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 5095445988 ps |
| CPU time | 20.75 seconds |
| Started | Aug 23 06:03:51 AM UTC 24 |
| Finished | Aug 23 06:04:13 AM UTC 24 |
| Peak memory | 220344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416498071 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.416498071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.1577422683 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 132827792 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 06:03:49 AM UTC 24 |
| Finished | Aug 23 06:03:52 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577422683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1577422683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.1462168681 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 189153511 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:03:49 AM UTC 24 |
| Finished | Aug 23 06:03:52 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462168681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.1462168681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.2116309665 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 82289297 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:05:09 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116309665 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2116309665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.482677187 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1960085565 ps |
| CPU time | 6.29 seconds |
| Started | Aug 23 06:05:08 AM UTC 24 |
| Finished | Aug 23 06:05:15 AM UTC 24 |
| Peak memory | 242316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482677187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.482677187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2448137002 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 301161246 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 06:05:09 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 237400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448137002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2448137002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.4271457431 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 104448398 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271457431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.4271457431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.3182382532 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1925288641 ps |
| CPU time | 6.18 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:14 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182382532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3182382532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4161919157 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 103946069 ps |
| CPU time | 0.88 seconds |
| Started | Aug 23 06:05:08 AM UTC 24 |
| Finished | Aug 23 06:05:10 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161919157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4161919157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.4149477208 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 195662430 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149477208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.4149477208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.1000498934 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2458933390 ps |
| CPU time | 11.3 seconds |
| Started | Aug 23 06:05:09 AM UTC 24 |
| Finished | Aug 23 06:05:21 AM UTC 24 |
| Peak memory | 209000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000498934 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1000498934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.3795883035 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 133482447 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 06:05:08 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795883035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.3795883035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3395105522 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 191443582 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 06:05:07 AM UTC 24 |
| Finished | Aug 23 06:05:09 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395105522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3395105522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.4020090410 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 74651516 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 06:05:12 AM UTC 24 |
| Finished | Aug 23 06:05:13 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020090410 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4020090410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.1597423752 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2443210799 ps |
| CPU time | 7.71 seconds |
| Started | Aug 23 06:05:10 AM UTC 24 |
| Finished | Aug 23 06:05:19 AM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597423752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.1597423752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2748207536 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 302532237 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:05:11 AM UTC 24 |
| Finished | Aug 23 06:05:13 AM UTC 24 |
| Peak memory | 237456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748207536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2748207536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.1759870522 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 134152952 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 06:05:09 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759870522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.1759870522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.612505716 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 1616579173 ps |
| CPU time | 5.78 seconds |
| Started | Aug 23 06:05:10 AM UTC 24 |
| Finished | Aug 23 06:05:17 AM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612505716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.612505716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2830401938 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 101080995 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 06:05:10 AM UTC 24 |
| Finished | Aug 23 06:05:12 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830401938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2830401938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.1590195872 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 118778246 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 06:05:09 AM UTC 24 |
| Finished | Aug 23 06:05:11 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590195872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.1590195872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.2174978042 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 4150614110 ps |
| CPU time | 15.56 seconds |
| Started | Aug 23 06:05:11 AM UTC 24 |
| Finished | Aug 23 06:05:28 AM UTC 24 |
| Peak memory | 209124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174978042 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2174978042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1873078320 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 277866231 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 06:05:10 AM UTC 24 |
| Finished | Aug 23 06:05:13 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873078320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1873078320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.1684496776 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 147707875 ps |
| CPU time | 0.93 seconds |
| Started | Aug 23 06:05:10 AM UTC 24 |
| Finished | Aug 23 06:05:12 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684496776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1684496776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.4105840245 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 63159935 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:05:14 AM UTC 24 |
| Finished | Aug 23 06:05:16 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105840245 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.4105840245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.3609624923 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2451628117 ps |
| CPU time | 7.13 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:21 AM UTC 24 |
| Peak memory | 242408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609624923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3609624923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1137518648 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 301495136 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:15 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137518648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1137518648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.2065360675 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 172277881 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 06:05:12 AM UTC 24 |
| Finished | Aug 23 06:05:13 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065360675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.2065360675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.200768261 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1005585518 ps |
| CPU time | 4.2 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:18 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200768261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.200768261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.217203067 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 188532469 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:15 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217203067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.217203067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2641529006 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 202984884 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 06:05:12 AM UTC 24 |
| Finished | Aug 23 06:05:14 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641529006 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2641529006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2900722012 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 8869396565 ps |
| CPU time | 30.05 seconds |
| Started | Aug 23 06:05:14 AM UTC 24 |
| Finished | Aug 23 06:05:45 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900722012 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2900722012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.3131168877 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 112651379 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:15 AM UTC 24 |
| Peak memory | 207816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131168877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3131168877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.2860159064 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 104658791 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 06:05:13 AM UTC 24 |
| Finished | Aug 23 06:05:15 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860159064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2860159064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.27188742 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 172499850 ps |
| CPU time | 0.88 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:18 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27188742 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.27188742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.904058734 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1972290552 ps |
| CPU time | 6.62 seconds |
| Started | Aug 23 06:05:15 AM UTC 24 |
| Finished | Aug 23 06:05:23 AM UTC 24 |
| Peak memory | 242116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904058734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.904058734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.229607389 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 301993127 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:18 AM UTC 24 |
| Peak memory | 237452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229607389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.229607389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2461544850 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 175490453 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 06:05:14 AM UTC 24 |
| Finished | Aug 23 06:05:16 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461544850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2461544850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.3947957794 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 791032274 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 06:05:15 AM UTC 24 |
| Finished | Aug 23 06:05:19 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947957794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3947957794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.1005683259 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 173361934 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 06:05:15 AM UTC 24 |
| Finished | Aug 23 06:05:17 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005683259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.1005683259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.3115124081 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 113081887 ps |
| CPU time | 1 seconds |
| Started | Aug 23 06:05:14 AM UTC 24 |
| Finished | Aug 23 06:05:16 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115124081 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3115124081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.1547432925 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 7718637327 ps |
| CPU time | 25.95 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:43 AM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547432925 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1547432925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.202267099 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 125361481 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 06:05:15 AM UTC 24 |
| Finished | Aug 23 06:05:17 AM UTC 24 |
| Peak memory | 216868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202267099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.202267099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.3346388840 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 111536868 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 06:05:15 AM UTC 24 |
| Finished | Aug 23 06:05:17 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346388840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3346388840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.1658128441 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 63272302 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:20 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658128441 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1658128441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.2789912612 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1967709444 ps |
| CPU time | 6.67 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:26 AM UTC 24 |
| Peak memory | 241736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789912612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2789912612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3539204331 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 301901767 ps |
| CPU time | 1.09 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:21 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539204331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3539204331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1424044191 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 76941498 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:18 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424044191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1424044191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.2190397161 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 758497321 ps |
| CPU time | 3.62 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:21 AM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190397161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2190397161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1824791167 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 169904055 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:18 AM UTC 24 |
| Finished | Aug 23 06:05:20 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824791167 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1824791167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.1554912775 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 120874931 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:05:16 AM UTC 24 |
| Finished | Aug 23 06:05:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554912775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1554912775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.3991983513 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 416657510 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:22 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991983513 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3991983513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.1361368515 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 348616910 ps |
| CPU time | 1.94 seconds |
| Started | Aug 23 06:05:18 AM UTC 24 |
| Finished | Aug 23 06:05:20 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361368515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1361368515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.1105118877 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 214697561 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 06:05:18 AM UTC 24 |
| Finished | Aug 23 06:05:20 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105118877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1105118877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.1813892545 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 78163508 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:23 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813892545 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.1813892545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.3024815410 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1283090427 ps |
| CPU time | 5.09 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:27 AM UTC 24 |
| Peak memory | 242216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024815410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3024815410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2245250325 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 302247028 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:23 AM UTC 24 |
| Peak memory | 237368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245250325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2245250325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.749351479 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 123698811 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:20 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749351479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.749351479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.3591586829 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 901415022 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 06:05:20 AM UTC 24 |
| Finished | Aug 23 06:05:25 AM UTC 24 |
| Peak memory | 209040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591586829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.3591586829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.517127314 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 106486927 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 06:05:20 AM UTC 24 |
| Finished | Aug 23 06:05:22 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517127314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.517127314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3257682892 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 117115615 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:19 AM UTC 24 |
| Finished | Aug 23 06:05:21 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257682892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3257682892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.1352031899 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 7526972742 ps |
| CPU time | 27.49 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352031899 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1352031899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.3024713498 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 144108776 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 06:05:20 AM UTC 24 |
| Finished | Aug 23 06:05:22 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024713498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3024713498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.285993219 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 83154316 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 06:05:20 AM UTC 24 |
| Finished | Aug 23 06:05:22 AM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285993219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.285993219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.4213288703 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 67443535 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:25 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213288703 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.4213288703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.746453291 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2458222429 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:31 AM UTC 24 |
| Peak memory | 241736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746453291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.746453291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.3668406853 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 302654198 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:24 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668406853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.3668406853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.2749430445 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 69854751 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:23 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749430445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2749430445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.2597633462 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 719167282 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:26 AM UTC 24 |
| Peak memory | 209320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597633462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2597633462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3206127382 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 99609737 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:24 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206127382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3206127382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.1725439618 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 114780840 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:21 AM UTC 24 |
| Finished | Aug 23 06:05:23 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725439618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1725439618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.306093904 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 4366653608 ps |
| CPU time | 17.4 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 209308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306093904 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.306093904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.3574332653 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 357119483 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:25 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574332653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.3574332653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.732044475 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 103623846 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 06:05:22 AM UTC 24 |
| Finished | Aug 23 06:05:24 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732044475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.732044475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.3618246834 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 73527655 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:05:26 AM UTC 24 |
| Finished | Aug 23 06:05:28 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618246834 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3618246834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.1659498711 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1971328613 ps |
| CPU time | 6.34 seconds |
| Started | Aug 23 06:05:25 AM UTC 24 |
| Finished | Aug 23 06:05:32 AM UTC 24 |
| Peak memory | 240540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659498711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1659498711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.2735989526 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 301739382 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:05:25 AM UTC 24 |
| Finished | Aug 23 06:05:27 AM UTC 24 |
| Peak memory | 237516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735989526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.2735989526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.1241900016 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 208940477 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:25 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241900016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1241900016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.501866644 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1914162842 ps |
| CPU time | 6.53 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:31 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501866644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.501866644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.578570431 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 143489055 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 06:05:25 AM UTC 24 |
| Finished | Aug 23 06:05:27 AM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578570431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.578570431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.4178610959 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 210832390 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178610959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4178610959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.4211094139 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 7314297982 ps |
| CPU time | 22.86 seconds |
| Started | Aug 23 06:05:25 AM UTC 24 |
| Finished | Aug 23 06:05:49 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211094139 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4211094139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2601467958 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 282198389 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601467958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2601467958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1228756512 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 222609991 ps |
| CPU time | 1.13 seconds |
| Started | Aug 23 06:05:24 AM UTC 24 |
| Finished | Aug 23 06:05:26 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228756512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1228756512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.245432070 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 58159103 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 06:05:28 AM UTC 24 |
| Finished | Aug 23 06:05:30 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245432070 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.245432070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.2935309368 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2450794066 ps |
| CPU time | 7.49 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 241720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935309368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2935309368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.3867795720 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 303333989 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:29 AM UTC 24 |
| Peak memory | 237564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867795720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.3867795720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.983253338 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 106114603 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:05:26 AM UTC 24 |
| Finished | Aug 23 06:05:28 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983253338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.983253338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.193406119 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1429417163 ps |
| CPU time | 5.55 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:34 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193406119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.193406119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1919862736 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 112867093 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:29 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919862736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1919862736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.2952704784 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 199857992 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 06:05:26 AM UTC 24 |
| Finished | Aug 23 06:05:28 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952704784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2952704784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.407141945 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 133398390 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:29 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407141945 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.407141945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.1564178217 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 123820164 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:29 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564178217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1564178217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.2635960612 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 123447585 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 06:05:27 AM UTC 24 |
| Finished | Aug 23 06:05:29 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635960612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.2635960612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.3974912750 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 116818052 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:05:31 AM UTC 24 |
| Finished | Aug 23 06:05:33 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974912750 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3974912750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1411883740 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1278379900 ps |
| CPU time | 4.89 seconds |
| Started | Aug 23 06:05:30 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 242340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411883740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1411883740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2423562207 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 301116388 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 06:05:31 AM UTC 24 |
| Finished | Aug 23 06:05:33 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423562207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2423562207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.228472107 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 192161476 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 06:05:28 AM UTC 24 |
| Finished | Aug 23 06:05:30 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228472107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.228472107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.2814664898 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 1539246065 ps |
| CPU time | 5.62 seconds |
| Started | Aug 23 06:05:30 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 209256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814664898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2814664898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.602048959 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 170703136 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:05:30 AM UTC 24 |
| Finished | Aug 23 06:05:32 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602048959 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.602048959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.4284128436 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 191776273 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 06:05:28 AM UTC 24 |
| Finished | Aug 23 06:05:31 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284128436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4284128436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.4061195815 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1351661854 ps |
| CPU time | 5.4 seconds |
| Started | Aug 23 06:05:31 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061195815 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.4061195815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.612319113 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 295040736 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 06:05:30 AM UTC 24 |
| Finished | Aug 23 06:05:32 AM UTC 24 |
| Peak memory | 216812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612319113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.612319113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.584192018 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 111743453 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 06:05:30 AM UTC 24 |
| Finished | Aug 23 06:05:31 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584192018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.584192018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.1093290418 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 57815736 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 06:03:55 AM UTC 24 |
| Finished | Aug 23 06:03:57 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093290418 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1093290418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.4148029829 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1270467324 ps |
| CPU time | 4.76 seconds |
| Started | Aug 23 06:03:53 AM UTC 24 |
| Finished | Aug 23 06:03:59 AM UTC 24 |
| Peak memory | 242400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148029829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4148029829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.45213204 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 302442751 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:03:54 AM UTC 24 |
| Finished | Aug 23 06:03:56 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45213204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.45213204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.991451008 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 135523647 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:03:52 AM UTC 24 |
| Finished | Aug 23 06:03:54 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991451008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.991451008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.1097534694 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 851579847 ps |
| CPU time | 3.85 seconds |
| Started | Aug 23 06:03:52 AM UTC 24 |
| Finished | Aug 23 06:03:57 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097534694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1097534694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1310925720 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 8455230891 ps |
| CPU time | 12.95 seconds |
| Started | Aug 23 06:03:55 AM UTC 24 |
| Finished | Aug 23 06:04:09 AM UTC 24 |
| Peak memory | 241720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310925720 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1310925720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.619788738 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 99203374 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 06:03:53 AM UTC 24 |
| Finished | Aug 23 06:03:55 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619788738 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.619788738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.325980603 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 202483721 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 06:03:52 AM UTC 24 |
| Finished | Aug 23 06:03:54 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325980603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.325980603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.93916009 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 124738875 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 06:03:53 AM UTC 24 |
| Finished | Aug 23 06:03:55 AM UTC 24 |
| Peak memory | 208200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93916009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.93916009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.705372629 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 175856586 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:03:53 AM UTC 24 |
| Finished | Aug 23 06:03:55 AM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705372629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.705372629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3350627386 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 73690375 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:05:33 AM UTC 24 |
| Finished | Aug 23 06:05:35 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350627386 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3350627386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.1535085548 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2436141903 ps |
| CPU time | 8.2 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 242304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535085548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.1535085548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3869237553 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 301948215 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:05:33 AM UTC 24 |
| Finished | Aug 23 06:05:35 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869237553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3869237553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.1692936918 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 192406412 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:34 AM UTC 24 |
| Peak memory | 208044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692936918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1692936918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.3911021929 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 822463068 ps |
| CPU time | 3.82 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911021929 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3911021929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3434530962 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 145541192 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:34 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434530962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3434530962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.475502986 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 190481451 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 06:05:31 AM UTC 24 |
| Finished | Aug 23 06:05:33 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475502986 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.475502986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.3596982354 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 14656437635 ps |
| CPU time | 48.05 seconds |
| Started | Aug 23 06:05:33 AM UTC 24 |
| Finished | Aug 23 06:06:23 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596982354 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3596982354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.2988431173 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 284663296 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:35 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988431173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.2988431173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.168071539 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 205864578 ps |
| CPU time | 1.08 seconds |
| Started | Aug 23 06:05:32 AM UTC 24 |
| Finished | Aug 23 06:05:34 AM UTC 24 |
| Peak memory | 208168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168071539 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.168071539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.256508242 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 72862080 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:38 AM UTC 24 |
| Peak memory | 207680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256508242 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.256508242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.1710657935 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1270841083 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 06:05:35 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 242344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710657935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1710657935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3461735657 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 301668017 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:05:36 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461735657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3461735657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.131772463 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 94201764 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:05:34 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131772463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.131772463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2298086904 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1756787410 ps |
| CPU time | 6.16 seconds |
| Started | Aug 23 06:05:34 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298086904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2298086904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3123616920 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 101238699 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 06:05:35 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123616920 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3123616920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.4279821580 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 229625046 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 06:05:33 AM UTC 24 |
| Finished | Aug 23 06:05:35 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279821580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.4279821580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.2118127072 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3955353018 ps |
| CPU time | 12.61 seconds |
| Started | Aug 23 06:05:36 AM UTC 24 |
| Finished | Aug 23 06:05:49 AM UTC 24 |
| Peak memory | 218172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118127072 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2118127072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.3501301463 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 362162155 ps |
| CPU time | 1.99 seconds |
| Started | Aug 23 06:05:34 AM UTC 24 |
| Finished | Aug 23 06:05:37 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501301463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.3501301463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.2265731036 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 64827894 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:05:34 AM UTC 24 |
| Finished | Aug 23 06:05:36 AM UTC 24 |
| Peak memory | 208296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265731036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.2265731036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.706686848 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 63449451 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:40 AM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706686848 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.706686848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.4198892291 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2434431599 ps |
| CPU time | 7.86 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198892291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.4198892291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1392095925 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 302075271 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:40 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392095925 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1392095925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.4137115376 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 199362548 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:38 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137115376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4137115376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.3162746729 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1052460045 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:42 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162746729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3162746729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.1681648819 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 181314284 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:39 AM UTC 24 |
| Peak memory | 207992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681648819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.1681648819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.2317394750 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 229569277 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:39 AM UTC 24 |
| Peak memory | 207872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317394750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.2317394750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.3164827989 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 492702207 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 208092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164827989 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.3164827989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.1493487682 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 320530987 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:40 AM UTC 24 |
| Peak memory | 209012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493487682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1493487682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.58117919 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 99654188 ps |
| CPU time | 0.88 seconds |
| Started | Aug 23 06:05:37 AM UTC 24 |
| Finished | Aug 23 06:05:39 AM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58117919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.58117919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.2531214923 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 88582691 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:05:40 AM UTC 24 |
| Finished | Aug 23 06:05:42 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531214923 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2531214923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2611337982 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1266581809 ps |
| CPU time | 5.18 seconds |
| Started | Aug 23 06:05:40 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 242336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611337982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2611337982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.859059895 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 301957480 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 06:05:40 AM UTC 24 |
| Finished | Aug 23 06:05:42 AM UTC 24 |
| Peak memory | 237628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859059895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.859059895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.348428347 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 118072373 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:40 AM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348428347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.348428347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.1135859909 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 957613137 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 06:05:39 AM UTC 24 |
| Finished | Aug 23 06:05:44 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135859909 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1135859909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.33490460 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 148788553 ps |
| CPU time | 0.94 seconds |
| Started | Aug 23 06:05:39 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33490460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.33490460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.545441320 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 200820163 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 06:05:38 AM UTC 24 |
| Finished | Aug 23 06:05:40 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545441320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.545441320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.3922212098 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 9069317351 ps |
| CPU time | 26.91 seconds |
| Started | Aug 23 06:05:40 AM UTC 24 |
| Finished | Aug 23 06:06:09 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922212098 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.3922212098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.4254381419 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 148230489 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 06:05:39 AM UTC 24 |
| Finished | Aug 23 06:05:42 AM UTC 24 |
| Peak memory | 208092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254381419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.4254381419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.4274988200 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 170275774 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:05:39 AM UTC 24 |
| Finished | Aug 23 06:05:41 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274988200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.4274988200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.3639091286 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 71870812 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:44 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639091286 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.3639091286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.1816302628 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2445547025 ps |
| CPU time | 7.62 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:51 AM UTC 24 |
| Peak memory | 242460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816302628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1816302628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.3237977089 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 301828293 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:45 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237977089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.3237977089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.3620787007 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 169277623 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:05:42 AM UTC 24 |
| Finished | Aug 23 06:05:43 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620787007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.3620787007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.3199691999 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1062628158 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 06:05:42 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199691999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3199691999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2470313820 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 152991048 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 06:05:42 AM UTC 24 |
| Finished | Aug 23 06:05:44 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470313820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2470313820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.166582151 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 124944811 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:05:40 AM UTC 24 |
| Finished | Aug 23 06:05:42 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166582151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.166582151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.3812823097 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 4002602265 ps |
| CPU time | 12.18 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:56 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812823097 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3812823097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1170474850 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 293986443 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 06:05:42 AM UTC 24 |
| Finished | Aug 23 06:05:44 AM UTC 24 |
| Peak memory | 216808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170474850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1170474850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.2375195034 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 162067190 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:05:42 AM UTC 24 |
| Finished | Aug 23 06:05:44 AM UTC 24 |
| Peak memory | 208332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375195034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2375195034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1290764018 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 67537691 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 06:05:45 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290764018 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1290764018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.1553370139 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1284709819 ps |
| CPU time | 5.52 seconds |
| Started | Aug 23 06:05:44 AM UTC 24 |
| Finished | Aug 23 06:05:51 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553370139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.1553370139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2224135048 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 302454411 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:44 AM UTC 24 |
| Finished | Aug 23 06:05:46 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224135048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2224135048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3449019067 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 152162169 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:45 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449019067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3449019067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.755714094 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2020548670 ps |
| CPU time | 6.16 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755714094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.755714094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.790726312 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 178703726 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:44 AM UTC 24 |
| Finished | Aug 23 06:05:46 AM UTC 24 |
| Peak memory | 208312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790726312 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.790726312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.984979321 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 235322848 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:45 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984979321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.984979321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.1166811879 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 7175126602 ps |
| CPU time | 22.29 seconds |
| Started | Aug 23 06:05:44 AM UTC 24 |
| Finished | Aug 23 06:06:08 AM UTC 24 |
| Peak memory | 209316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166811879 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.1166811879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.1039265277 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 379324458 ps |
| CPU time | 1.92 seconds |
| Started | Aug 23 06:05:44 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039265277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1039265277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.2097948781 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 163026531 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:43 AM UTC 24 |
| Finished | Aug 23 06:05:45 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097948781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2097948781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3141959364 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 75615083 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 207408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141959364 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3141959364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.317060196 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1957714342 ps |
| CPU time | 6.94 seconds |
| Started | Aug 23 06:05:47 AM UTC 24 |
| Finished | Aug 23 06:05:55 AM UTC 24 |
| Peak memory | 242376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317060196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.317060196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.689921214 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 301992604 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:05:47 AM UTC 24 |
| Finished | Aug 23 06:05:49 AM UTC 24 |
| Peak memory | 237452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689921214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.689921214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2401181453 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 196872964 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 06:05:45 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401181453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2401181453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.1209183612 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2053755461 ps |
| CPU time | 6.26 seconds |
| Started | Aug 23 06:05:45 AM UTC 24 |
| Finished | Aug 23 06:05:53 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209183612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.1209183612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3244097719 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 107072960 ps |
| CPU time | 0.9 seconds |
| Started | Aug 23 06:05:47 AM UTC 24 |
| Finished | Aug 23 06:05:48 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244097719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3244097719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.3492095082 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 200616813 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 06:05:45 AM UTC 24 |
| Finished | Aug 23 06:05:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492095082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3492095082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3947853401 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 5149912831 ps |
| CPU time | 19.05 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:06:08 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947853401 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3947853401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.3624188677 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 124323547 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 06:05:46 AM UTC 24 |
| Finished | Aug 23 06:05:49 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624188677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3624188677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.3801214199 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 112441151 ps |
| CPU time | 0.92 seconds |
| Started | Aug 23 06:05:46 AM UTC 24 |
| Finished | Aug 23 06:05:48 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801214199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.3801214199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.505726194 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 82701188 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:05:52 AM UTC 24 |
| Peak memory | 208112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505726194 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.505726194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3045685057 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1964120472 ps |
| CPU time | 6.8 seconds |
| Started | Aug 23 06:05:49 AM UTC 24 |
| Finished | Aug 23 06:05:57 AM UTC 24 |
| Peak memory | 242348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045685057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3045685057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2818665955 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 301070075 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 06:05:49 AM UTC 24 |
| Finished | Aug 23 06:05:51 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818665955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2818665955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.1555049812 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 223816064 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555049812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1555049812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.2994449481 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1624663377 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:55 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994449481 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.2994449481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.702290813 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 155078315 ps |
| CPU time | 0.97 seconds |
| Started | Aug 23 06:05:49 AM UTC 24 |
| Finished | Aug 23 06:05:51 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702290813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.702290813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.619824973 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 206580128 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619824973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.619824973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3653062405 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4629605189 ps |
| CPU time | 18.04 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:06:09 AM UTC 24 |
| Peak memory | 209376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653062405 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3653062405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.1431832956 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 121444831 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431832956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.1431832956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.3452016994 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 173612526 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 06:05:48 AM UTC 24 |
| Finished | Aug 23 06:05:50 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452016994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3452016994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.3139452886 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 68990784 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:05:53 AM UTC 24 |
| Peak memory | 208120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139452886 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.3139452886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3923738979 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2457976937 ps |
| CPU time | 7.43 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:06:00 AM UTC 24 |
| Peak memory | 242104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923738979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3923738979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.3792414200 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 301039309 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:05:54 AM UTC 24 |
| Peak memory | 237044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792414200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.3792414200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.3471520402 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 135329135 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:05:52 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471520402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3471520402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.3470499077 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1455166771 ps |
| CPU time | 5.3 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:05:57 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470499077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3470499077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3939573277 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 190527127 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:05:54 AM UTC 24 |
| Peak memory | 208156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939573277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3939573277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.1858669918 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 123531350 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:05:52 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858669918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.1858669918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.3658438370 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 224033235 ps |
| CPU time | 1.38 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:05:54 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658438370 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.3658438370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.1160346868 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 452165795 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 06:05:51 AM UTC 24 |
| Finished | Aug 23 06:05:54 AM UTC 24 |
| Peak memory | 209120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160346868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1160346868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3195956619 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 73605488 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:50 AM UTC 24 |
| Finished | Aug 23 06:05:52 AM UTC 24 |
| Peak memory | 208304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195956619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3195956619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.1391567436 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 55939201 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 06:05:55 AM UTC 24 |
| Finished | Aug 23 06:05:57 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391567436 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1391567436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.2632187824 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2266929675 ps |
| CPU time | 7.36 seconds |
| Started | Aug 23 06:05:54 AM UTC 24 |
| Finished | Aug 23 06:06:02 AM UTC 24 |
| Peak memory | 242188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632187824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2632187824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3032460031 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 301777128 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 06:05:54 AM UTC 24 |
| Finished | Aug 23 06:05:56 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032460031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3032460031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.2550061541 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 92117931 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 06:05:53 AM UTC 24 |
| Finished | Aug 23 06:05:55 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550061541 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2550061541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.1720653617 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1423836818 ps |
| CPU time | 4.79 seconds |
| Started | Aug 23 06:05:53 AM UTC 24 |
| Finished | Aug 23 06:05:59 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720653617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1720653617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.601459092 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 159825015 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 06:05:53 AM UTC 24 |
| Finished | Aug 23 06:05:55 AM UTC 24 |
| Peak memory | 208368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601459092 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.601459092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.1115514405 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 224116141 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 06:05:52 AM UTC 24 |
| Finished | Aug 23 06:05:54 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115514405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1115514405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.4183943956 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 311315574 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 06:05:55 AM UTC 24 |
| Finished | Aug 23 06:05:58 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183943956 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.4183943956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.1397592368 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 373525819 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 06:05:53 AM UTC 24 |
| Finished | Aug 23 06:05:56 AM UTC 24 |
| Peak memory | 208992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397592368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.1397592368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.303063074 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 93031625 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 06:05:53 AM UTC 24 |
| Finished | Aug 23 06:05:55 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303063074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.303063074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4221767545 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 68191154 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:04:00 AM UTC 24 |
| Finished | Aug 23 06:04:01 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221767545 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4221767545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.1103814112 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1270087222 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 06:03:57 AM UTC 24 |
| Finished | Aug 23 06:04:04 AM UTC 24 |
| Peak memory | 241796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103814112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1103814112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1345611515 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 302108973 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:03:58 AM UTC 24 |
| Finished | Aug 23 06:04:00 AM UTC 24 |
| Peak memory | 237448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345611515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.1345611515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.3288503197 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 199993729 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 06:03:56 AM UTC 24 |
| Finished | Aug 23 06:03:58 AM UTC 24 |
| Peak memory | 208064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288503197 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.3288503197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1143302370 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 812536491 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 06:03:56 AM UTC 24 |
| Finished | Aug 23 06:04:01 AM UTC 24 |
| Peak memory | 209188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143302370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1143302370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3838074969 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 150320194 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 06:03:57 AM UTC 24 |
| Finished | Aug 23 06:03:59 AM UTC 24 |
| Peak memory | 207648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838074969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.3838074969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.685145625 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 261333896 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 06:03:56 AM UTC 24 |
| Finished | Aug 23 06:03:59 AM UTC 24 |
| Peak memory | 208152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685145625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.685145625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.1601828800 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5002867154 ps |
| CPU time | 18.78 seconds |
| Started | Aug 23 06:03:59 AM UTC 24 |
| Finished | Aug 23 06:04:19 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601828800 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.1601828800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1870689067 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 150606555 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 06:03:57 AM UTC 24 |
| Finished | Aug 23 06:04:00 AM UTC 24 |
| Peak memory | 207508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870689067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.1870689067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3260196035 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 187231967 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 06:03:56 AM UTC 24 |
| Finished | Aug 23 06:03:58 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260196035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3260196035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.360534171 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 77321356 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:03 AM UTC 24 |
| Finished | Aug 23 06:04:05 AM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360534171 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.360534171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2021540711 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2449599309 ps |
| CPU time | 7.93 seconds |
| Started | Aug 23 06:04:02 AM UTC 24 |
| Finished | Aug 23 06:04:11 AM UTC 24 |
| Peak memory | 242440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021540711 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2021540711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3678241938 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 302654584 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:02 AM UTC 24 |
| Finished | Aug 23 06:04:04 AM UTC 24 |
| Peak memory | 237620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678241938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3678241938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.335301355 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 75442038 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 06:04:00 AM UTC 24 |
| Finished | Aug 23 06:04:01 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335301355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.335301355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.3960707734 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1982886094 ps |
| CPU time | 5.99 seconds |
| Started | Aug 23 06:04:00 AM UTC 24 |
| Finished | Aug 23 06:04:07 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960707734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.3960707734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.2077283174 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 166573600 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:01 AM UTC 24 |
| Finished | Aug 23 06:04:03 AM UTC 24 |
| Peak memory | 208308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077283174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.2077283174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.3910698750 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 259250616 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 06:04:00 AM UTC 24 |
| Finished | Aug 23 06:04:02 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910698750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3910698750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.218129129 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 5144912190 ps |
| CPU time | 18.93 seconds |
| Started | Aug 23 06:04:02 AM UTC 24 |
| Finished | Aug 23 06:04:22 AM UTC 24 |
| Peak memory | 218232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218129129 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.218129129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.1127101290 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 382571224 ps |
| CPU time | 1.98 seconds |
| Started | Aug 23 06:04:01 AM UTC 24 |
| Finished | Aug 23 06:04:04 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127101290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.1127101290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2120401116 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 113570823 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 06:04:01 AM UTC 24 |
| Finished | Aug 23 06:04:03 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120401116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2120401116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.1847029175 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 61953462 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:04:07 AM UTC 24 |
| Finished | Aug 23 06:04:08 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847029175 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1847029175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.850362214 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2444351057 ps |
| CPU time | 7.94 seconds |
| Started | Aug 23 06:04:05 AM UTC 24 |
| Finished | Aug 23 06:04:14 AM UTC 24 |
| Peak memory | 241712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850362214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.850362214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1660712669 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 302320291 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:04:06 AM UTC 24 |
| Finished | Aug 23 06:04:09 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660712669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1660712669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.3997868011 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 120415344 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 06:04:04 AM UTC 24 |
| Finished | Aug 23 06:04:06 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997868011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3997868011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.1739196183 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1442963894 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 06:04:04 AM UTC 24 |
| Finished | Aug 23 06:04:10 AM UTC 24 |
| Peak memory | 209252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739196183 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1739196183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2335765707 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 105999535 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 06:04:04 AM UTC 24 |
| Finished | Aug 23 06:04:06 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335765707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2335765707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.4189435033 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 197790955 ps |
| CPU time | 1.15 seconds |
| Started | Aug 23 06:04:03 AM UTC 24 |
| Finished | Aug 23 06:04:05 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189435033 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.4189435033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.281182500 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1295701244 ps |
| CPU time | 4.89 seconds |
| Started | Aug 23 06:04:06 AM UTC 24 |
| Finished | Aug 23 06:04:12 AM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281182500 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.281182500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3048210107 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 137944432 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 06:04:04 AM UTC 24 |
| Finished | Aug 23 06:04:07 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048210107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3048210107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1512098635 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 60911689 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:04 AM UTC 24 |
| Finished | Aug 23 06:04:06 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512098635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1512098635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.4279925403 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 73192485 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 06:04:11 AM UTC 24 |
| Finished | Aug 23 06:04:13 AM UTC 24 |
| Peak memory | 208080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279925403 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4279925403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.4180405725 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2455585120 ps |
| CPU time | 7.79 seconds |
| Started | Aug 23 06:04:10 AM UTC 24 |
| Finished | Aug 23 06:04:19 AM UTC 24 |
| Peak memory | 242312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180405725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4180405725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.564504301 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 301614188 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:04:10 AM UTC 24 |
| Finished | Aug 23 06:04:12 AM UTC 24 |
| Peak memory | 237624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564504301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.564504301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3804848103 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 169154777 ps |
| CPU time | 0.73 seconds |
| Started | Aug 23 06:04:07 AM UTC 24 |
| Finished | Aug 23 06:04:08 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804848103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3804848103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.4285701384 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 920995073 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 06:04:08 AM UTC 24 |
| Finished | Aug 23 06:04:13 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285701384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4285701384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2025329624 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 174989045 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 06:04:09 AM UTC 24 |
| Finished | Aug 23 06:04:11 AM UTC 24 |
| Peak memory | 208372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025329624 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2025329624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.237079196 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 225982654 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 06:04:07 AM UTC 24 |
| Finished | Aug 23 06:04:09 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237079196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.237079196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4281782735 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2254583382 ps |
| CPU time | 7.33 seconds |
| Started | Aug 23 06:04:10 AM UTC 24 |
| Finished | Aug 23 06:04:18 AM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281782735 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4281782735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.937807228 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 119649922 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 06:04:09 AM UTC 24 |
| Finished | Aug 23 06:04:11 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937807228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.937807228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3119524177 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 181706810 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:04:08 AM UTC 24 |
| Finished | Aug 23 06:04:10 AM UTC 24 |
| Peak memory | 208300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119524177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3119524177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.1875562972 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 62454355 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 06:04:14 AM UTC 24 |
| Finished | Aug 23 06:04:16 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875562972 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.1875562972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.919568505 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1284504714 ps |
| CPU time | 5.1 seconds |
| Started | Aug 23 06:04:13 AM UTC 24 |
| Finished | Aug 23 06:04:20 AM UTC 24 |
| Peak memory | 241664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919568505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.919568505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1739016172 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 301858313 ps |
| CPU time | 1.06 seconds |
| Started | Aug 23 06:04:13 AM UTC 24 |
| Finished | Aug 23 06:04:15 AM UTC 24 |
| Peak memory | 237684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739016172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1739016172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1079684887 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 112943548 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 06:04:11 AM UTC 24 |
| Finished | Aug 23 06:04:13 AM UTC 24 |
| Peak memory | 207928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079684887 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1079684887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1330669883 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1110753617 ps |
| CPU time | 4.62 seconds |
| Started | Aug 23 06:04:12 AM UTC 24 |
| Finished | Aug 23 06:04:18 AM UTC 24 |
| Peak memory | 209248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330669883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1330669883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.941079818 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 144248976 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 06:04:13 AM UTC 24 |
| Finished | Aug 23 06:04:15 AM UTC 24 |
| Peak memory | 208364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941079818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.941079818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.4180329076 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 115120431 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 06:04:11 AM UTC 24 |
| Finished | Aug 23 06:04:14 AM UTC 24 |
| Peak memory | 207684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180329076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.4180329076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2765562176 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4044138085 ps |
| CPU time | 15.68 seconds |
| Started | Aug 23 06:04:13 AM UTC 24 |
| Finished | Aug 23 06:04:30 AM UTC 24 |
| Peak memory | 209240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765562176 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2765562176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.675497122 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 459027396 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 06:04:12 AM UTC 24 |
| Finished | Aug 23 06:04:16 AM UTC 24 |
| Peak memory | 208932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675497122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.675497122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.2772490203 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 64072035 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 06:04:12 AM UTC 24 |
| Finished | Aug 23 06:04:14 AM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772490203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2772490203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
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