Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8172

1

T2

2

T10

6

T14

7

auto[1]

11245

1

T2

1

T4

4

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5869	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6517	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3113	1			T4	1		T5	1		T11	1
reset_info_cp[4]	3955	1			T4	1		T5	1		T11	1
reset_info_cp[8]	111	1			T10	1		T122	1		T58	1
reset_info_cp[16]	102	1			T106	1		T57	1		T109	1
reset_info_cp[32]	105	1			T14	1		T123	1		T58	1
reset_info_cp[64]	100	1			T98	1		T121	1		T109	2
reset_info_cp[128]	131	1			T10	1		T14	1		T106	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3120	1			T57	3		T98	4		T99	9
reset_info_cp[1]	auto[1]	2811	1			T4	1		T5	1		T11	1
reset_info_cp[2]	auto[0]	1017	1			T57	9		T98	8		T99	4
reset_info_cp[2]	auto[1]	2096	1			T4	1		T5	1		T11	1
reset_info_cp[4]	auto[0]	1425	1			T57	5		T98	3		T99	6
reset_info_cp[4]	auto[1]	2530	1			T4	1		T5	1		T11	1
reset_info_cp[8]	auto[0]	42	1			T10	1		T39	1		T127	1
reset_info_cp[8]	auto[1]	69	1			T122	1		T58	1		T45	2
reset_info_cp[16]	auto[0]	39	1			T106	1		T109	1		T123	1
reset_info_cp[16]	auto[1]	63	1			T57	1		T44	1		T54	1
reset_info_cp[32]	auto[0]	45	1			T14	1		T123	1		T54	1
reset_info_cp[32]	auto[1]	60	1			T58	1		T37	1		T27	1
reset_info_cp[64]	auto[0]	40	1			T98	1		T121	1		T109	2
reset_info_cp[64]	auto[1]	60	1			T58	3		T45	1		T36	1
reset_info_cp[128]	auto[0]	44	1			T10	1		T14	1		T106	1
reset_info_cp[128]	auto[1]	87	1			T105	1		T58	1		T44	2