| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.45 | 99.40 | 99.24 | 100.00 | 99.83 | 99.46 | 98.77 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 80.20 | 80.20 | 95.53 | 95.53 | 76.47 | 76.47 | 80.31 | 80.31 | 94.83 | 94.83 | 89.23 | 89.23 | 44.83 | 44.83 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3096096219 | ||
| 88.96 | 8.76 | 97.26 | 1.73 | 84.52 | 8.05 | 91.37 | 11.06 | 97.67 | 2.83 | 92.73 | 3.50 | 70.20 | 25.37 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.22652942 | ||
| 91.99 | 3.03 | 97.38 | 0.12 | 93.75 | 9.23 | 92.17 | 0.80 | 97.83 | 0.17 | 93.94 | 1.21 | 76.85 | 6.65 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1500985952 | ||
| 94.12 | 2.13 | 98.27 | 0.89 | 95.84 | 2.08 | 92.75 | 0.59 | 99.00 | 1.17 | 94.35 | 0.40 | 84.48 | 7.64 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4074335059 | ||
| 95.59 | 1.47 | 98.69 | 0.42 | 96.04 | 0.21 | 95.81 | 3.06 | 99.33 | 0.33 | 94.48 | 0.13 | 89.16 | 4.68 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2656933073 | ||
| 96.89 | 1.30 | 99.11 | 0.42 | 96.53 | 0.49 | 98.24 | 2.43 | 99.67 | 0.33 | 98.12 | 3.63 | 89.66 | 0.49 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2856517855 | ||
| 97.81 | 0.92 | 99.11 | 0.00 | 98.20 | 1.67 | 98.24 | 0.00 | 99.83 | 0.17 | 98.38 | 0.27 | 93.10 | 3.45 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2503399037 | ||
| 98.33 | 0.52 | 99.40 | 0.30 | 98.61 | 0.42 | 99.16 | 0.92 | 99.83 | 0.00 | 98.38 | 0.00 | 94.58 | 1.48 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1420262560 | ||
| 98.64 | 0.31 | 99.40 | 0.00 | 98.61 | 0.00 | 99.16 | 0.00 | 99.83 | 0.00 | 98.52 | 0.13 | 96.31 | 1.72 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1641508620 | ||
| 98.80 | 0.16 | 99.40 | 0.00 | 98.61 | 0.00 | 99.16 | 0.00 | 99.83 | 0.00 | 98.52 | 0.00 | 97.29 | 0.99 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4066537760 | ||
| 98.97 | 0.16 | 99.40 | 0.00 | 98.61 | 0.00 | 99.16 | 0.00 | 99.83 | 0.00 | 98.52 | 0.00 | 98.28 | 0.99 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2839817044 | ||
| 99.11 | 0.14 | 99.40 | 0.00 | 98.61 | 0.00 | 99.75 | 0.59 | 99.83 | 0.00 | 98.79 | 0.27 | 98.28 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.673725050 | ||
| 99.19 | 0.08 | 99.40 | 0.00 | 98.82 | 0.21 | 99.75 | 0.00 | 99.83 | 0.00 | 98.79 | 0.00 | 98.52 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3751453035 | ||
| 99.25 | 0.06 | 99.40 | 0.00 | 98.82 | 0.00 | 99.75 | 0.00 | 99.83 | 0.00 | 98.92 | 0.13 | 98.77 | 0.25 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.366540266 | ||
| 99.30 | 0.05 | 99.40 | 0.00 | 98.82 | 0.00 | 99.92 | 0.17 | 99.83 | 0.00 | 99.06 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2783694604 | ||
| 99.35 | 0.05 | 99.40 | 0.00 | 99.10 | 0.28 | 99.92 | 0.00 | 99.83 | 0.00 | 99.06 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2011884968 | ||
| 99.39 | 0.04 | 99.40 | 0.00 | 99.10 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.27 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3162083307 | ||
| 99.41 | 0.02 | 99.40 | 0.00 | 99.10 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.46 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3615222490 | ||
| 99.43 | 0.01 | 99.40 | 0.00 | 99.10 | 0.00 | 100.00 | 0.08 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2167369879 | ||
| 99.44 | 0.01 | 99.40 | 0.00 | 99.17 | 0.07 | 100.00 | 0.00 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.648733538 | ||
| 99.45 | 0.01 | 99.40 | 0.00 | 99.24 | 0.07 | 100.00 | 0.00 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1264239993 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.765766491 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.149011956 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4080978935 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4214521417 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2995045208 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.667581646 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2347242185 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1707531801 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4163130410 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4272732953 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3694075275 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2207561427 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3920380494 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3286560370 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2264393512 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2060355920 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3604929271 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3713402070 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4201038914 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1592731320 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2559266673 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.402038565 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3214672344 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1903182172 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.239744194 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4198288403 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1566495835 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3410013505 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3213179647 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1809774509 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.805554891 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.991945741 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2350399056 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3958903250 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2587098361 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2470526275 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3075462601 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.4251907473 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2340807043 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1887444398 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1436701322 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3714625218 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2756272045 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2896817093 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3259197508 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1571259183 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4110494929 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.967544449 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2217027921 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.347076545 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.945214066 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1143185477 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.707571037 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.556474496 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.387763727 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.769229518 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.648184456 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2084596286 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2586229566 |
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| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2320885960 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1820410400 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2930596874 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.704272045 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.134348087 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3344801020 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.806991443 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2949219627 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.7478222 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.101319153 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.252535132 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2938135509 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.51424185 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.463201482 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1519181022 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2849084093 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.2837636967 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.4119460410 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3164968424 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3317977606 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.758433206 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1577302437 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4259097411 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1088639936 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.565679805 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.717768129 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.2166902263 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2954734188 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1180185981 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2634341598 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2654393915 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2166836138 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1161882168 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.862905127 |
| /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1098542662 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1206312996 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:07:59 AM UTC 24 | 118523147 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1487810130 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:07:59 AM UTC 24 | 68239412 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1420262560 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:07:59 AM UTC 24 | 74773973 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4066537760 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:00 AM UTC 24 | 143859621 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3096096219 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:00 AM UTC 24 | 125159831 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2167369879 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:00 AM UTC 24 | 301449850 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3269253872 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 325568314 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.366540266 | Aug 25 04:07:58 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 157244826 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1137815915 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 64314488 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3361838402 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 123035670 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1075477242 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 101615318 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.4095079123 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:01 AM UTC 24 | 157778031 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4020098423 | Aug 25 04:07:58 AM UTC 24 | Aug 25 04:08:02 AM UTC 24 | 197283805 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1687917336 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:02 AM UTC 24 | 302700732 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.315798671 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:02 AM UTC 24 | 154535941 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4038495172 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:02 AM UTC 24 | 146824099 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2028955949 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:02 AM UTC 24 | 189940267 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1740968076 | Aug 25 04:08:00 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 64406305 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.223812618 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 344829933 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.864043181 | Aug 25 04:08:00 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 152026566 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.22652942 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 350905348 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3714224633 | Aug 25 04:08:01 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 106082889 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3830706942 | Aug 25 04:08:00 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 301777398 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1120594252 | Aug 25 04:08:00 AM UTC 24 | Aug 25 04:08:03 AM UTC 24 | 123990128 ps | ||
| T106 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2839817044 | Aug 25 04:08:01 AM UTC 24 | Aug 25 04:08:04 AM UTC 24 | 156826957 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1500985952 | Aug 25 04:08:10 AM UTC 24 | Aug 25 04:08:17 AM UTC 24 | 772741147 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3610924228 | Aug 25 04:08:01 AM UTC 24 | Aug 25 04:08:04 AM UTC 24 | 301993871 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1214001889 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:04 AM UTC 24 | 53828677 ps | ||
| T111 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.293180975 | Aug 25 04:08:01 AM UTC 24 | Aug 25 04:08:05 AM UTC 24 | 252291106 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3838937199 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:05 AM UTC 24 | 138107722 ps | ||
| T107 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.258824983 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:05 AM UTC 24 | 156405359 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2958427967 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:05 AM UTC 24 | 252611752 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.1712550636 | Aug 25 04:08:03 AM UTC 24 | Aug 25 04:08:06 AM UTC 24 | 74040145 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2375706276 | Aug 25 04:08:04 AM UTC 24 | Aug 25 04:08:06 AM UTC 24 | 96065179 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.339585065 | Aug 25 04:08:03 AM UTC 24 | Aug 25 04:08:06 AM UTC 24 | 98400416 ps | ||
| T108 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.4190424483 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:06 AM UTC 24 | 276696689 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1884553405 | Aug 25 04:08:03 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 301120140 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.950991428 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 1196409566 ps | ||
| T112 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.280298950 | Aug 25 04:08:04 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 191165455 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3416686763 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 1139923392 ps | ||
| T156 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4029200158 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 67115940 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4026366659 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:07 AM UTC 24 | 107992095 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.4139257611 | Aug 25 04:08:01 AM UTC 24 | Aug 25 04:08:08 AM UTC 24 | 761818925 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2887236696 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:14 AM UTC 24 | 1155788335 ps | ||
| T109 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.4038988595 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:08 AM UTC 24 | 257202606 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3536529205 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:08 AM UTC 24 | 301481555 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.3561057815 | Aug 25 04:08:06 AM UTC 24 | Aug 25 04:08:08 AM UTC 24 | 123955773 ps | ||
| T110 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3344801020 | Aug 25 04:08:06 AM UTC 24 | Aug 25 04:08:09 AM UTC 24 | 107154110 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3524356247 | Aug 25 04:08:05 AM UTC 24 | Aug 25 04:08:09 AM UTC 24 | 301989220 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1820410400 | Aug 25 04:08:06 AM UTC 24 | Aug 25 04:08:09 AM UTC 24 | 158405996 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2980832419 | Aug 25 04:08:02 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 838625902 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2930596874 | Aug 25 04:08:06 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 247362179 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1796808097 | Aug 25 04:08:08 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 63858671 ps | ||
| T159 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.29666477 | Aug 25 04:08:08 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 302331175 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.51424185 | Aug 25 04:08:08 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 114111544 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2656933073 | Aug 25 04:07:57 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 1968127912 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.101319153 | Aug 25 04:08:08 AM UTC 24 | Aug 25 04:08:10 AM UTC 24 | 199208384 ps | ||
| T63 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.134348087 | Aug 25 04:08:06 AM UTC 24 | Aug 25 04:08:11 AM UTC 24 | 349905101 ps | ||
| T44 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.3931443969 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:11 AM UTC 24 | 1972667736 ps | ||
| T49 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2849084093 | Aug 25 04:08:09 AM UTC 24 | Aug 25 04:08:12 AM UTC 24 | 180414000 ps | ||
| T45 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.278601330 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:17 AM UTC 24 | 2463802035 ps | ||
| T50 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2938135509 | Aug 25 04:08:09 AM UTC 24 | Aug 25 04:08:12 AM UTC 24 | 169413500 ps | ||
| T51 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1519181022 | Aug 25 04:08:09 AM UTC 24 | Aug 25 04:08:12 AM UTC 24 | 113744504 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.7478222 | Aug 25 04:08:09 AM UTC 24 | Aug 25 04:08:12 AM UTC 24 | 302988319 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.806991443 | Aug 25 04:08:10 AM UTC 24 | Aug 25 04:08:12 AM UTC 24 | 74063697 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1022439826 | Aug 25 04:07:59 AM UTC 24 | Aug 25 04:08:13 AM UTC 24 | 2193463064 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3317977606 | Aug 25 04:08:10 AM UTC 24 | Aug 25 04:08:13 AM UTC 24 | 226241899 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.565679805 | Aug 25 04:08:10 AM UTC 24 | Aug 25 04:08:13 AM UTC 24 | 125605998 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1577302437 | Aug 25 04:08:10 AM UTC 24 | Aug 25 04:08:14 AM UTC 24 | 248987670 ps | ||
| T150 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.2837636967 | Aug 25 04:08:12 AM UTC 24 | Aug 25 04:08:14 AM UTC 24 | 66105214 ps | ||
| T151 | /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.758433206 | Aug 25 04:08:12 AM UTC 24 | Aug 25 04:08:14 AM UTC 24 | 107277459 ps | ||
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