Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.40 99.24 100.00 99.83 99.46 98.77


Total tests in report: 586
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
80.20 80.20 95.53 95.53 76.47 76.47 80.31 80.31 94.83 94.83 89.23 89.23 44.83 44.83 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3096096219
88.96 8.76 97.26 1.73 84.52 8.05 91.37 11.06 97.67 2.83 92.73 3.50 70.20 25.37 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.22652942
91.99 3.03 97.38 0.12 93.75 9.23 92.17 0.80 97.83 0.17 93.94 1.21 76.85 6.65 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1500985952
94.12 2.13 98.27 0.89 95.84 2.08 92.75 0.59 99.00 1.17 94.35 0.40 84.48 7.64 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4074335059
95.59 1.47 98.69 0.42 96.04 0.21 95.81 3.06 99.33 0.33 94.48 0.13 89.16 4.68 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2656933073
96.89 1.30 99.11 0.42 96.53 0.49 98.24 2.43 99.67 0.33 98.12 3.63 89.66 0.49 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2856517855
97.81 0.92 99.11 0.00 98.20 1.67 98.24 0.00 99.83 0.17 98.38 0.27 93.10 3.45 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2503399037
98.33 0.52 99.40 0.30 98.61 0.42 99.16 0.92 99.83 0.00 98.38 0.00 94.58 1.48 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1420262560
98.64 0.31 99.40 0.00 98.61 0.00 99.16 0.00 99.83 0.00 98.52 0.13 96.31 1.72 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1641508620
98.80 0.16 99.40 0.00 98.61 0.00 99.16 0.00 99.83 0.00 98.52 0.00 97.29 0.99 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4066537760
98.97 0.16 99.40 0.00 98.61 0.00 99.16 0.00 99.83 0.00 98.52 0.00 98.28 0.99 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2839817044
99.11 0.14 99.40 0.00 98.61 0.00 99.75 0.59 99.83 0.00 98.79 0.27 98.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.673725050
99.19 0.08 99.40 0.00 98.82 0.21 99.75 0.00 99.83 0.00 98.79 0.00 98.52 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3751453035
99.25 0.06 99.40 0.00 98.82 0.00 99.75 0.00 99.83 0.00 98.92 0.13 98.77 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.366540266
99.30 0.05 99.40 0.00 98.82 0.00 99.92 0.17 99.83 0.00 99.06 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2783694604
99.35 0.05 99.40 0.00 99.10 0.28 99.92 0.00 99.83 0.00 99.06 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2011884968
99.39 0.04 99.40 0.00 99.10 0.00 99.92 0.00 99.83 0.00 99.33 0.27 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3162083307
99.41 0.02 99.40 0.00 99.10 0.00 99.92 0.00 99.83 0.00 99.46 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3615222490
99.43 0.01 99.40 0.00 99.10 0.00 100.00 0.08 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2167369879
99.44 0.01 99.40 0.00 99.17 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.648733538
99.45 0.01 99.40 0.00 99.24 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1264239993

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.765766491
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.149011956
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4080978935
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4214521417
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2995045208
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.667581646
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2347242185
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1707531801
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4163130410
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4272732953
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3694075275
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2207561427
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3920380494
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3286560370
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2264393512
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2060355920
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3604929271
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3713402070
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4201038914
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1592731320
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2559266673
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.402038565
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3214672344
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1903182172
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.239744194
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4198288403
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1566495835
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3410013505
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3213179647
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1809774509
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2025789188
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1115866119
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.805554891
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.991945741
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2350399056
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3958903250
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.628375326
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1635750193
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2587098361
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3269892943
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2470526275
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3075462601
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.4251907473
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3516870151
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2340807043
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1887444398
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1436701322
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3714625218
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2756272045
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2896817093
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3259197508
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1571259183
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4110494929
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.967544449
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2217027921
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.347076545
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.945214066
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2861119894
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1143185477
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.707571037
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.556474496
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.387763727
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.769229518
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.648184456
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2084596286
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2586229566
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2250514088
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.983821337
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.995445291
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1219723008
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.535046000
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2435436654
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3964126975
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1040665320
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.891716297
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1419958168
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3777959772
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.1738783254
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.603225164
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1206312996
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.950991428
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.4150247480
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2419046178
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3269253872
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1487810130
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1137815915
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.3931443969
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1687917336
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3416686763
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1075477242
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4020098423
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.2511795811
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.223812618
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3361838402
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1626805075
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.625523883
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.674065597
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.251831939
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4005828619
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.260510464
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2874884135
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.3887642848
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3178028873
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/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2166836138
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1161882168
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.862905127
/workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1098542662



Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1206312996 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 118523147 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1487810130 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 68239412 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1420262560 Aug 25 04:07:57 AM UTC 24 Aug 25 04:07:59 AM UTC 24 74773973 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4066537760 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:00 AM UTC 24 143859621 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3096096219 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:00 AM UTC 24 125159831 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2167369879 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:00 AM UTC 24 301449850 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3269253872 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:01 AM UTC 24 325568314 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.366540266 Aug 25 04:07:58 AM UTC 24 Aug 25 04:08:01 AM UTC 24 157244826 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1137815915 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:01 AM UTC 24 64314488 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3361838402 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:01 AM UTC 24 123035670 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1075477242 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:01 AM UTC 24 101615318 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.4095079123 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:01 AM UTC 24 157778031 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4020098423 Aug 25 04:07:58 AM UTC 24 Aug 25 04:08:02 AM UTC 24 197283805 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1687917336 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:02 AM UTC 24 302700732 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.315798671 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:02 AM UTC 24 154535941 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4038495172 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:02 AM UTC 24 146824099 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2028955949 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:02 AM UTC 24 189940267 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1740968076 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:03 AM UTC 24 64406305 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.223812618 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:03 AM UTC 24 344829933 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.864043181 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:03 AM UTC 24 152026566 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.22652942 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:03 AM UTC 24 350905348 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3714224633 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:03 AM UTC 24 106082889 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3830706942 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:03 AM UTC 24 301777398 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1120594252 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:03 AM UTC 24 123990128 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2839817044 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:04 AM UTC 24 156826957 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1500985952 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:17 AM UTC 24 772741147 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3610924228 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:04 AM UTC 24 301993871 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1214001889 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:04 AM UTC 24 53828677 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.293180975 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:05 AM UTC 24 252291106 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3838937199 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:05 AM UTC 24 138107722 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.258824983 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:05 AM UTC 24 156405359 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2958427967 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:05 AM UTC 24 252611752 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.1712550636 Aug 25 04:08:03 AM UTC 24 Aug 25 04:08:06 AM UTC 24 74040145 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2375706276 Aug 25 04:08:04 AM UTC 24 Aug 25 04:08:06 AM UTC 24 96065179 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.339585065 Aug 25 04:08:03 AM UTC 24 Aug 25 04:08:06 AM UTC 24 98400416 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.4190424483 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:06 AM UTC 24 276696689 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1884553405 Aug 25 04:08:03 AM UTC 24 Aug 25 04:08:07 AM UTC 24 301120140 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.950991428 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:07 AM UTC 24 1196409566 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.280298950 Aug 25 04:08:04 AM UTC 24 Aug 25 04:08:07 AM UTC 24 191165455 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3416686763 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:07 AM UTC 24 1139923392 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4029200158 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:07 AM UTC 24 67115940 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4026366659 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:07 AM UTC 24 107992095 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.4139257611 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:08 AM UTC 24 761818925 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2887236696 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:14 AM UTC 24 1155788335 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.4038988595 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:08 AM UTC 24 257202606 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3536529205 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:08 AM UTC 24 301481555 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.3561057815 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:08 AM UTC 24 123955773 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3344801020 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:09 AM UTC 24 107154110 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3524356247 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:09 AM UTC 24 301989220 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1820410400 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:09 AM UTC 24 158405996 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2980832419 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:10 AM UTC 24 838625902 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2930596874 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:10 AM UTC 24 247362179 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1796808097 Aug 25 04:08:08 AM UTC 24 Aug 25 04:08:10 AM UTC 24 63858671 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.29666477 Aug 25 04:08:08 AM UTC 24 Aug 25 04:08:10 AM UTC 24 302331175 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.51424185 Aug 25 04:08:08 AM UTC 24 Aug 25 04:08:10 AM UTC 24 114111544 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2656933073 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:10 AM UTC 24 1968127912 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.101319153 Aug 25 04:08:08 AM UTC 24 Aug 25 04:08:10 AM UTC 24 199208384 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.134348087 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:11 AM UTC 24 349905101 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.3931443969 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:11 AM UTC 24 1972667736 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2849084093 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:12 AM UTC 24 180414000 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.278601330 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:17 AM UTC 24 2463802035 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2938135509 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:12 AM UTC 24 169413500 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1519181022 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:12 AM UTC 24 113744504 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.7478222 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:12 AM UTC 24 302988319 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.806991443 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:12 AM UTC 24 74063697 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1022439826 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:13 AM UTC 24 2193463064 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3317977606 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:13 AM UTC 24 226241899 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.565679805 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:13 AM UTC 24 125605998 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1577302437 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:14 AM UTC 24 248987670 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.2837636967 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:14 AM UTC 24 66105214 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.758433206 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:14 AM UTC 24 107277459 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1180185981 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:14 AM UTC 24 144911485 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3164968424 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:15 AM UTC 24 309285251 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.748846636 Aug 25 04:08:01 AM UTC 24 Aug 25 04:08:15 AM UTC 24 2260798204 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2166836138 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:15 AM UTC 24 198122901 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4043657871 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:16 AM UTC 24 1946262964 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1088639936 Aug 25 04:08:10 AM UTC 24 Aug 25 04:08:16 AM UTC 24 557859273 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.823911919 Aug 25 04:08:03 AM UTC 24 Aug 25 04:08:16 AM UTC 24 1941041603 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1098542662 Aug 25 04:08:13 AM UTC 24 Aug 25 04:08:16 AM UTC 24 167483773 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2654393915 Aug 25 04:08:13 AM UTC 24 Aug 25 04:08:16 AM UTC 24 160522273 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2954734188 Aug 25 04:08:13 AM UTC 24 Aug 25 04:08:16 AM UTC 24 301290109 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4259097411 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:17 AM UTC 24 474193379 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.717768129 Aug 25 04:08:15 AM UTC 24 Aug 25 04:08:17 AM UTC 24 68650800 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.251831939 Aug 25 04:08:15 AM UTC 24 Aug 25 04:08:17 AM UTC 24 225573793 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2320885960 Aug 25 04:08:06 AM UTC 24 Aug 25 04:08:17 AM UTC 24 1539957818 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.862905127 Aug 25 04:08:13 AM UTC 24 Aug 25 04:08:17 AM UTC 24 345690658 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.260510464 Aug 25 04:08:15 AM UTC 24 Aug 25 04:08:17 AM UTC 24 123940284 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3178028873 Aug 25 04:08:15 AM UTC 24 Aug 25 04:08:17 AM UTC 24 147119080 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4005828619 Aug 25 04:08:16 AM UTC 24 Aug 25 04:08:19 AM UTC 24 159659594 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.673725050 Aug 25 04:08:07 AM UTC 24 Aug 25 04:08:19 AM UTC 24 1954672172 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.674065597 Aug 25 04:08:16 AM UTC 24 Aug 25 04:08:19 AM UTC 24 302734813 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1626805075 Aug 25 04:08:17 AM UTC 24 Aug 25 04:08:19 AM UTC 24 72365058 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.3887642848 Aug 25 04:08:16 AM UTC 24 Aug 25 04:08:19 AM UTC 24 135747955 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.638230661 Aug 25 04:08:17 AM UTC 24 Aug 25 04:08:21 AM UTC 24 117940536 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.252535132 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:21 AM UTC 24 1903496559 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2634341598 Aug 25 04:08:12 AM UTC 24 Aug 25 04:08:21 AM UTC 24 1463966225 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.2511795811 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:22 AM UTC 24 3110224917 ps
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T30 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.625523883 Aug 25 04:08:16 AM UTC 24 Aug 25 04:08:25 AM UTC 24 1269371438 ps
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T73 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.2414729765 Aug 25 04:08:03 AM UTC 24 Aug 25 04:08:28 AM UTC 24 8310504162 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3162083307 Aug 25 04:08:15 AM UTC 24 Aug 25 04:08:28 AM UTC 24 1987348186 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1782118561 Aug 25 04:08:28 AM UTC 24 Aug 25 04:08:30 AM UTC 24 75365441 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.10979182 Aug 25 04:08:17 AM UTC 24 Aug 25 04:08:31 AM UTC 24 166818643 ps
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T168 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.2674536993 Aug 25 04:08:28 AM UTC 24 Aug 25 04:08:31 AM UTC 24 124866481 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2856517855 Aug 25 04:07:59 AM UTC 24 Aug 25 04:08:32 AM UTC 24 8288349507 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.4002447189 Aug 25 04:08:17 AM UTC 24 Aug 25 04:08:32 AM UTC 24 325445545 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.4085232794 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:33 AM UTC 24 5945626954 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1641508620 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:33 AM UTC 24 5528747817 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2419046178 Aug 25 04:07:57 AM UTC 24 Aug 25 04:08:35 AM UTC 24 5696534307 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3412838641 Aug 25 04:08:17 AM UTC 24 Aug 25 04:08:35 AM UTC 24 882999926 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.3728291274 Aug 25 04:08:00 AM UTC 24 Aug 25 04:08:36 AM UTC 24 16538112086 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2264517327 Aug 25 04:08:20 AM UTC 24 Aug 25 04:08:37 AM UTC 24 382833212 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.1069294516 Aug 25 04:08:18 AM UTC 24 Aug 25 04:08:38 AM UTC 24 1274073816 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.2623845062 Aug 25 04:08:05 AM UTC 24 Aug 25 04:08:42 AM UTC 24 9211487702 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.463201482 Aug 25 04:08:09 AM UTC 24 Aug 25 04:08:42 AM UTC 24 8511850933 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.704272045 Aug 25 04:08:08 AM UTC 24 Aug 25 04:08:43 AM UTC 24 8260506160 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2874884135 Aug 25 04:08:16 AM UTC 24 Aug 25 04:08:45 AM UTC 24 5472867533 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3603287547 Aug 25 04:08:19 AM UTC 24 Aug 25 04:08:45 AM UTC 24 912491031 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.3143727196 Aug 25 04:08:36 AM UTC 24 Aug 25 04:08:46 AM UTC 24 299496773 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3209404865 Aug 25 04:08:33 AM UTC 24 Aug 25 04:08:46 AM UTC 24 306856584 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3255868346 Aug 25 04:08:02 AM UTC 24 Aug 25 04:08:47 AM UTC 24 17634203611 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2593880818 Aug 25 04:08:20 AM UTC 24 Aug 25 04:08:55 AM UTC 24 107567858 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2779168947 Aug 25 04:08:20 AM UTC 24 Aug 25 04:08:55 AM UTC 24 302943252 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.600911208 Aug 25 04:08:46 AM UTC 24 Aug 25 04:08:56 AM UTC 24 302664685 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2914928287 Aug 25 04:08:22 AM UTC 24 Aug 25 04:08:56 AM UTC 24 235820503 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3498349897 Aug 25 04:08:22 AM UTC 24 Aug 25 04:08:56 AM UTC 24 82287358 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.330781931 Aug 25 04:08:36 AM UTC 24 Aug 25 04:08:56 AM UTC 24 109236971 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.675704222 Aug 25 04:08:22 AM UTC 24 Aug 25 04:08:56 AM UTC 24 116317000 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1283628245 Aug 25 04:08:47 AM UTC 24 Aug 25 04:09:00 AM UTC 24 235830721 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.198221145 Aug 25 04:08:39 AM UTC 24 Aug 25 04:09:00 AM UTC 24 74240286 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.2020317017 Aug 25 04:08:47 AM UTC 24 Aug 25 04:09:01 AM UTC 24 63034350 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.435051017 Aug 25 04:08:37 AM UTC 24 Aug 25 04:09:01 AM UTC 24 302332559 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2362618653 Aug 25 04:08:19 AM UTC 24 Aug 25 04:09:01 AM UTC 24 62024030 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2434597889 Aug 25 04:08:42 AM UTC 24 Aug 25 04:09:01 AM UTC 24 69946626 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1399809018 Aug 25 04:08:32 AM UTC 24 Aug 25 04:09:01 AM UTC 24 300868662 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.4286211973 Aug 25 04:08:59 AM UTC 24 Aug 25 04:09:01 AM UTC 24 132985607 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2416607380 Aug 25 04:08:59 AM UTC 24 Aug 25 04:09:01 AM UTC 24 156909007 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.2447005635 Aug 25 04:08:58 AM UTC 24 Aug 25 04:09:01 AM UTC 24 69399796 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3255013496 Aug 25 04:08:19 AM UTC 24 Aug 25 04:09:01 AM UTC 24 186777888 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4030684057 Aug 25 04:08:32 AM UTC 24 Aug 25 04:09:02 AM UTC 24 143901614 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.500050298 Aug 25 04:08:58 AM UTC 24 Aug 25 04:09:02 AM UTC 24 112731571 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.251128921 Aug 25 04:08:26 AM UTC 24 Aug 25 04:09:02 AM UTC 24 302498608 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.2387266906 Aug 25 04:08:19 AM UTC 24 Aug 25 04:09:02 AM UTC 24 127108667 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.1817352704 Aug 25 04:08:19 AM UTC 24 Aug 25 04:09:02 AM UTC 24 152566342 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.377860246 Aug 25 04:08:47 AM UTC 24 Aug 25 04:09:02 AM UTC 24 252790568 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.2656405997 Aug 25 04:08:20 AM UTC 24 Aug 25 04:09:02 AM UTC 24 2242220427 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1258137567 Aug 25 04:08:31 AM UTC 24 Aug 25 04:09:03 AM UTC 24 382331211 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3822362244 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:05 AM UTC 24 178452101 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1023338513 Aug 25 04:08:42 AM UTC 24 Aug 25 04:09:05 AM UTC 24 838501777 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.1078040284 Aug 25 04:08:37 AM UTC 24 Aug 25 04:09:05 AM UTC 24 1281256909 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3924822935 Aug 25 04:08:45 AM UTC 24 Aug 25 04:09:06 AM UTC 24 1264837547 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.4185034278 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:06 AM UTC 24 73073259 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.1856878656 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:06 AM UTC 24 118581182 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.136649921 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:07 AM UTC 24 82731150 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3742971083 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:07 AM UTC 24 69361674 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1161882168 Aug 25 04:08:14 AM UTC 24 Aug 25 04:09:07 AM UTC 24 15650938621 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.2162762993 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:07 AM UTC 24 124121015 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2098738632 Aug 25 04:08:24 AM UTC 24 Aug 25 04:09:07 AM UTC 24 107039875 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.1876096893 Aug 25 04:08:24 AM UTC 24 Aug 25 04:09:07 AM UTC 24 134330022 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3902971443 Aug 25 04:08:32 AM UTC 24 Aug 25 04:09:07 AM UTC 24 1963999420 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1327166396 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:07 AM UTC 24 302498066 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3977045355 Aug 25 04:08:24 AM UTC 24 Aug 25 04:09:07 AM UTC 24 117451411 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1726231264 Aug 25 04:08:20 AM UTC 24 Aug 25 04:09:07 AM UTC 24 2996396307 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.1933130560 Aug 25 04:08:43 AM UTC 24 Aug 25 04:09:07 AM UTC 24 128233022 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2946780473 Aug 25 04:09:01 AM UTC 24 Aug 25 04:09:07 AM UTC 24 101780869 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1936829998 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:07 AM UTC 24 242274077 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1998470404 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:07 AM UTC 24 302996309 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.686461079 Aug 25 04:08:26 AM UTC 24 Aug 25 04:09:08 AM UTC 24 1970997871 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2943774559 Aug 25 04:08:59 AM UTC 24 Aug 25 04:09:09 AM UTC 24 2052677366 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.4007258574 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:10 AM UTC 24 67107605 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.2488855528 Aug 25 04:09:01 AM UTC 24 Aug 25 04:09:10 AM UTC 24 117909005 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.605029005 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:11 AM UTC 24 146162523 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1023241724 Aug 25 04:09:01 AM UTC 24 Aug 25 04:09:11 AM UTC 24 301029977 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3088726677 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:11 AM UTC 24 60914803 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3864687217 Aug 25 04:09:05 AM UTC 24 Aug 25 04:09:11 AM UTC 24 171868536 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.1552995611 Aug 25 04:08:24 AM UTC 24 Aug 25 04:09:11 AM UTC 24 1942162874 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.3829748538 Aug 25 04:08:29 AM UTC 24 Aug 25 04:09:12 AM UTC 24 78824726 ps
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T229 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.3744871261 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:12 AM UTC 24 201413036 ps
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T231 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.793270648 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:12 AM UTC 24 112831940 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.781939749 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:12 AM UTC 24 1550537355 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.4068329942 Aug 25 04:09:09 AM UTC 24 Aug 25 04:09:12 AM UTC 24 203452901 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2754908764 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:12 AM UTC 24 302107831 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.89392019 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:12 AM UTC 24 247374054 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.4039587989 Aug 25 04:09:11 AM UTC 24 Aug 25 04:09:13 AM UTC 24 61573529 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.3182861001 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:14 AM UTC 24 725660355 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.179030341 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:14 AM UTC 24 974459697 ps
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T239 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3773249119 Aug 25 04:08:29 AM UTC 24 Aug 25 04:09:15 AM UTC 24 116371680 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.1252934684 Aug 25 04:09:12 AM UTC 24 Aug 25 04:09:15 AM UTC 24 240772944 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.593511874 Aug 25 04:09:10 AM UTC 24 Aug 25 04:09:15 AM UTC 24 302122632 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1986074535 Aug 25 04:09:06 AM UTC 24 Aug 25 04:09:15 AM UTC 24 187404892 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.835066353 Aug 25 04:09:07 AM UTC 24 Aug 25 04:09:15 AM UTC 24 301114740 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.2469467970 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:15 AM UTC 24 61193883 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.336086397 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:16 AM UTC 24 105108661 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.1832859603 Aug 25 04:08:40 AM UTC 24 Aug 25 04:09:16 AM UTC 24 119234828 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1429907881 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:16 AM UTC 24 302202361 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.2802624136 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:16 AM UTC 24 211105972 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.1056081957 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:16 AM UTC 24 2583427750 ps
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T251 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.773226525 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:16 AM UTC 24 168776399 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3208277461 Aug 25 04:08:44 AM UTC 24 Aug 25 04:09:17 AM UTC 24 101147147 ps
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T253 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2060895430 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:17 AM UTC 24 110494248 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3779401784 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:17 AM UTC 24 205612588 ps
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T256 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.3943375910 Aug 25 04:09:06 AM UTC 24 Aug 25 04:09:17 AM UTC 24 404031421 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.1863389779 Aug 25 04:08:43 AM UTC 24 Aug 25 04:09:17 AM UTC 24 133737988 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.2939836561 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:17 AM UTC 24 127197566 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.222392050 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:18 AM UTC 24 386702950 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.1740379904 Aug 25 04:08:19 AM UTC 24 Aug 25 04:09:19 AM UTC 24 12757417517 ps
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T260 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.2158956497 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:21 AM UTC 24 1536533632 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3226849326 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:21 AM UTC 24 1112419107 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.1346042818 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:21 AM UTC 24 70456980 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.3958975556 Aug 25 04:09:14 AM UTC 24 Aug 25 04:09:21 AM UTC 24 1273459099 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.3276947048 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:21 AM UTC 24 85164692 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3372678345 Aug 25 04:09:06 AM UTC 24 Aug 25 04:09:21 AM UTC 24 1960792717 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2783694604 Aug 25 04:08:57 AM UTC 24 Aug 25 04:09:21 AM UTC 24 1280368984 ps
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T265 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.1095553996 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:22 AM UTC 24 114982133 ps
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T267 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4292723179 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:22 AM UTC 24 302277219 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.877746603 Aug 25 04:09:12 AM UTC 24 Aug 25 04:09:22 AM UTC 24 108650713 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.599654258 Aug 25 04:09:08 AM UTC 24 Aug 25 04:09:22 AM UTC 24 111287480 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2575065982 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:22 AM UTC 24 185620741 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.320228890 Aug 25 04:09:13 AM UTC 24 Aug 25 04:09:22 AM UTC 24 1963926151 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.883214139 Aug 25 04:09:12 AM UTC 24 Aug 25 04:09:22 AM UTC 24 262371781 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3409736560 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:22 AM UTC 24 1971968950 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.2956868601 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:23 AM UTC 24 143650570 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.2806324977 Aug 25 04:09:03 AM UTC 24 Aug 25 04:09:23 AM UTC 24 4235473354 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.344689903 Aug 25 04:09:09 AM UTC 24 Aug 25 04:09:25 AM UTC 24 95164271 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1391742658 Aug 25 04:09:16 AM UTC 24 Aug 25 04:09:25 AM UTC 24 92032182 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.116412786 Aug 25 04:09:23 AM UTC 24 Aug 25 04:09:25 AM UTC 24 62152361 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.1808587772 Aug 25 04:09:19 AM UTC 24 Aug 25 04:09:26 AM UTC 24 279119067 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1881826480 Aug 25 04:09:16 AM UTC 24 Aug 25 04:09:25 AM UTC 24 182487997 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3200794464 Aug 25 04:09:12 AM UTC 24 Aug 25 04:09:25 AM UTC 24 1205032324 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.375787211 Aug 25 04:09:23 AM UTC 24 Aug 25 04:09:26 AM UTC 24 222708340 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3422395005 Aug 25 04:09:23 AM UTC 24 Aug 25 04:09:26 AM UTC 24 119579184 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.2657148387 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:26 AM UTC 24 1243126438 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1595064358 Aug 25 04:09:20 AM UTC 24 Aug 25 04:09:26 AM UTC 24 146944685 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1562773809 Aug 25 04:09:23 AM UTC 24 Aug 25 04:09:26 AM UTC 24 151741080 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2445001871 Aug 25 04:09:18 AM UTC 24 Aug 25 04:09:26 AM UTC 24 1635218201 ps
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