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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.40 99.24 100.00 99.83 99.46 98.77


Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T68 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2995045208 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:04 AM UTC 24 75704376 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4080978935 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:05 AM UTC 24 122499049 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3615222490 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:05 AM UTC 24 165947478 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.765766491 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:06 AM UTC 24 155526898 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4272732953 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:06 AM UTC 24 87193258 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4074335059 Aug 25 04:10:17 AM UTC 24 Aug 25 04:10:27 AM UTC 24 936286404 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2207561427 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:06 AM UTC 24 80074512 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.945214066 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:06 AM UTC 24 76873550 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4214521417 Aug 25 04:10:03 AM UTC 24 Aug 25 04:10:06 AM UTC 24 124109457 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.667581646 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:06 AM UTC 24 412491428 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3920380494 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:06 AM UTC 24 82070105 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.387763727 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:06 AM UTC 24 101403762 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.648184456 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 80359909 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2217027921 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 136327884 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3694075275 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 133207597 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1707531801 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 202112235 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2347242185 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:07 AM UTC 24 877406833 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2861119894 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 133070454 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.347076545 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:07 AM UTC 24 172567336 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1143185477 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:08 AM UTC 24 298369276 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2586229566 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:08 AM UTC 24 152691337 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2250514088 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:08 AM UTC 24 426945316 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4110494929 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:08 AM UTC 24 266873448 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.648733538 Aug 25 04:10:03 AM UTC 24 Aug 25 04:10:08 AM UTC 24 991502014 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1264239993 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:08 AM UTC 24 893700305 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2503399037 Aug 25 04:10:03 AM UTC 24 Aug 25 04:10:09 AM UTC 24 397613268 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2264393512 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:10 AM UTC 24 57108169 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2060355920 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:10 AM UTC 24 76025114 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2084596286 Aug 25 04:10:05 AM UTC 24 Aug 25 04:10:11 AM UTC 24 120563740 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.769229518 Aug 25 04:10:05 AM UTC 24 Aug 25 04:10:11 AM UTC 24 178524611 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1040665320 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:11 AM UTC 24 194458881 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.707571037 Aug 25 04:10:05 AM UTC 24 Aug 25 04:10:11 AM UTC 24 114036423 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3604929271 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:12 AM UTC 24 807659094 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.1738783254 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:12 AM UTC 24 127233063 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2011884968 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:13 AM UTC 24 514706949 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2435436654 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:13 AM UTC 24 422368287 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.967544449 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:14 AM UTC 24 1552496766 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4163130410 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:14 AM UTC 24 1566001448 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.149011956 Aug 25 04:10:02 AM UTC 24 Aug 25 04:10:14 AM UTC 24 2305807414 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.535046000 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:15 AM UTC 24 63039427 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1219723008 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:15 AM UTC 24 100943110 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.556474496 Aug 25 04:10:04 AM UTC 24 Aug 25 04:10:15 AM UTC 24 2292753143 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2025789188 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:15 AM UTC 24 82817984 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.891716297 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:15 AM UTC 24 134781380 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.805554891 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:15 AM UTC 24 79161823 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1115866119 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:15 AM UTC 24 103787116 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.991945741 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:16 AM UTC 24 146452014 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3213179647 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:16 AM UTC 24 135191849 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.628375326 Aug 25 04:10:14 AM UTC 24 Aug 25 04:10:16 AM UTC 24 108776517 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1635750193 Aug 25 04:10:14 AM UTC 24 Aug 25 04:10:16 AM UTC 24 160400319 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.983821337 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:16 AM UTC 24 407037680 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3964126975 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:16 AM UTC 24 821618730 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3958903250 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:17 AM UTC 24 773361850 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2350399056 Aug 25 04:10:12 AM UTC 24 Aug 25 04:10:17 AM UTC 24 391956608 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3751453035 Aug 25 04:10:13 AM UTC 24 Aug 25 04:10:17 AM UTC 24 892748430 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2587098361 Aug 25 04:10:13 AM UTC 24 Aug 25 04:10:18 AM UTC 24 477991352 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1809774509 Aug 25 04:10:11 AM UTC 24 Aug 25 04:10:20 AM UTC 24 88148888 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3410013505 Aug 25 04:10:11 AM UTC 24 Aug 25 04:10:20 AM UTC 24 83748179 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1419958168 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:21 AM UTC 24 85077683 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3777959772 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:21 AM UTC 24 142404504 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.995445291 Aug 25 04:10:06 AM UTC 24 Aug 25 04:10:22 AM UTC 24 1549453743 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.603225164 Aug 25 04:10:08 AM UTC 24 Aug 25 04:10:23 AM UTC 24 802498595 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1887444398 Aug 25 04:10:17 AM UTC 24 Aug 25 04:10:24 AM UTC 24 58324366 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3286560370 Aug 25 04:10:09 AM UTC 24 Aug 25 04:10:25 AM UTC 24 167899512 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3075462601 Aug 25 04:10:16 AM UTC 24 Aug 25 04:10:25 AM UTC 24 133605715 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1592731320 Aug 25 04:10:10 AM UTC 24 Aug 25 04:10:25 AM UTC 24 216912530 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.402038565 Aug 25 04:10:10 AM UTC 24 Aug 25 04:10:26 AM UTC 24 574699140 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2559266673 Aug 25 04:10:09 AM UTC 24 Aug 25 04:10:26 AM UTC 24 445532768 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3269892943 Aug 25 04:10:16 AM UTC 24 Aug 25 04:10:35 AM UTC 24 127078834 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1436701322 Aug 25 04:10:16 AM UTC 24 Aug 25 04:10:36 AM UTC 24 104954097 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4201038914 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:05 AM UTC 24 63617251 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3713402070 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:05 AM UTC 24 116067557 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1903182172 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:05 AM UTC 24 56690606 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2896817093 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:06 AM UTC 24 76873626 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2756272045 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:06 AM UTC 24 87231859 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.239744194 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:06 AM UTC 24 219400723 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3714625218 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:06 AM UTC 24 99992319 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3214672344 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:06 AM UTC 24 172651704 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2470526275 Aug 25 04:10:15 AM UTC 24 Aug 25 04:11:17 AM UTC 24 69855379 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2340807043 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:06 AM UTC 24 126944259 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4198288403 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:07 AM UTC 24 191492542 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1566495835 Aug 25 04:10:10 AM UTC 24 Aug 25 04:11:07 AM UTC 24 420235697 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1571259183 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:07 AM UTC 24 473583217 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3259197508 Aug 25 04:10:17 AM UTC 24 Aug 25 04:11:07 AM UTC 24 236913816 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3516870151 Aug 25 04:10:15 AM UTC 24 Aug 25 04:11:19 AM UTC 24 422238744 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.4251907473 Aug 25 04:10:15 AM UTC 24 Aug 25 04:11:19 AM UTC 24 184566311 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3096096219
Short name T5
Test name
Test status
Simulation time 125159831 ps
CPU time 1.85 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096096219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3096096219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.22652942
Short name T67
Test name
Test status
Simulation time 350905348 ps
CPU time 3.1 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 209032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22652942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.22652942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1500985952
Short name T57
Test name
Test status
Simulation time 772741147 ps
CPU time 5.52 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500985952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.1500985952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.4074335059
Short name T75
Test name
Test status
Simulation time 936286404 ps
CPU time 3 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:10:27 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074335059 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.4074335059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2656933073
Short name T58
Test name
Test status
Simulation time 1968127912 ps
CPU time 11.91 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 241724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656933073 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2656933073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2856517855
Short name T74
Test name
Test status
Simulation time 8288349507 ps
CPU time 31.25 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:32 AM UTC 24
Peak memory 241864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856517855 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2856517855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.2503399037
Short name T92
Test name
Test status
Simulation time 397613268 ps
CPU time 3.76 seconds
Started Aug 25 04:10:03 AM UTC 24
Finished Aug 25 04:10:09 AM UTC 24
Peak memory 221924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503399037 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.2503399037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.1420262560
Short name T3
Test name
Test status
Simulation time 74773973 ps
CPU time 1.12 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420262560 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.1420262560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1641508620
Short name T131
Test name
Test status
Simulation time 5528747817 ps
CPU time 31.78 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:33 AM UTC 24
Peak memory 225308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641508620 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1641508620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4066537760
Short name T4
Test name
Test status
Simulation time 143859621 ps
CPU time 1.54 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:00 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066537760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4066537760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.2839817044
Short name T106
Test name
Test status
Simulation time 156826957 ps
CPU time 1.85 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:04 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839817044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2839817044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.673725050
Short name T28
Test name
Test status
Simulation time 1954672172 ps
CPU time 10.24 seconds
Started Aug 25 04:08:07 AM UTC 24
Finished Aug 25 04:08:19 AM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673725050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.673725050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3751453035
Short name T96
Test name
Test status
Simulation time 892748430 ps
CPU time 2.61 seconds
Started Aug 25 04:10:13 AM UTC 24
Finished Aug 25 04:10:17 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751453035 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.3751453035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.366540266
Short name T8
Test name
Test status
Simulation time 157244826 ps
CPU time 1.41 seconds
Started Aug 25 04:07:58 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366540266 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.366540266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.2783694604
Short name T47
Test name
Test status
Simulation time 1280368984 ps
CPU time 6.11 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 242400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783694604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.2783694604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.2011884968
Short name T102
Test name
Test status
Simulation time 514706949 ps
CPU time 3.37 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:13 AM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011884968 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2011884968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3162083307
Short name T85
Test name
Test status
Simulation time 1987348186 ps
CPU time 12.11 seconds
Started Aug 25 04:08:15 AM UTC 24
Finished Aug 25 04:08:28 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162083307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3162083307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3615222490
Short name T70
Test name
Test status
Simulation time 165947478 ps
CPU time 1.46 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:05 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615222490 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.3615222490
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2167369879
Short name T6
Test name
Test status
Simulation time 301449850 ps
CPU time 1.87 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:00 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167369879 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2167369879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.648733538
Short name T94
Test name
Test status
Simulation time 991502014 ps
CPU time 3.73 seconds
Started Aug 25 04:10:03 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648733538 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.648733538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1264239993
Short name T93
Test name
Test status
Simulation time 893700305 ps
CPU time 3.47 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264239993 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.1264239993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.765766491
Short name T71
Test name
Test status
Simulation time 155526898 ps
CPU time 2.32 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765766491 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.765766491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.149011956
Short name T544
Test name
Test status
Simulation time 2305807414 ps
CPU time 10.36 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:14 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149011956 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.149011956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.4080978935
Short name T69
Test name
Test status
Simulation time 122499049 ps
CPU time 1.36 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:05 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080978935 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.4080978935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4214521417
Short name T76
Test name
Test status
Simulation time 124109457 ps
CPU time 1.55 seconds
Started Aug 25 04:10:03 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4214521417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w
ith_rand_reset.4214521417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.2995045208
Short name T68
Test name
Test status
Simulation time 75704376 ps
CPU time 0.96 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995045208 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.2995045208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.667581646
Short name T77
Test name
Test status
Simulation time 412491428 ps
CPU time 3.16 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 225224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667581646 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.667581646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2347242185
Short name T79
Test name
Test status
Simulation time 877406833 ps
CPU time 3.61 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 208792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347242185 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.2347242185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.1707531801
Short name T154
Test name
Test status
Simulation time 202112235 ps
CPU time 1.77 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707531801 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.1707531801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4163130410
Short name T543
Test name
Test status
Simulation time 1566001448 ps
CPU time 8.8 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:14 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163130410 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4163130410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4272732953
Short name T536
Test name
Test status
Simulation time 87193258 ps
CPU time 1.15 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272732953 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.4272732953
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3694075275
Short name T78
Test name
Test status
Simulation time 133207597 ps
CPU time 1.76 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3694075275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w
ith_rand_reset.3694075275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2207561427
Short name T128
Test name
Test status
Simulation time 80074512 ps
CPU time 1.3 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207561427 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.2207561427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3920380494
Short name T135
Test name
Test status
Simulation time 82070105 ps
CPU time 1.46 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920380494 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3920380494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3286560370
Short name T565
Test name
Test status
Simulation time 167899512 ps
CPU time 1.12 seconds
Started Aug 25 04:10:09 AM UTC 24
Finished Aug 25 04:10:25 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3286560370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_
with_rand_reset.3286560370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2264393512
Short name T138
Test name
Test status
Simulation time 57108169 ps
CPU time 0.91 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264393512 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2264393512
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2060355920
Short name T139
Test name
Test status
Simulation time 76025114 ps
CPU time 0.88 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060355920 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.2060355920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3604929271
Short name T101
Test name
Test status
Simulation time 807659094 ps
CPU time 2.67 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:12 AM UTC 24
Peak memory 208608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604929271 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.3604929271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3713402070
Short name T572
Test name
Test status
Simulation time 116067557 ps
CPU time 1.14 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:05 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3713402070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_
with_rand_reset.3713402070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.4201038914
Short name T571
Test name
Test status
Simulation time 63617251 ps
CPU time 0.87 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:05 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201038914 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.4201038914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1592731320
Short name T567
Test name
Test status
Simulation time 216912530 ps
CPU time 1.41 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:10:25 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592731320 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1592731320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2559266673
Short name T568
Test name
Test status
Simulation time 445532768 ps
CPU time 2.59 seconds
Started Aug 25 04:10:09 AM UTC 24
Finished Aug 25 04:10:26 AM UTC 24
Peak memory 217644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559266673 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2559266673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.402038565
Short name T97
Test name
Test status
Simulation time 574699140 ps
CPU time 1.96 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:10:26 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402038565 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.402038565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3214672344
Short name T578
Test name
Test status
Simulation time 172651704 ps
CPU time 2 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 217264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3214672344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_
with_rand_reset.3214672344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1903182172
Short name T573
Test name
Test status
Simulation time 56690606 ps
CPU time 1.04 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:05 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903182172 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1903182172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.239744194
Short name T576
Test name
Test status
Simulation time 219400723 ps
CPU time 1.85 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239744194 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.239744194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.4198288403
Short name T581
Test name
Test status
Simulation time 191492542 ps
CPU time 2.83 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:07 AM UTC 24
Peak memory 225292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198288403 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.4198288403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.1566495835
Short name T582
Test name
Test status
Simulation time 420235697 ps
CPU time 2.97 seconds
Started Aug 25 04:10:10 AM UTC 24
Finished Aug 25 04:11:07 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566495835 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.1566495835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.3410013505
Short name T560
Test name
Test status
Simulation time 83748179 ps
CPU time 0.94 seconds
Started Aug 25 04:10:11 AM UTC 24
Finished Aug 25 04:10:20 AM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410013505 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.3410013505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3213179647
Short name T551
Test name
Test status
Simulation time 135191849 ps
CPU time 1.36 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3213179647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_
with_rand_reset.3213179647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1809774509
Short name T559
Test name
Test status
Simulation time 88148888 ps
CPU time 0.74 seconds
Started Aug 25 04:10:11 AM UTC 24
Finished Aug 25 04:10:20 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809774509 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1809774509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2025789188
Short name T142
Test name
Test status
Simulation time 82817984 ps
CPU time 0.88 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025789188 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.2025789188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1115866119
Short name T549
Test name
Test status
Simulation time 103787116 ps
CPU time 0.79 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1115866119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_
with_rand_reset.1115866119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.805554891
Short name T548
Test name
Test status
Simulation time 79161823 ps
CPU time 0.84 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805554891 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.805554891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.991945741
Short name T550
Test name
Test status
Simulation time 146452014 ps
CPU time 1.1 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991945741 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.991945741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2350399056
Short name T557
Test name
Test status
Simulation time 391956608 ps
CPU time 2.54 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:17 AM UTC 24
Peak memory 217760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350399056 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2350399056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3958903250
Short name T556
Test name
Test status
Simulation time 773361850 ps
CPU time 2.37 seconds
Started Aug 25 04:10:12 AM UTC 24
Finished Aug 25 04:10:17 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958903250 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3958903250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.628375326
Short name T552
Test name
Test status
Simulation time 108776517 ps
CPU time 0.96 seconds
Started Aug 25 04:10:14 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=628375326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_w
ith_rand_reset.628375326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1635750193
Short name T553
Test name
Test status
Simulation time 160400319 ps
CPU time 1.08 seconds
Started Aug 25 04:10:14 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635750193 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.1635750193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2587098361
Short name T558
Test name
Test status
Simulation time 477991352 ps
CPU time 2.79 seconds
Started Aug 25 04:10:13 AM UTC 24
Finished Aug 25 04:10:18 AM UTC 24
Peak memory 217544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587098361 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2587098361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.3269892943
Short name T569
Test name
Test status
Simulation time 127078834 ps
CPU time 0.92 seconds
Started Aug 25 04:10:16 AM UTC 24
Finished Aug 25 04:10:35 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3269892943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_
with_rand_reset.3269892943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2470526275
Short name T579
Test name
Test status
Simulation time 69855379 ps
CPU time 1.06 seconds
Started Aug 25 04:10:15 AM UTC 24
Finished Aug 25 04:11:17 AM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470526275 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2470526275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3075462601
Short name T566
Test name
Test status
Simulation time 133605715 ps
CPU time 1.11 seconds
Started Aug 25 04:10:16 AM UTC 24
Finished Aug 25 04:10:25 AM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075462601 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.3075462601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.4251907473
Short name T586
Test name
Test status
Simulation time 184566311 ps
CPU time 3.48 seconds
Started Aug 25 04:10:15 AM UTC 24
Finished Aug 25 04:11:19 AM UTC 24
Peak memory 221832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251907473 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.4251907473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3516870151
Short name T585
Test name
Test status
Simulation time 422238744 ps
CPU time 2.9 seconds
Started Aug 25 04:10:15 AM UTC 24
Finished Aug 25 04:11:19 AM UTC 24
Peak memory 208784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516870151 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.3516870151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2340807043
Short name T580
Test name
Test status
Simulation time 126944259 ps
CPU time 1.29 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2340807043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_
with_rand_reset.2340807043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1887444398
Short name T564
Test name
Test status
Simulation time 58324366 ps
CPU time 0.73 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:10:24 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887444398 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1887444398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1436701322
Short name T570
Test name
Test status
Simulation time 104954097 ps
CPU time 1.3 seconds
Started Aug 25 04:10:16 AM UTC 24
Finished Aug 25 04:10:36 AM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436701322 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1436701322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3714625218
Short name T577
Test name
Test status
Simulation time 99992319 ps
CPU time 1.21 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3714625218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_
with_rand_reset.3714625218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.2756272045
Short name T575
Test name
Test status
Simulation time 87231859 ps
CPU time 1.12 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756272045 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.2756272045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2896817093
Short name T574
Test name
Test status
Simulation time 76873626 ps
CPU time 1.34 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:06 AM UTC 24
Peak memory 207784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896817093 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.2896817093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.3259197508
Short name T584
Test name
Test status
Simulation time 236913816 ps
CPU time 1.97 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:07 AM UTC 24
Peak memory 219692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259197508 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.3259197508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1571259183
Short name T583
Test name
Test status
Simulation time 473583217 ps
CPU time 2.23 seconds
Started Aug 25 04:10:17 AM UTC 24
Finished Aug 25 04:11:07 AM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571259183 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1571259183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.4110494929
Short name T539
Test name
Test status
Simulation time 266873448 ps
CPU time 2.62 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 208728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110494929 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.4110494929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.967544449
Short name T542
Test name
Test status
Simulation time 1552496766 ps
CPU time 8.51 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:14 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967544449 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.967544449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2217027921
Short name T538
Test name
Test status
Simulation time 136327884 ps
CPU time 1.52 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217027921 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2217027921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.347076545
Short name T80
Test name
Test status
Simulation time 172567336 ps
CPU time 1.8 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=347076545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_wi
th_rand_reset.347076545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.945214066
Short name T134
Test name
Test status
Simulation time 76873550 ps
CPU time 1.07 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945214066 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.945214066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2861119894
Short name T137
Test name
Test status
Simulation time 133070454 ps
CPU time 1.87 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861119894 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.2861119894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1143185477
Short name T89
Test name
Test status
Simulation time 298369276 ps
CPU time 2.46 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 217700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143185477 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.1143185477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.707571037
Short name T540
Test name
Test status
Simulation time 114036423 ps
CPU time 1.45 seconds
Started Aug 25 04:10:05 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707571037 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.707571037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.556474496
Short name T546
Test name
Test status
Simulation time 2292753143 ps
CPU time 9.41 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556474496 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.556474496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.387763727
Short name T537
Test name
Test status
Simulation time 101403762 ps
CPU time 1.05 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387763727 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.387763727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.769229518
Short name T116
Test name
Test status
Simulation time 178524611 ps
CPU time 1.19 seconds
Started Aug 25 04:10:05 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=769229518 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_wi
th_rand_reset.769229518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.648184456
Short name T136
Test name
Test status
Simulation time 80359909 ps
CPU time 1.09 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648184456 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.648184456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.2084596286
Short name T140
Test name
Test status
Simulation time 120563740 ps
CPU time 1.06 seconds
Started Aug 25 04:10:05 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084596286 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.2084596286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2586229566
Short name T91
Test name
Test status
Simulation time 152691337 ps
CPU time 2.28 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 225088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586229566 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2586229566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.2250514088
Short name T90
Test name
Test status
Simulation time 426945316 ps
CPU time 2.33 seconds
Started Aug 25 04:10:04 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250514088 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.2250514088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.983821337
Short name T554
Test name
Test status
Simulation time 407037680 ps
CPU time 2.4 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983821337 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.983821337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.995445291
Short name T563
Test name
Test status
Simulation time 1549453743 ps
CPU time 7.62 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:22 AM UTC 24
Peak memory 208288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995445291 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.995445291
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.1219723008
Short name T545
Test name
Test status
Simulation time 100943110 ps
CPU time 0.87 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219723008 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.1219723008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.535046000
Short name T141
Test name
Test status
Simulation time 63039427 ps
CPU time 0.85 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535046000 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.535046000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2435436654
Short name T95
Test name
Test status
Simulation time 422368287 ps
CPU time 2.95 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:13 AM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435436654 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2435436654
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3964126975
Short name T555
Test name
Test status
Simulation time 821618730 ps
CPU time 2.62 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964126975 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3964126975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1040665320
Short name T117
Test name
Test status
Simulation time 194458881 ps
CPU time 1.37 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1040665320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w
ith_rand_reset.1040665320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.891716297
Short name T547
Test name
Test status
Simulation time 134781380 ps
CPU time 1.17 seconds
Started Aug 25 04:10:06 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891716297 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.891716297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1419958168
Short name T561
Test name
Test status
Simulation time 85077683 ps
CPU time 0.87 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:21 AM UTC 24
Peak memory 207584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419958168 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1419958168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.3777959772
Short name T562
Test name
Test status
Simulation time 142404504 ps
CPU time 1.12 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:21 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777959772 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.3777959772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.1738783254
Short name T541
Test name
Test status
Simulation time 127233063 ps
CPU time 1.95 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:12 AM UTC 24
Peak memory 219692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738783254 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.1738783254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.603225164
Short name T100
Test name
Test status
Simulation time 802498595 ps
CPU time 2.87 seconds
Started Aug 25 04:10:08 AM UTC 24
Finished Aug 25 04:10:23 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603225164 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.603225164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1206312996
Short name T1
Test name
Test status
Simulation time 118523147 ps
CPU time 1.25 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206312996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1206312996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.950991428
Short name T98
Test name
Test status
Simulation time 1196409566 ps
CPU time 8.66 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950991428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.950991428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.4150247480
Short name T72
Test name
Test status
Simulation time 8725557547 ps
CPU time 24.45 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:23 AM UTC 24
Peak memory 241808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150247480 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.4150247480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.2419046178
Short name T132
Test name
Test status
Simulation time 5696534307 ps
CPU time 36.35 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:35 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419046178 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.2419046178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.3269253872
Short name T7
Test name
Test status
Simulation time 325568314 ps
CPU time 2.7 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269253872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3269253872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1487810130
Short name T2
Test name
Test status
Simulation time 68239412 ps
CPU time 1.18 seconds
Started Aug 25 04:07:57 AM UTC 24
Finished Aug 25 04:07:59 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487810130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1487810130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1137815915
Short name T9
Test name
Test status
Simulation time 64314488 ps
CPU time 1.16 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137815915 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1137815915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.3931443969
Short name T44
Test name
Test status
Simulation time 1972667736 ps
CPU time 11.4 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:11 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931443969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3931443969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.1687917336
Short name T25
Test name
Test status
Simulation time 302700732 ps
CPU time 1.87 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:02 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687917336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.1687917336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.3416686763
Short name T99
Test name
Test status
Simulation time 1139923392 ps
CPU time 7.57 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416686763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3416686763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1075477242
Short name T11
Test name
Test status
Simulation time 101615318 ps
CPU time 1.52 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075477242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.1075477242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4020098423
Short name T13
Test name
Test status
Simulation time 197283805 ps
CPU time 2.03 seconds
Started Aug 25 04:07:58 AM UTC 24
Finished Aug 25 04:08:02 AM UTC 24
Peak memory 209116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020098423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4020098423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.2511795811
Short name T127
Test name
Test status
Simulation time 3110224917 ps
CPU time 22.22 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:22 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511795811 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.2511795811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.223812618
Short name T66
Test name
Test status
Simulation time 344829933 ps
CPU time 3.09 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223812618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.223812618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3361838402
Short name T10
Test name
Test status
Simulation time 123035670 ps
CPU time 1.53 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361838402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3361838402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1626805075
Short name T166
Test name
Test status
Simulation time 72365058 ps
CPU time 1.22 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:19 AM UTC 24
Peak memory 207688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626805075 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1626805075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.625523883
Short name T30
Test name
Test status
Simulation time 1269371438 ps
CPU time 7.64 seconds
Started Aug 25 04:08:16 AM UTC 24
Finished Aug 25 04:08:25 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625523883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.625523883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.674065597
Short name T165
Test name
Test status
Simulation time 302734813 ps
CPU time 1.95 seconds
Started Aug 25 04:08:16 AM UTC 24
Finished Aug 25 04:08:19 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674065597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.674065597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.251831939
Short name T161
Test name
Test status
Simulation time 225573793 ps
CPU time 1.59 seconds
Started Aug 25 04:08:15 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251831939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.251831939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4005828619
Short name T164
Test name
Test status
Simulation time 159659594 ps
CPU time 1.94 seconds
Started Aug 25 04:08:16 AM UTC 24
Finished Aug 25 04:08:19 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005828619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.4005828619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.260510464
Short name T162
Test name
Test status
Simulation time 123940284 ps
CPU time 1.96 seconds
Started Aug 25 04:08:15 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260510464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.260510464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2874884135
Short name T175
Test name
Test status
Simulation time 5472867533 ps
CPU time 27.24 seconds
Started Aug 25 04:08:16 AM UTC 24
Finished Aug 25 04:08:45 AM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874884135 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2874884135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.3887642848
Short name T115
Test name
Test status
Simulation time 135747955 ps
CPU time 2.62 seconds
Started Aug 25 04:08:16 AM UTC 24
Finished Aug 25 04:08:19 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887642848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.3887642848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.3178028873
Short name T163
Test name
Test status
Simulation time 147119080 ps
CPU time 1.72 seconds
Started Aug 25 04:08:15 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178028873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.3178028873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2362618653
Short name T190
Test name
Test status
Simulation time 62024030 ps
CPU time 0.9 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362618653 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2362618653
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.1069294516
Short name T172
Test name
Test status
Simulation time 1274073816 ps
CPU time 9.03 seconds
Started Aug 25 04:08:18 AM UTC 24
Finished Aug 25 04:08:38 AM UTC 24
Peak memory 241372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069294516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.1069294516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.10979182
Short name T87
Test name
Test status
Simulation time 166818643 ps
CPU time 1.37 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:31 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10979182 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.10979182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3412838641
Short name T170
Test name
Test status
Simulation time 882999926 ps
CPU time 5.52 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:35 AM UTC 24
Peak memory 209168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412838641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3412838641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.638230661
Short name T167
Test name
Test status
Simulation time 117940536 ps
CPU time 1.73 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:21 AM UTC 24
Peak memory 207996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638230661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.638230661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.1740379904
Short name T148
Test name
Test status
Simulation time 12757417517 ps
CPU time 38.87 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:09:19 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740379904 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.1740379904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.4002447189
Short name T169
Test name
Test status
Simulation time 325445545 ps
CPU time 2.91 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:32 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002447189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.4002447189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.3453811103
Short name T88
Test name
Test status
Simulation time 126784085 ps
CPU time 1.61 seconds
Started Aug 25 04:08:17 AM UTC 24
Finished Aug 25 04:08:31 AM UTC 24
Peak memory 208292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453811103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.3453811103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.3498349897
Short name T183
Test name
Test status
Simulation time 82287358 ps
CPU time 1.19 seconds
Started Aug 25 04:08:22 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498349897 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.3498349897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.2656405997
Short name T203
Test name
Test status
Simulation time 2242220427 ps
CPU time 8.06 seconds
Started Aug 25 04:08:20 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 242160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656405997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.2656405997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2779168947
Short name T180
Test name
Test status
Simulation time 302943252 ps
CPU time 1.18 seconds
Started Aug 25 04:08:20 AM UTC 24
Finished Aug 25 04:08:55 AM UTC 24
Peak memory 237456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779168947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2779168947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3255013496
Short name T196
Test name
Test status
Simulation time 186777888 ps
CPU time 1.49 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255013496 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3255013496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3603287547
Short name T176
Test name
Test status
Simulation time 912491031 ps
CPU time 5.17 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:08:45 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603287547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3603287547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.2593880818
Short name T179
Test name
Test status
Simulation time 107567858 ps
CPU time 1.16 seconds
Started Aug 25 04:08:20 AM UTC 24
Finished Aug 25 04:08:55 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593880818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.2593880818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.2387266906
Short name T200
Test name
Test status
Simulation time 127108667 ps
CPU time 1.79 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387266906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.2387266906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.1726231264
Short name T216
Test name
Test status
Simulation time 2996396307 ps
CPU time 12.59 seconds
Started Aug 25 04:08:20 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 218296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726231264 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.1726231264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.2264517327
Short name T171
Test name
Test status
Simulation time 382833212 ps
CPU time 2.41 seconds
Started Aug 25 04:08:20 AM UTC 24
Finished Aug 25 04:08:37 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264517327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.2264517327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.1817352704
Short name T201
Test name
Test status
Simulation time 152566342 ps
CPU time 1.59 seconds
Started Aug 25 04:08:19 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817352704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1817352704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1782118561
Short name T86
Test name
Test status
Simulation time 75365441 ps
CPU time 1.21 seconds
Started Aug 25 04:08:28 AM UTC 24
Finished Aug 25 04:08:30 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782118561 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1782118561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.686461079
Short name T34
Test name
Test status
Simulation time 1970997871 ps
CPU time 7.49 seconds
Started Aug 25 04:08:26 AM UTC 24
Finished Aug 25 04:09:08 AM UTC 24
Peak memory 242212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686461079 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.686461079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.251128921
Short name T199
Test name
Test status
Simulation time 302498608 ps
CPU time 1.48 seconds
Started Aug 25 04:08:26 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 236976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251128921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.251128921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2914928287
Short name T182
Test name
Test status
Simulation time 235820503 ps
CPU time 1.07 seconds
Started Aug 25 04:08:22 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914928287 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2914928287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.1552995611
Short name T146
Test name
Test status
Simulation time 1942162874 ps
CPU time 6.42 seconds
Started Aug 25 04:08:24 AM UTC 24
Finished Aug 25 04:09:11 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552995611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.1552995611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2098738632
Short name T212
Test name
Test status
Simulation time 107039875 ps
CPU time 1.56 seconds
Started Aug 25 04:08:24 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098738632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2098738632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.675704222
Short name T185
Test name
Test status
Simulation time 116317000 ps
CPU time 1.39 seconds
Started Aug 25 04:08:22 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675704222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.675704222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3977045355
Short name T215
Test name
Test status
Simulation time 117451411 ps
CPU time 2.03 seconds
Started Aug 25 04:08:24 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977045355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3977045355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.1876096893
Short name T213
Test name
Test status
Simulation time 134330022 ps
CPU time 1.63 seconds
Started Aug 25 04:08:24 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 206940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876096893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.1876096893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.1763436860
Short name T288
Test name
Test status
Simulation time 68489749 ps
CPU time 1.13 seconds
Started Aug 25 04:08:34 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763436860 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.1763436860
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3902971443
Short name T33
Test name
Test status
Simulation time 1963999420 ps
CPU time 7.24 seconds
Started Aug 25 04:08:32 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 241732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902971443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3902971443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.1399809018
Short name T192
Test name
Test status
Simulation time 300868662 ps
CPU time 1.33 seconds
Started Aug 25 04:08:32 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 237332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399809018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.1399809018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.3829748538
Short name T227
Test name
Test status
Simulation time 78824726 ps
CPU time 1.08 seconds
Started Aug 25 04:08:29 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829748538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.3829748538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.3727269116
Short name T361
Test name
Test status
Simulation time 1409423882 ps
CPU time 6.35 seconds
Started Aug 25 04:08:29 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727269116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.3727269116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.4030684057
Short name T197
Test name
Test status
Simulation time 143901614 ps
CPU time 1.77 seconds
Started Aug 25 04:08:32 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030684057 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.4030684057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.2674536993
Short name T168
Test name
Test status
Simulation time 124866481 ps
CPU time 1.98 seconds
Started Aug 25 04:08:28 AM UTC 24
Finished Aug 25 04:08:31 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674536993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2674536993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.3209404865
Short name T178
Test name
Test status
Simulation time 306856584 ps
CPU time 2.33 seconds
Started Aug 25 04:08:33 AM UTC 24
Finished Aug 25 04:08:46 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209404865 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.3209404865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1258137567
Short name T204
Test name
Test status
Simulation time 382331211 ps
CPU time 3.31 seconds
Started Aug 25 04:08:31 AM UTC 24
Finished Aug 25 04:09:03 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258137567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1258137567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.3773249119
Short name T239
Test name
Test status
Simulation time 116371680 ps
CPU time 1.01 seconds
Started Aug 25 04:08:29 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773249119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.3773249119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.198221145
Short name T187
Test name
Test status
Simulation time 74240286 ps
CPU time 0.84 seconds
Started Aug 25 04:08:39 AM UTC 24
Finished Aug 25 04:09:00 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198221145 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.198221145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.1078040284
Short name T60
Test name
Test status
Simulation time 1281256909 ps
CPU time 5.63 seconds
Started Aug 25 04:08:37 AM UTC 24
Finished Aug 25 04:09:05 AM UTC 24
Peak memory 241616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078040284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1078040284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.435051017
Short name T189
Test name
Test status
Simulation time 302332559 ps
CPU time 1.04 seconds
Started Aug 25 04:08:37 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 237632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435051017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.435051017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.1437763557
Short name T286
Test name
Test status
Simulation time 176488909 ps
CPU time 1.04 seconds
Started Aug 25 04:08:34 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437763557 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1437763557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.3137438598
Short name T338
Test name
Test status
Simulation time 1687719642 ps
CPU time 7.13 seconds
Started Aug 25 04:08:34 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137438598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.3137438598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.330781931
Short name T184
Test name
Test status
Simulation time 109236971 ps
CPU time 1.37 seconds
Started Aug 25 04:08:36 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330781931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.330781931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.3515922350
Short name T292
Test name
Test status
Simulation time 121035796 ps
CPU time 1.73 seconds
Started Aug 25 04:08:34 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515922350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3515922350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.155619770
Short name T376
Test name
Test status
Simulation time 12262121967 ps
CPU time 41.68 seconds
Started Aug 25 04:08:39 AM UTC 24
Finished Aug 25 04:09:42 AM UTC 24
Peak memory 220212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155619770 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.155619770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.3143727196
Short name T177
Test name
Test status
Simulation time 299496773 ps
CPU time 1.85 seconds
Started Aug 25 04:08:36 AM UTC 24
Finished Aug 25 04:08:46 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143727196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.3143727196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.3065667390
Short name T287
Test name
Test status
Simulation time 56364203 ps
CPU time 1.15 seconds
Started Aug 25 04:08:34 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065667390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.3065667390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.2020317017
Short name T188
Test name
Test status
Simulation time 63034350 ps
CPU time 1.02 seconds
Started Aug 25 04:08:47 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020317017 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.2020317017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3924822935
Short name T32
Test name
Test status
Simulation time 1264837547 ps
CPU time 6.55 seconds
Started Aug 25 04:08:45 AM UTC 24
Finished Aug 25 04:09:06 AM UTC 24
Peak memory 242376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924822935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3924822935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.600911208
Short name T181
Test name
Test status
Simulation time 302664685 ps
CPU time 1.15 seconds
Started Aug 25 04:08:46 AM UTC 24
Finished Aug 25 04:08:56 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600911208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.600911208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2434597889
Short name T191
Test name
Test status
Simulation time 69946626 ps
CPU time 0.81 seconds
Started Aug 25 04:08:42 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434597889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2434597889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1023338513
Short name T206
Test name
Test status
Simulation time 838501777 ps
CPU time 4.96 seconds
Started Aug 25 04:08:42 AM UTC 24
Finished Aug 25 04:09:05 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023338513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1023338513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.3208277461
Short name T252
Test name
Test status
Simulation time 101147147 ps
CPU time 1.27 seconds
Started Aug 25 04:08:44 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208277461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.3208277461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.1832859603
Short name T246
Test name
Test status
Simulation time 119234828 ps
CPU time 1.76 seconds
Started Aug 25 04:08:40 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832859603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1832859603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3806048717
Short name T147
Test name
Test status
Simulation time 5366821735 ps
CPU time 16.82 seconds
Started Aug 25 04:08:47 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 209020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806048717 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3806048717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.1863389779
Short name T257
Test name
Test status
Simulation time 133737988 ps
CPU time 1.82 seconds
Started Aug 25 04:08:43 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863389779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1863389779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.1933130560
Short name T217
Test name
Test status
Simulation time 128233022 ps
CPU time 1.64 seconds
Started Aug 25 04:08:43 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933130560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.1933130560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.2447005635
Short name T195
Test name
Test status
Simulation time 69399796 ps
CPU time 1.07 seconds
Started Aug 25 04:08:58 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447005635 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2447005635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1327166396
Short name T214
Test name
Test status
Simulation time 302498066 ps
CPU time 1.45 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 237568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327166396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1327166396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1283628245
Short name T186
Test name
Test status
Simulation time 235830721 ps
CPU time 0.9 seconds
Started Aug 25 04:08:47 AM UTC 24
Finished Aug 25 04:09:00 AM UTC 24
Peak memory 208144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283628245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1283628245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3226849326
Short name T261
Test name
Test status
Simulation time 1112419107 ps
CPU time 5.74 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226849326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3226849326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3822362244
Short name T205
Test name
Test status
Simulation time 178452101 ps
CPU time 1.04 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:05 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822362244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3822362244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.377860246
Short name T202
Test name
Test status
Simulation time 252790568 ps
CPU time 2.2 seconds
Started Aug 25 04:08:47 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377860246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.377860246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.1056081957
Short name T249
Test name
Test status
Simulation time 2583427750 ps
CPU time 10.74 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 216832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056081957 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1056081957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.2939836561
Short name T258
Test name
Test status
Simulation time 127197566 ps
CPU time 2.07 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 208436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939836561 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2939836561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.2162762993
Short name T211
Test name
Test status
Simulation time 124121015 ps
CPU time 1.49 seconds
Started Aug 25 04:08:57 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 206464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162762993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.2162762993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.4185034278
Short name T207
Test name
Test status
Simulation time 73073259 ps
CPU time 0.87 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:06 AM UTC 24
Peak memory 207832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185034278 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.4185034278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.2888126224
Short name T61
Test name
Test status
Simulation time 2258016163 ps
CPU time 7.81 seconds
Started Aug 25 04:09:01 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 241788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888126224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2888126224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1023241724
Short name T224
Test name
Test status
Simulation time 301029977 ps
CPU time 1.32 seconds
Started Aug 25 04:09:01 AM UTC 24
Finished Aug 25 04:09:11 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023241724 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1023241724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2416607380
Short name T194
Test name
Test status
Simulation time 156909007 ps
CPU time 0.99 seconds
Started Aug 25 04:08:59 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416607380 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.2416607380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.2943774559
Short name T145
Test name
Test status
Simulation time 2052677366 ps
CPU time 8.53 seconds
Started Aug 25 04:08:59 AM UTC 24
Finished Aug 25 04:09:09 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943774559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2943774559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2946780473
Short name T218
Test name
Test status
Simulation time 101780869 ps
CPU time 1.51 seconds
Started Aug 25 04:09:01 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946780473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2946780473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.500050298
Short name T198
Test name
Test status
Simulation time 112731571 ps
CPU time 1.59 seconds
Started Aug 25 04:08:58 AM UTC 24
Finished Aug 25 04:09:02 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500050298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.500050298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.2806324977
Short name T273
Test name
Test status
Simulation time 4235473354 ps
CPU time 18.11 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:23 AM UTC 24
Peak memory 209236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806324977 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2806324977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.2488855528
Short name T222
Test name
Test status
Simulation time 117909005 ps
CPU time 1.65 seconds
Started Aug 25 04:09:01 AM UTC 24
Finished Aug 25 04:09:10 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488855528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.2488855528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.4286211973
Short name T193
Test name
Test status
Simulation time 132985607 ps
CPU time 1.06 seconds
Started Aug 25 04:08:59 AM UTC 24
Finished Aug 25 04:09:01 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286211973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.4286211973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3742971083
Short name T210
Test name
Test status
Simulation time 69361674 ps
CPU time 1.15 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742971083 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3742971083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3409736560
Short name T62
Test name
Test status
Simulation time 1971968950 ps
CPU time 7.23 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 242368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409736560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3409736560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1998470404
Short name T220
Test name
Test status
Simulation time 302996309 ps
CPU time 1.96 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998470404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1998470404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.1856878656
Short name T208
Test name
Test status
Simulation time 118581182 ps
CPU time 1.26 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:06 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856878656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1856878656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.781939749
Short name T232
Test name
Test status
Simulation time 1550537355 ps
CPU time 6.56 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781939749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.781939749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.2060895430
Short name T253
Test name
Test status
Simulation time 110494248 ps
CPU time 1.46 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060895430 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.2060895430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1936829998
Short name T219
Test name
Test status
Simulation time 242274077 ps
CPU time 2.12 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936829998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1936829998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.353192458
Short name T295
Test name
Test status
Simulation time 6544049982 ps
CPU time 22.25 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:28 AM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353192458 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.353192458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.222392050
Short name T259
Test name
Test status
Simulation time 386702950 ps
CPU time 2.42 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:18 AM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222392050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.222392050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.136649921
Short name T209
Test name
Test status
Simulation time 82731150 ps
CPU time 1.29 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 208148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136649921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.136649921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1740968076
Short name T81
Test name
Test status
Simulation time 64406305 ps
CPU time 1.16 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740968076 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1740968076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.278601330
Short name T45
Test name
Test status
Simulation time 2463802035 ps
CPU time 16.18 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 242440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278601330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.278601330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3830706942
Short name T56
Test name
Test status
Simulation time 301777398 ps
CPU time 2.11 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830706942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3830706942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.4095079123
Short name T12
Test name
Test status
Simulation time 157778031 ps
CPU time 1.45 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:01 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095079123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.4095079123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1022439826
Short name T54
Test name
Test status
Simulation time 2193463064 ps
CPU time 12.68 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:13 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022439826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1022439826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.3728291274
Short name T82
Test name
Test status
Simulation time 16538112086 ps
CPU time 34.31 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:36 AM UTC 24
Peak memory 241860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728291274 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3728291274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.4038495172
Short name T22
Test name
Test status
Simulation time 146824099 ps
CPU time 1.76 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:02 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038495172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.4038495172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2028955949
Short name T23
Test name
Test status
Simulation time 189940267 ps
CPU time 2.06 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:02 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028955949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2028955949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.315798671
Short name T14
Test name
Test status
Simulation time 154535941 ps
CPU time 1.75 seconds
Started Aug 25 04:07:59 AM UTC 24
Finished Aug 25 04:08:02 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315798671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.315798671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.3088726677
Short name T225
Test name
Test status
Simulation time 60914803 ps
CPU time 1.05 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:11 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088726677 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3088726677
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3372678345
Short name T65
Test name
Test status
Simulation time 1960792717 ps
CPU time 7.35 seconds
Started Aug 25 04:09:06 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 242336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372678345 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3372678345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.835066353
Short name T243
Test name
Test status
Simulation time 301114740 ps
CPU time 1.41 seconds
Started Aug 25 04:09:07 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835066353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.835066353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1986074535
Short name T242
Test name
Test status
Simulation time 187404892 ps
CPU time 1.42 seconds
Started Aug 25 04:09:06 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986074535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1986074535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.113828686
Short name T294
Test name
Test status
Simulation time 226613512 ps
CPU time 1.95 seconds
Started Aug 25 04:09:03 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 208320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113828686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.113828686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.2771812604
Short name T365
Test name
Test status
Simulation time 5106898647 ps
CPU time 23.69 seconds
Started Aug 25 04:09:07 AM UTC 24
Finished Aug 25 04:09:38 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771812604 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.2771812604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.3943375910
Short name T256
Test name
Test status
Simulation time 404031421 ps
CPU time 2.22 seconds
Started Aug 25 04:09:06 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943375910 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3943375910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.3864687217
Short name T226
Test name
Test status
Simulation time 171868536 ps
CPU time 1.52 seconds
Started Aug 25 04:09:05 AM UTC 24
Finished Aug 25 04:09:11 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864687217 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.3864687217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.4007258574
Short name T221
Test name
Test status
Simulation time 67107605 ps
CPU time 0.74 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:10 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007258574 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.4007258574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.4231959729
Short name T64
Test name
Test status
Simulation time 1262073332 ps
CPU time 5.14 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:14 AM UTC 24
Peak memory 242376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231959729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.4231959729
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2754908764
Short name T234
Test name
Test status
Simulation time 302107831 ps
CPU time 1.56 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754908764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2754908764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.2137606245
Short name T230
Test name
Test status
Simulation time 203658863 ps
CPU time 1.42 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137606245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2137606245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.3182861001
Short name T237
Test name
Test status
Simulation time 725660355 ps
CPU time 4.66 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:14 AM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182861001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.3182861001
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.599654258
Short name T269
Test name
Test status
Simulation time 111287480 ps
CPU time 1.38 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599654258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.599654258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.3744871261
Short name T229
Test name
Test status
Simulation time 201413036 ps
CPU time 1.47 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744871261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3744871261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.501248577
Short name T298
Test name
Test status
Simulation time 5959459109 ps
CPU time 19.45 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:29 AM UTC 24
Peak memory 217800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501248577 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.501248577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.793270648
Short name T231
Test name
Test status
Simulation time 112831940 ps
CPU time 1.57 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793270648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.793270648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.89392019
Short name T235
Test name
Test status
Simulation time 247374054 ps
CPU time 1.94 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89392019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.89392019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.4039587989
Short name T236
Test name
Test status
Simulation time 61573529 ps
CPU time 0.81 seconds
Started Aug 25 04:09:11 AM UTC 24
Finished Aug 25 04:09:13 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039587989 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.4039587989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3586459005
Short name T46
Test name
Test status
Simulation time 1276241549 ps
CPU time 5.3 seconds
Started Aug 25 04:09:10 AM UTC 24
Finished Aug 25 04:09:19 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586459005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3586459005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.593511874
Short name T241
Test name
Test status
Simulation time 302122632 ps
CPU time 1.36 seconds
Started Aug 25 04:09:10 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593511874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.593511874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.605029005
Short name T223
Test name
Test status
Simulation time 146162523 ps
CPU time 1.11 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:11 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605029005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.605029005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.179030341
Short name T238
Test name
Test status
Simulation time 974459697 ps
CPU time 4.32 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:14 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179030341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.179030341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.344689903
Short name T274
Test name
Test status
Simulation time 95164271 ps
CPU time 0.95 seconds
Started Aug 25 04:09:09 AM UTC 24
Finished Aug 25 04:09:25 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344689903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.344689903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.4224934020
Short name T228
Test name
Test status
Simulation time 241147787 ps
CPU time 2.14 seconds
Started Aug 25 04:09:08 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224934020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.4224934020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.3679625240
Short name T355
Test name
Test status
Simulation time 6804753027 ps
CPU time 22.3 seconds
Started Aug 25 04:09:10 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 209308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679625240 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3679625240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.367320820
Short name T290
Test name
Test status
Simulation time 325911519 ps
CPU time 2.78 seconds
Started Aug 25 04:09:09 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367320820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.367320820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.4068329942
Short name T233
Test name
Test status
Simulation time 203452901 ps
CPU time 1.47 seconds
Started Aug 25 04:09:09 AM UTC 24
Finished Aug 25 04:09:12 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068329942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.4068329942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.2469467970
Short name T244
Test name
Test status
Simulation time 61193883 ps
CPU time 1 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469467970 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2469467970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.320228890
Short name T48
Test name
Test status
Simulation time 1963926151 ps
CPU time 7.57 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320228890 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.320228890
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1429907881
Short name T247
Test name
Test status
Simulation time 302202361 ps
CPU time 1.63 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 237544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429907881 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1429907881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.1252934684
Short name T240
Test name
Test status
Simulation time 240772944 ps
CPU time 0.96 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:15 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252934684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.1252934684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3200794464
Short name T279
Test name
Test status
Simulation time 1205032324 ps
CPU time 4.93 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:25 AM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200794464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3200794464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1447825560
Short name T328
Test name
Test status
Simulation time 99241923 ps
CPU time 1.3 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447825560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1447825560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3340217449
Short name T333
Test name
Test status
Simulation time 249023688 ps
CPU time 1.61 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340217449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3340217449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.2399228152
Short name T255
Test name
Test status
Simulation time 326078724 ps
CPU time 2.28 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 209096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399228152 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.2399228152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.883214139
Short name T271
Test name
Test status
Simulation time 262371781 ps
CPU time 1.75 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883214139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.883214139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.877746603
Short name T268
Test name
Test status
Simulation time 108650713 ps
CPU time 1.26 seconds
Started Aug 25 04:09:12 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877746603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.877746603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.851169150
Short name T302
Test name
Test status
Simulation time 70563028 ps
CPU time 0.83 seconds
Started Aug 25 04:09:15 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851169150 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.851169150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.3958975556
Short name T35
Test name
Test status
Simulation time 1273459099 ps
CPU time 6.51 seconds
Started Aug 25 04:09:14 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958975556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3958975556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1910978871
Short name T303
Test name
Test status
Simulation time 301612412 ps
CPU time 1.26 seconds
Started Aug 25 04:09:15 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910978871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1910978871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.2802624136
Short name T248
Test name
Test status
Simulation time 211105972 ps
CPU time 1.47 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802624136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2802624136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.2158956497
Short name T260
Test name
Test status
Simulation time 1536533632 ps
CPU time 5.94 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158956497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.2158956497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.336086397
Short name T245
Test name
Test status
Simulation time 105108661 ps
CPU time 1.06 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336086397 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.336086397
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.3779401784
Short name T254
Test name
Test status
Simulation time 205612588 ps
CPU time 2.03 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:17 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779401784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.3779401784
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.962112591
Short name T364
Test name
Test status
Simulation time 4980411513 ps
CPU time 18.53 seconds
Started Aug 25 04:09:15 AM UTC 24
Finished Aug 25 04:09:38 AM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962112591 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.962112591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.294042388
Short name T250
Test name
Test status
Simulation time 151903704 ps
CPU time 1.73 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294042388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.294042388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.773226525
Short name T251
Test name
Test status
Simulation time 168776399 ps
CPU time 1.8 seconds
Started Aug 25 04:09:13 AM UTC 24
Finished Aug 25 04:09:16 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773226525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.773226525
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.1346042818
Short name T262
Test name
Test status
Simulation time 70456980 ps
CPU time 0.95 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346042818 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.1346042818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.2200578260
Short name T296
Test name
Test status
Simulation time 1960088637 ps
CPU time 8.29 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:29 AM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200578260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.2200578260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4292723179
Short name T267
Test name
Test status
Simulation time 302277219 ps
CPU time 1.5 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 237568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292723179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4292723179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.1475055918
Short name T323
Test name
Test status
Simulation time 202999678 ps
CPU time 1.04 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475055918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1475055918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1374563975
Short name T297
Test name
Test status
Simulation time 1192750937 ps
CPU time 5.07 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:29 AM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374563975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1374563975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1881826480
Short name T278
Test name
Test status
Simulation time 182487997 ps
CPU time 1.6 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:25 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881826480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1881826480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.359005612
Short name T339
Test name
Test status
Simulation time 202117800 ps
CPU time 1.87 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359005612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.359005612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.2657148387
Short name T282
Test name
Test status
Simulation time 1243126438 ps
CPU time 5.68 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657148387 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2657148387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.2785692595
Short name T341
Test name
Test status
Simulation time 303329039 ps
CPU time 2.13 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 217920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785692595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2785692595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1391742658
Short name T275
Test name
Test status
Simulation time 92032182 ps
CPU time 1.33 seconds
Started Aug 25 04:09:16 AM UTC 24
Finished Aug 25 04:09:25 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391742658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1391742658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.3276947048
Short name T263
Test name
Test status
Simulation time 85164692 ps
CPU time 0.84 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276947048 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.3276947048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2417512012
Short name T293
Test name
Test status
Simulation time 1957051918 ps
CPU time 7.89 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417512012 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2417512012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1134391440
Short name T334
Test name
Test status
Simulation time 300287275 ps
CPU time 1.78 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134391440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1134391440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.1095553996
Short name T265
Test name
Test status
Simulation time 114982133 ps
CPU time 1.27 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095553996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1095553996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.2445001871
Short name T285
Test name
Test status
Simulation time 1635218201 ps
CPU time 5.88 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445001871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.2445001871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2575065982
Short name T270
Test name
Test status
Simulation time 185620741 ps
CPU time 1.35 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575065982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2575065982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3377379244
Short name T266
Test name
Test status
Simulation time 201151503 ps
CPU time 1.47 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:22 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377379244 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3377379244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.1775596674
Short name T428
Test name
Test status
Simulation time 5685294069 ps
CPU time 21.99 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:53 AM UTC 24
Peak memory 209352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775596674 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1775596674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.2956868601
Short name T272
Test name
Test status
Simulation time 143650570 ps
CPU time 2.38 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:23 AM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956868601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.2956868601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.624437639
Short name T264
Test name
Test status
Simulation time 75660655 ps
CPU time 1.06 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:21 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624437639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.624437639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2326325017
Short name T301
Test name
Test status
Simulation time 64453854 ps
CPU time 0.69 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326325017 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2326325017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.921318600
Short name T308
Test name
Test status
Simulation time 1275045656 ps
CPU time 5.56 seconds
Started Aug 25 04:09:21 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 241940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921318600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.921318600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1973791707
Short name T306
Test name
Test status
Simulation time 301655227 ps
CPU time 1.58 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973791707 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1973791707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1112918523
Short name T326
Test name
Test status
Simulation time 127655408 ps
CPU time 1.25 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 206876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112918523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1112918523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.1782402061
Short name T299
Test name
Test status
Simulation time 1063503249 ps
CPU time 5.11 seconds
Started Aug 25 04:09:19 AM UTC 24
Finished Aug 25 04:09:29 AM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782402061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1782402061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.1595064358
Short name T283
Test name
Test status
Simulation time 146944685 ps
CPU time 1.37 seconds
Started Aug 25 04:09:20 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595064358 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.1595064358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.3727436361
Short name T332
Test name
Test status
Simulation time 129165463 ps
CPU time 1.48 seconds
Started Aug 25 04:09:18 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727436361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.3727436361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.4125747271
Short name T381
Test name
Test status
Simulation time 4174776852 ps
CPU time 14.76 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:44 AM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125747271 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.4125747271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.1808587772
Short name T277
Test name
Test status
Simulation time 279119067 ps
CPU time 2 seconds
Started Aug 25 04:09:19 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808587772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1808587772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.2885456922
Short name T325
Test name
Test status
Simulation time 109532865 ps
CPU time 1.03 seconds
Started Aug 25 04:09:19 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885456922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.2885456922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.116412786
Short name T276
Test name
Test status
Simulation time 62152361 ps
CPU time 0.91 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:25 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116412786 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.116412786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.96420694
Short name T309
Test name
Test status
Simulation time 1274083243 ps
CPU time 5.73 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 242308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96420694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.96420694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2756037115
Short name T289
Test name
Test status
Simulation time 301581608 ps
CPU time 1.35 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 237272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756037115 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2756037115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.246561987
Short name T311
Test name
Test status
Simulation time 97778767 ps
CPU time 0.99 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246561987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.246561987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.1318944245
Short name T347
Test name
Test status
Simulation time 1120871047 ps
CPU time 5.41 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:35 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318944245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1318944245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3410154555
Short name T320
Test name
Test status
Simulation time 98868732 ps
CPU time 1.45 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410154555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3410154555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3462888272
Short name T304
Test name
Test status
Simulation time 118737868 ps
CPU time 1.22 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462888272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3462888272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.1739049233
Short name T401
Test name
Test status
Simulation time 6130083377 ps
CPU time 23.26 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:48 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739049233 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1739049233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.1694341651
Short name T317
Test name
Test status
Simulation time 361903371 ps
CPU time 2.31 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694341651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1694341651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.528813974
Short name T318
Test name
Test status
Simulation time 124873817 ps
CPU time 1.37 seconds
Started Aug 25 04:09:22 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528813974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.528813974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.3646995755
Short name T330
Test name
Test status
Simulation time 70856724 ps
CPU time 1.14 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646995755 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3646995755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.3528059169
Short name T487
Test name
Test status
Simulation time 1273702455 ps
CPU time 7.08 seconds
Started Aug 25 04:09:24 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 241996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528059169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.3528059169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.4124433627
Short name T321
Test name
Test status
Simulation time 301777726 ps
CPU time 1.88 seconds
Started Aug 25 04:09:25 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124433627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.4124433627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.375787211
Short name T280
Test name
Test status
Simulation time 222708340 ps
CPU time 1.36 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375787211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.375787211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.4131939702
Short name T300
Test name
Test status
Simulation time 964291346 ps
CPU time 4.82 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:29 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131939702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4131939702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2714058337
Short name T515
Test name
Test status
Simulation time 169121050 ps
CPU time 1.76 seconds
Started Aug 25 04:09:24 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714058337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2714058337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.1958804550
Short name T291
Test name
Test status
Simulation time 203572197 ps
CPU time 1.58 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:27 AM UTC 24
Peak memory 207852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958804550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.1958804550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.1104346863
Short name T358
Test name
Test status
Simulation time 1781670323 ps
CPU time 7.09 seconds
Started Aug 25 04:09:25 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104346863 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.1104346863
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1562773809
Short name T284
Test name
Test status
Simulation time 151741080 ps
CPU time 1.75 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562773809 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1562773809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3422395005
Short name T281
Test name
Test status
Simulation time 119579184 ps
CPU time 1.26 seconds
Started Aug 25 04:09:23 AM UTC 24
Finished Aug 25 04:09:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422395005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3422395005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1214001889
Short name T118
Test name
Test status
Simulation time 53828677 ps
CPU time 1.13 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:04 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214001889 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1214001889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.748846636
Short name T26
Test name
Test status
Simulation time 2260798204 ps
CPU time 12.89 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:15 AM UTC 24
Peak memory 241524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748846636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.748846636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3610924228
Short name T103
Test name
Test status
Simulation time 301993871 ps
CPU time 2.12 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:04 AM UTC 24
Peak memory 237828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610924228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3610924228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.864043181
Short name T15
Test name
Test status
Simulation time 152026566 ps
CPU time 1.41 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864043181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.864043181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.4139257611
Short name T121
Test name
Test status
Simulation time 761818925 ps
CPU time 5.86 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:08 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139257611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.4139257611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3255868346
Short name T83
Test name
Test status
Simulation time 17634203611 ps
CPU time 43.1 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:47 AM UTC 24
Peak memory 241800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255868346 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3255868346
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3714224633
Short name T24
Test name
Test status
Simulation time 106082889 ps
CPU time 1.63 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714224633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3714224633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1120594252
Short name T104
Test name
Test status
Simulation time 123990128 ps
CPU time 1.89 seconds
Started Aug 25 04:08:00 AM UTC 24
Finished Aug 25 04:08:03 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120594252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.1120594252
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.4085232794
Short name T143
Test name
Test status
Simulation time 5945626954 ps
CPU time 29.8 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:33 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085232794 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.4085232794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.293180975
Short name T111
Test name
Test status
Simulation time 252291106 ps
CPU time 2.79 seconds
Started Aug 25 04:08:01 AM UTC 24
Finished Aug 25 04:08:05 AM UTC 24
Peak memory 208720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293180975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.293180975
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.3712394799
Short name T315
Test name
Test status
Simulation time 90819289 ps
CPU time 1.06 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712394799 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3712394799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.3151724733
Short name T363
Test name
Test status
Simulation time 1267866858 ps
CPU time 6.2 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:38 AM UTC 24
Peak memory 242040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151724733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3151724733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.697830649
Short name T343
Test name
Test status
Simulation time 301332371 ps
CPU time 1.65 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697830649 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.697830649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2310548063
Short name T329
Test name
Test status
Simulation time 112872513 ps
CPU time 1.01 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310548063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2310548063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.2483550087
Short name T354
Test name
Test status
Simulation time 1071121214 ps
CPU time 5.14 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483550087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.2483550087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.1713714578
Short name T344
Test name
Test status
Simulation time 173699919 ps
CPU time 1.83 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713714578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.1713714578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.3824275340
Short name T336
Test name
Test status
Simulation time 203360063 ps
CPU time 1.43 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824275340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3824275340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.1631784335
Short name T404
Test name
Test status
Simulation time 4210941842 ps
CPU time 17.4 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:49 AM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631784335 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.1631784335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.734089708
Short name T346
Test name
Test status
Simulation time 277288332 ps
CPU time 2.13 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734089708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.734089708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.228827437
Short name T337
Test name
Test status
Simulation time 160529789 ps
CPU time 1.46 seconds
Started Aug 25 04:09:27 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228827437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.228827437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.512050069
Short name T324
Test name
Test status
Simulation time 75497827 ps
CPU time 1.03 seconds
Started Aug 25 04:09:29 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512050069 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.512050069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.2194044856
Short name T351
Test name
Test status
Simulation time 1272666178 ps
CPU time 6.36 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 242056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194044856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.2194044856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1544291740
Short name T307
Test name
Test status
Simulation time 301277869 ps
CPU time 1.11 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544291740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1544291740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.3703219566
Short name T312
Test name
Test status
Simulation time 118034689 ps
CPU time 0.87 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703219566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.3703219566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.495844261
Short name T340
Test name
Test status
Simulation time 830071645 ps
CPU time 3.6 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495844261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.495844261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2519776084
Short name T305
Test name
Test status
Simulation time 111068901 ps
CPU time 1.12 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:30 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519776084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2519776084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.4000231121
Short name T316
Test name
Test status
Simulation time 116742152 ps
CPU time 1.2 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000231121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.4000231121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.3618870307
Short name T345
Test name
Test status
Simulation time 348030630 ps
CPU time 2.41 seconds
Started Aug 25 04:09:29 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 209148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618870307 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3618870307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.1182863256
Short name T335
Test name
Test status
Simulation time 515453750 ps
CPU time 3.2 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182863256 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.1182863256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.3301035540
Short name T313
Test name
Test status
Simulation time 91814332 ps
CPU time 1.11 seconds
Started Aug 25 04:09:28 AM UTC 24
Finished Aug 25 04:09:31 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301035540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3301035540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.347141659
Short name T366
Test name
Test status
Simulation time 56854961 ps
CPU time 0.79 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347141659 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.347141659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.190496398
Short name T362
Test name
Test status
Simulation time 1268340634 ps
CPU time 5.5 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 242296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190496398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.190496398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.2775929031
Short name T368
Test name
Test status
Simulation time 301622611 ps
CPU time 1.21 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775929031 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.2775929031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1667335414
Short name T319
Test name
Test status
Simulation time 129567913 ps
CPU time 0.9 seconds
Started Aug 25 04:09:29 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667335414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1667335414
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.472756917
Short name T359
Test name
Test status
Simulation time 1528869032 ps
CPU time 6.05 seconds
Started Aug 25 04:09:30 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 208464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472756917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.472756917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.3757827462
Short name T342
Test name
Test status
Simulation time 102911112 ps
CPU time 1.15 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:33 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757827462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.3757827462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2895279918
Short name T331
Test name
Test status
Simulation time 125230500 ps
CPU time 1.45 seconds
Started Aug 25 04:09:29 AM UTC 24
Finished Aug 25 04:09:32 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895279918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2895279918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.1849474155
Short name T396
Test name
Test status
Simulation time 1853619270 ps
CPU time 7.12 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 218016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849474155 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.1849474155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.3191312170
Short name T327
Test name
Test status
Simulation time 336577277 ps
CPU time 2.04 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191312170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3191312170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.278815404
Short name T367
Test name
Test status
Simulation time 131823191 ps
CPU time 1.12 seconds
Started Aug 25 04:09:31 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278815404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.278815404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.3462846191
Short name T352
Test name
Test status
Simulation time 68864275 ps
CPU time 0.97 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462846191 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.3462846191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.4025239750
Short name T379
Test name
Test status
Simulation time 2441389168 ps
CPU time 8.39 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:43 AM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025239750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.4025239750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.2946386990
Short name T356
Test name
Test status
Simulation time 302273914 ps
CPU time 1.95 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946386990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.2946386990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.2799546005
Short name T348
Test name
Test status
Simulation time 185785276 ps
CPU time 1.04 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:35 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799546005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.2799546005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.1803204586
Short name T371
Test name
Test status
Simulation time 1562969384 ps
CPU time 6.45 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803204586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1803204586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3788434718
Short name T353
Test name
Test status
Simulation time 176989422 ps
CPU time 1.49 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788434718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3788434718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.1429324915
Short name T349
Test name
Test status
Simulation time 118108743 ps
CPU time 1.29 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429324915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1429324915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.2651295797
Short name T413
Test name
Test status
Simulation time 4073144477 ps
CPU time 15.67 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651295797 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2651295797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.1959882226
Short name T360
Test name
Test status
Simulation time 122530070 ps
CPU time 2.31 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959882226 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1959882226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.722503085
Short name T350
Test name
Test status
Simulation time 130079667 ps
CPU time 1.15 seconds
Started Aug 25 04:09:32 AM UTC 24
Finished Aug 25 04:09:36 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722503085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.722503085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.1622460732
Short name T445
Test name
Test status
Simulation time 79407196 ps
CPU time 0.88 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622460732 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.1622460732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.2856212330
Short name T494
Test name
Test status
Simulation time 1943539876 ps
CPU time 7.45 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 242336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856212330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.2856212330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.563545432
Short name T450
Test name
Test status
Simulation time 301908993 ps
CPU time 1.36 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:09:57 AM UTC 24
Peak memory 237632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563545432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.563545432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.332936822
Short name T391
Test name
Test status
Simulation time 261815648 ps
CPU time 1.05 seconds
Started Aug 25 04:09:33 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332936822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.332936822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.2512391637
Short name T423
Test name
Test status
Simulation time 1925212993 ps
CPU time 6.68 seconds
Started Aug 25 04:09:33 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512391637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.2512391637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2139301761
Short name T449
Test name
Test status
Simulation time 99741912 ps
CPU time 1.27 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139301761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2139301761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.1930023933
Short name T357
Test name
Test status
Simulation time 247122573 ps
CPU time 1.77 seconds
Started Aug 25 04:09:33 AM UTC 24
Finished Aug 25 04:09:37 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930023933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1930023933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.3882973758
Short name T531
Test name
Test status
Simulation time 10974074605 ps
CPU time 37.15 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:33 AM UTC 24
Peak memory 220344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882973758 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3882973758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.401563919
Short name T399
Test name
Test status
Simulation time 144290614 ps
CPU time 1.62 seconds
Started Aug 25 04:09:33 AM UTC 24
Finished Aug 25 04:09:47 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401563919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.401563919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.1798724492
Short name T394
Test name
Test status
Simulation time 140072008 ps
CPU time 1.11 seconds
Started Aug 25 04:09:33 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798724492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1798724492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.2559264852
Short name T503
Test name
Test status
Simulation time 64621388 ps
CPU time 1.1 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559264852 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2559264852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.2072462220
Short name T458
Test name
Test status
Simulation time 1971912323 ps
CPU time 9.71 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:12 AM UTC 24
Peak memory 242368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072462220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2072462220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.231830638
Short name T506
Test name
Test status
Simulation time 301580436 ps
CPU time 1.39 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231830638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.231830638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.2827108477
Short name T500
Test name
Test status
Simulation time 83118516 ps
CPU time 0.74 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827108477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2827108477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2583218349
Short name T474
Test name
Test status
Simulation time 1515173731 ps
CPU time 6.1 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583218349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2583218349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1871132072
Short name T505
Test name
Test status
Simulation time 106073477 ps
CPU time 1.42 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871132072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1871132072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.3082749293
Short name T511
Test name
Test status
Simulation time 196193778 ps
CPU time 1.88 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082749293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.3082749293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.3622296262
Short name T535
Test name
Test status
Simulation time 17008880210 ps
CPU time 49.69 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:53 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622296262 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.3622296262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.3223871834
Short name T441
Test name
Test status
Simulation time 117248638 ps
CPU time 1.64 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:09:57 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223871834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.3223871834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.1226085482
Short name T502
Test name
Test status
Simulation time 135996653 ps
CPU time 1.17 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226085482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1226085482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.91940740
Short name T384
Test name
Test status
Simulation time 76994185 ps
CPU time 0.93 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91940740 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.91940740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.2972336684
Short name T516
Test name
Test status
Simulation time 1282217257 ps
CPU time 6.24 seconds
Started Aug 25 04:09:35 AM UTC 24
Finished Aug 25 04:10:05 AM UTC 24
Peak memory 242344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972336684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.2972336684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.1210383210
Short name T372
Test name
Test status
Simulation time 302247896 ps
CPU time 1.35 seconds
Started Aug 25 04:09:36 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 237140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210383210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.1210383210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.3613803935
Short name T508
Test name
Test status
Simulation time 136068730 ps
CPU time 1.25 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613803935 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3613803935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.3282531725
Short name T510
Test name
Test status
Simulation time 1311466393 ps
CPU time 5.49 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282531725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3282531725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.2820702070
Short name T454
Test name
Test status
Simulation time 101039823 ps
CPU time 1.04 seconds
Started Aug 25 04:09:35 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820702070 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.2820702070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.273197255
Short name T512
Test name
Test status
Simulation time 222315790 ps
CPU time 1.63 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273197255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.273197255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.181212056
Short name T378
Test name
Test status
Simulation time 527577571 ps
CPU time 2.95 seconds
Started Aug 25 04:09:36 AM UTC 24
Finished Aug 25 04:09:43 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181212056 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.181212056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.2099962409
Short name T468
Test name
Test status
Simulation time 302367537 ps
CPU time 1.85 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099962409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2099962409
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.1193370310
Short name T464
Test name
Test status
Simulation time 172541951 ps
CPU time 1.55 seconds
Started Aug 25 04:09:34 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193370310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1193370310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.1384944566
Short name T314
Test name
Test status
Simulation time 82497238 ps
CPU time 0.87 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384944566 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.1384944566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.1741079900
Short name T387
Test name
Test status
Simulation time 1274132572 ps
CPU time 5 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 242224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741079900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1741079900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1493692026
Short name T374
Test name
Test status
Simulation time 302328564 ps
CPU time 1.14 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493692026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1493692026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.2976466878
Short name T382
Test name
Test status
Simulation time 80983234 ps
CPU time 0.74 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976466878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.2976466878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.857609885
Short name T402
Test name
Test status
Simulation time 787450390 ps
CPU time 3.62 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:48 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857609885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.857609885
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.2370227428
Short name T373
Test name
Test status
Simulation time 150905325 ps
CPU time 1.02 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370227428 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.2370227428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.4106859579
Short name T386
Test name
Test status
Simulation time 110190032 ps
CPU time 1.2 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106859579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.4106859579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.3462970772
Short name T518
Test name
Test status
Simulation time 7677809388 ps
CPU time 25.33 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462970772 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.3462970772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.1402789575
Short name T392
Test name
Test status
Simulation time 259447127 ps
CPU time 1.64 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402789575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1402789575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.4244196845
Short name T383
Test name
Test status
Simulation time 67779575 ps
CPU time 0.71 seconds
Started Aug 25 04:09:37 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244196845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.4244196845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.2530629030
Short name T393
Test name
Test status
Simulation time 62314341 ps
CPU time 1.09 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530629030 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.2530629030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.596187227
Short name T400
Test name
Test status
Simulation time 1967208878 ps
CPU time 6.69 seconds
Started Aug 25 04:09:40 AM UTC 24
Finished Aug 25 04:09:47 AM UTC 24
Peak memory 242312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596187227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.596187227
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.2787140170
Short name T377
Test name
Test status
Simulation time 301657528 ps
CPU time 1.2 seconds
Started Aug 25 04:09:40 AM UTC 24
Finished Aug 25 04:09:42 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787140170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.2787140170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.801714138
Short name T322
Test name
Test status
Simulation time 210398590 ps
CPU time 0.97 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 207700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801714138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.801714138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.2750687080
Short name T380
Test name
Test status
Simulation time 954955373 ps
CPU time 4 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:43 AM UTC 24
Peak memory 209172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750687080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2750687080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1406651622
Short name T369
Test name
Test status
Simulation time 100152599 ps
CPU time 0.89 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:40 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406651622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1406651622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.618450911
Short name T375
Test name
Test status
Simulation time 245236702 ps
CPU time 1.99 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618450911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.618450911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.3752895467
Short name T529
Test name
Test status
Simulation time 7771798527 ps
CPU time 31.16 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:10:16 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752895467 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3752895467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.1367439411
Short name T310
Test name
Test status
Simulation time 120980396 ps
CPU time 1.44 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367439411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.1367439411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.1795977472
Short name T370
Test name
Test status
Simulation time 90038473 ps
CPU time 1.09 seconds
Started Aug 25 04:09:38 AM UTC 24
Finished Aug 25 04:09:41 AM UTC 24
Peak memory 207692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795977472 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1795977472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.2475908251
Short name T477
Test name
Test status
Simulation time 76694182 ps
CPU time 1.1 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475908251 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.2475908251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.2937490823
Short name T520
Test name
Test status
Simulation time 1267036125 ps
CPU time 6.29 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:10:07 AM UTC 24
Peak memory 242388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937490823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2937490823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.3917945369
Short name T491
Test name
Test status
Simulation time 301917881 ps
CPU time 2.1 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 237776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917945369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.3917945369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.819545480
Short name T446
Test name
Test status
Simulation time 158614849 ps
CPU time 1.13 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819545480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.819545480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.3052158325
Short name T403
Test name
Test status
Simulation time 870788924 ps
CPU time 3.85 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:09:49 AM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052158325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3052158325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.363759635
Short name T480
Test name
Test status
Simulation time 105193894 ps
CPU time 1.54 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363759635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.363759635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.819837049
Short name T398
Test name
Test status
Simulation time 119900315 ps
CPU time 1.46 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819837049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.819837049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.2533283809
Short name T389
Test name
Test status
Simulation time 1581708215 ps
CPU time 5.83 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533283809 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.2533283809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.2058727515
Short name T479
Test name
Test status
Simulation time 120983791 ps
CPU time 1.55 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058727515 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2058727515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.2957743424
Short name T397
Test name
Test status
Simulation time 196949589 ps
CPU time 1.25 seconds
Started Aug 25 04:09:41 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957743424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2957743424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.1712550636
Short name T119
Test name
Test status
Simulation time 74040145 ps
CPU time 1.24 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:06 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712550636 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1712550636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.823911919
Short name T27
Test name
Test status
Simulation time 1941041603 ps
CPU time 11.57 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 241712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823911919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.823911919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1884553405
Short name T155
Test name
Test status
Simulation time 301120140 ps
CPU time 2.27 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 237672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884553405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1884553405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.3838937199
Short name T16
Test name
Test status
Simulation time 138107722 ps
CPU time 1.46 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:05 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838937199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3838937199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2980832419
Short name T123
Test name
Test status
Simulation time 838625902 ps
CPU time 6.36 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980832419 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2980832419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.2414729765
Short name T73
Test name
Test status
Simulation time 8310504162 ps
CPU time 23.18 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:28 AM UTC 24
Peak memory 242264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414729765 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2414729765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.339585065
Short name T120
Test name
Test status
Simulation time 98400416 ps
CPU time 1.47 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:06 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339585065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.339585065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2958427967
Short name T105
Test name
Test status
Simulation time 252611752 ps
CPU time 2.26 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:05 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958427967 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2958427967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.3213484196
Short name T84
Test name
Test status
Simulation time 4328610950 ps
CPU time 22.71 seconds
Started Aug 25 04:08:03 AM UTC 24
Finished Aug 25 04:08:27 AM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213484196 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3213484196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.4190424483
Short name T108
Test name
Test status
Simulation time 276696689 ps
CPU time 2.83 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:06 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190424483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4190424483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.258824983
Short name T107
Test name
Test status
Simulation time 156405359 ps
CPU time 1.79 seconds
Started Aug 25 04:08:02 AM UTC 24
Finished Aug 25 04:08:05 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258824983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.258824983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.2709821630
Short name T453
Test name
Test status
Simulation time 54855579 ps
CPU time 0.65 seconds
Started Aug 25 04:09:44 AM UTC 24
Finished Aug 25 04:09:59 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709821630 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2709821630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.3888669173
Short name T427
Test name
Test status
Simulation time 2470767523 ps
CPU time 7.57 seconds
Started Aug 25 04:09:43 AM UTC 24
Finished Aug 25 04:09:52 AM UTC 24
Peak memory 241708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888669173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3888669173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2519863999
Short name T461
Test name
Test status
Simulation time 301868065 ps
CPU time 1.22 seconds
Started Aug 25 04:09:44 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519863999 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2519863999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.39860352
Short name T385
Test name
Test status
Simulation time 99985279 ps
CPU time 0.78 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39860352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.39860352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2255930458
Short name T405
Test name
Test status
Simulation time 1488049851 ps
CPU time 5.18 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255930458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2255930458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1357206097
Short name T390
Test name
Test status
Simulation time 188831386 ps
CPU time 1.04 seconds
Started Aug 25 04:09:43 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357206097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1357206097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.700326398
Short name T425
Test name
Test status
Simulation time 114916375 ps
CPU time 1.17 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:09:52 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700326398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.700326398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.1060978808
Short name T533
Test name
Test status
Simulation time 11860535339 ps
CPU time 34.22 seconds
Started Aug 25 04:09:44 AM UTC 24
Finished Aug 25 04:10:37 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060978808 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1060978808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.3349009908
Short name T395
Test name
Test status
Simulation time 121657877 ps
CPU time 1.49 seconds
Started Aug 25 04:09:43 AM UTC 24
Finished Aug 25 04:09:46 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349009908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3349009908
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.4005845664
Short name T388
Test name
Test status
Simulation time 174189174 ps
CPU time 1.07 seconds
Started Aug 25 04:09:42 AM UTC 24
Finished Aug 25 04:09:45 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005845664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.4005845664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.4123560700
Short name T421
Test name
Test status
Simulation time 74661960 ps
CPU time 0.96 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123560700 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.4123560700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2025340383
Short name T452
Test name
Test status
Simulation time 1945966783 ps
CPU time 7.18 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:57 AM UTC 24
Peak memory 242436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025340383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2025340383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4022501840
Short name T422
Test name
Test status
Simulation time 301908534 ps
CPU time 1.26 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022501840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4022501840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.1957168579
Short name T416
Test name
Test status
Simulation time 87025228 ps
CPU time 0.84 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957168579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1957168579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2644186100
Short name T432
Test name
Test status
Simulation time 1352461927 ps
CPU time 4.98 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644186100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2644186100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3955678679
Short name T419
Test name
Test status
Simulation time 99317704 ps
CPU time 0.97 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955678679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3955678679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.1385776317
Short name T420
Test name
Test status
Simulation time 121570872 ps
CPU time 1.25 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385776317 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1385776317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.2442340808
Short name T424
Test name
Test status
Simulation time 217658787 ps
CPU time 1.37 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:52 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442340808 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.2442340808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1741247673
Short name T426
Test name
Test status
Simulation time 155733182 ps
CPU time 1.76 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:52 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741247673 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1741247673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.1172718146
Short name T418
Test name
Test status
Simulation time 69313178 ps
CPU time 0.88 seconds
Started Aug 25 04:09:46 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172718146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1172718146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.4277445578
Short name T410
Test name
Test status
Simulation time 77155259 ps
CPU time 0.72 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277445578 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.4277445578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.767092091
Short name T451
Test name
Test status
Simulation time 2433208605 ps
CPU time 7.83 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:57 AM UTC 24
Peak memory 242304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767092091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.767092091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3807921332
Short name T412
Test name
Test status
Simulation time 303025512 ps
CPU time 1.09 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807921332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3807921332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.2505181636
Short name T406
Test name
Test status
Simulation time 94446797 ps
CPU time 0.73 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505181636 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2505181636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.3131060000
Short name T485
Test name
Test status
Simulation time 2002295064 ps
CPU time 6.92 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131060000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3131060000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2297241353
Short name T408
Test name
Test status
Simulation time 140326768 ps
CPU time 0.96 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297241353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2297241353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.3710925602
Short name T415
Test name
Test status
Simulation time 227399218 ps
CPU time 1.51 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710925602 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3710925602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.4164363703
Short name T532
Test name
Test status
Simulation time 13115842385 ps
CPU time 42.78 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:10:33 AM UTC 24
Peak memory 209108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164363703 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.4164363703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.3279869199
Short name T417
Test name
Test status
Simulation time 110571505 ps
CPU time 1.43 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279869199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.3279869199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.3079360813
Short name T407
Test name
Test status
Simulation time 70194544 ps
CPU time 0.73 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079360813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3079360813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.204932978
Short name T447
Test name
Test status
Simulation time 87580303 ps
CPU time 1.13 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204932978 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.204932978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.1239704545
Short name T460
Test name
Test status
Simulation time 1270532413 ps
CPU time 5.08 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 240372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239704545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1239704545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1589230421
Short name T440
Test name
Test status
Simulation time 302369160 ps
CPU time 1.14 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589230421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1589230421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.313447094
Short name T411
Test name
Test status
Simulation time 100529234 ps
CPU time 0.71 seconds
Started Aug 25 04:09:48 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313447094 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.313447094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.3198207667
Short name T429
Test name
Test status
Simulation time 1301789541 ps
CPU time 4.86 seconds
Started Aug 25 04:09:48 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198207667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.3198207667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1828413289
Short name T430
Test name
Test status
Simulation time 145248414 ps
CPU time 1 seconds
Started Aug 25 04:09:50 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828413289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1828413289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.4194529492
Short name T414
Test name
Test status
Simulation time 115411585 ps
CPU time 1.07 seconds
Started Aug 25 04:09:47 AM UTC 24
Finished Aug 25 04:09:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194529492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.4194529492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.4269008250
Short name T457
Test name
Test status
Simulation time 3290474167 ps
CPU time 14.61 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 208860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269008250 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.4269008250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.1586536142
Short name T498
Test name
Test status
Simulation time 313609929 ps
CPU time 2.21 seconds
Started Aug 25 04:09:50 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586536142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.1586536142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.2248091513
Short name T409
Test name
Test status
Simulation time 64614756 ps
CPU time 0.71 seconds
Started Aug 25 04:09:48 AM UTC 24
Finished Aug 25 04:09:50 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248091513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2248091513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.108265941
Short name T434
Test name
Test status
Simulation time 77240040 ps
CPU time 0.89 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108265941 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.108265941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.8736659
Short name T523
Test name
Test status
Simulation time 1268913147 ps
CPU time 7.64 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8736659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.8736659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4145691129
Short name T442
Test name
Test status
Simulation time 301665266 ps
CPU time 1.52 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145691129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4145691129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.1608699324
Short name T443
Test name
Test status
Simulation time 151664863 ps
CPU time 0.84 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608699324 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.1608699324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.2566152348
Short name T475
Test name
Test status
Simulation time 1725327285 ps
CPU time 6.43 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 209384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566152348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.2566152348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.2379683489
Short name T472
Test name
Test status
Simulation time 108483089 ps
CPU time 1 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379683489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.2379683489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.3405379174
Short name T444
Test name
Test status
Simulation time 115941804 ps
CPU time 1.02 seconds
Started Aug 25 04:09:51 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405379174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3405379174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.1933063859
Short name T528
Test name
Test status
Simulation time 3202714061 ps
CPU time 14.01 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:15 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933063859 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.1933063859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.14173021
Short name T493
Test name
Test status
Simulation time 140784981 ps
CPU time 2.4 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 208824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14173021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.14173021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.1953008792
Short name T481
Test name
Test status
Simulation time 156954924 ps
CPU time 1.73 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953008792 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.1953008792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.253149146
Short name T435
Test name
Test status
Simulation time 66989988 ps
CPU time 0.63 seconds
Started Aug 25 04:09:53 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253149146 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.253149146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2769028383
Short name T456
Test name
Test status
Simulation time 1273707770 ps
CPU time 5.26 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 241964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769028383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2769028383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.2041468111
Short name T439
Test name
Test status
Simulation time 305247033 ps
CPU time 1.06 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041468111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.2041468111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3809364171
Short name T438
Test name
Test status
Simulation time 128416749 ps
CPU time 1.14 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809364171 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3809364171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.1254817199
Short name T448
Test name
Test status
Simulation time 1526330530 ps
CPU time 5.09 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:59 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254817199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1254817199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.3788134513
Short name T436
Test name
Test status
Simulation time 153949744 ps
CPU time 1.03 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788134513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.3788134513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.450175130
Short name T478
Test name
Test status
Simulation time 106915998 ps
CPU time 1.6 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450175130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.450175130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.531716087
Short name T530
Test name
Test status
Simulation time 5798702444 ps
CPU time 22.67 seconds
Started Aug 25 04:09:53 AM UTC 24
Finished Aug 25 04:10:18 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531716087 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.531716087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.1840284370
Short name T437
Test name
Test status
Simulation time 294537010 ps
CPU time 1.91 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840284370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1840284370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.1287544804
Short name T433
Test name
Test status
Simulation time 101442662 ps
CPU time 0.82 seconds
Started Aug 25 04:09:52 AM UTC 24
Finished Aug 25 04:09:55 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287544804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.1287544804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.392994074
Short name T482
Test name
Test status
Simulation time 71450763 ps
CPU time 0.84 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392994074 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.392994074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.473980076
Short name T525
Test name
Test status
Simulation time 2448376945 ps
CPU time 9.24 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:09 AM UTC 24
Peak memory 242448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473980076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.473980076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.3499940898
Short name T473
Test name
Test status
Simulation time 303164699 ps
CPU time 1.3 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499940898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.3499940898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.1253379574
Short name T466
Test name
Test status
Simulation time 85279228 ps
CPU time 0.73 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253379574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.1253379574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.3440925585
Short name T517
Test name
Test status
Simulation time 1554709724 ps
CPU time 5.65 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:05 AM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440925585 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.3440925585
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1741310460
Short name T470
Test name
Test status
Simulation time 112988870 ps
CPU time 1.06 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741310460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1741310460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.394764752
Short name T431
Test name
Test status
Simulation time 256944248 ps
CPU time 1.63 seconds
Started Aug 25 04:09:53 AM UTC 24
Finished Aug 25 04:09:56 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394764752 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.394764752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1475768412
Short name T486
Test name
Test status
Simulation time 1902219228 ps
CPU time 8.37 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 218044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475768412 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1475768412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.3620012133
Short name T484
Test name
Test status
Simulation time 148663998 ps
CPU time 2.43 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620012133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3620012133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.4009179829
Short name T471
Test name
Test status
Simulation time 215246008 ps
CPU time 1.29 seconds
Started Aug 25 04:09:56 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009179829 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.4009179829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.3001219390
Short name T459
Test name
Test status
Simulation time 66789587 ps
CPU time 0.72 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001219390 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.3001219390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.2608619531
Short name T527
Test name
Test status
Simulation time 2455249740 ps
CPU time 8.98 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 241804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608619531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2608619531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.2273697255
Short name T488
Test name
Test status
Simulation time 302907151 ps
CPU time 1.11 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 237276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273697255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.2273697255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.1739772254
Short name T483
Test name
Test status
Simulation time 83438227 ps
CPU time 1.08 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739772254 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.1739772254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.1777459921
Short name T519
Test name
Test status
Simulation time 1015533820 ps
CPU time 4.98 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:06 AM UTC 24
Peak memory 208756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777459921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1777459921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.3034682272
Short name T463
Test name
Test status
Simulation time 114206984 ps
CPU time 1 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034682272 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.3034682272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.3585389181
Short name T489
Test name
Test status
Simulation time 251364722 ps
CPU time 1.4 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585389181 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3585389181
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.914409229
Short name T521
Test name
Test status
Simulation time 1454744023 ps
CPU time 8.46 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 217700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914409229 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.914409229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.3538552282
Short name T501
Test name
Test status
Simulation time 136455768 ps
CPU time 2.02 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538552282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3538552282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.2648361620
Short name T490
Test name
Test status
Simulation time 85904013 ps
CPU time 1.2 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648361620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.2648361620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.111101519
Short name T495
Test name
Test status
Simulation time 80231963 ps
CPU time 0.98 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111101519 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.111101519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3869934497
Short name T522
Test name
Test status
Simulation time 1273156027 ps
CPU time 6.21 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 241312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869934497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3869934497
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.789897756
Short name T499
Test name
Test status
Simulation time 300906217 ps
CPU time 1.39 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 237568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789897756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.789897756
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.3719095268
Short name T462
Test name
Test status
Simulation time 92869320 ps
CPU time 0.65 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719095268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.3719095268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.3984172329
Short name T497
Test name
Test status
Simulation time 681493381 ps
CPU time 3.43 seconds
Started Aug 25 04:09:58 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984172329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3984172329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1552603341
Short name T469
Test name
Test status
Simulation time 159080157 ps
CPU time 1.19 seconds
Started Aug 25 04:09:58 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552603341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1552603341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.3800115734
Short name T467
Test name
Test status
Simulation time 198536795 ps
CPU time 1.31 seconds
Started Aug 25 04:09:57 AM UTC 24
Finished Aug 25 04:10:01 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800115734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.3800115734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.72607642
Short name T526
Test name
Test status
Simulation time 1742828276 ps
CPU time 7.85 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:10 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72607642 -assert nopostproc +UVM_TESTNAME=rs
tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.72607642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.1357533617
Short name T476
Test name
Test status
Simulation time 369698095 ps
CPU time 2.15 seconds
Started Aug 25 04:09:58 AM UTC 24
Finished Aug 25 04:10:02 AM UTC 24
Peak memory 217856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357533617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1357533617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.133169679
Short name T465
Test name
Test status
Simulation time 93441274 ps
CPU time 0.89 seconds
Started Aug 25 04:09:58 AM UTC 24
Finished Aug 25 04:10:00 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133169679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.133169679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.4022270331
Short name T509
Test name
Test status
Simulation time 55859716 ps
CPU time 0.97 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022270331 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.4022270331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.4097739675
Short name T455
Test name
Test status
Simulation time 2253933636 ps
CPU time 8.23 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:11 AM UTC 24
Peak memory 242464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097739675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.4097739675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3577232713
Short name T514
Test name
Test status
Simulation time 300995491 ps
CPU time 1.37 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 237568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577232713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3577232713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.1470051996
Short name T496
Test name
Test status
Simulation time 165125093 ps
CPU time 1 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470051996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.1470051996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.1186687510
Short name T524
Test name
Test status
Simulation time 1517336803 ps
CPU time 6.35 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:08 AM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186687510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1186687510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.4092158942
Short name T513
Test name
Test status
Simulation time 136318182 ps
CPU time 1.32 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092158942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.4092158942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.2428060153
Short name T507
Test name
Test status
Simulation time 187819895 ps
CPU time 2.15 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428060153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2428060153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2696313985
Short name T534
Test name
Test status
Simulation time 13258646531 ps
CPU time 39.49 seconds
Started Aug 25 04:10:02 AM UTC 24
Finished Aug 25 04:10:43 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696313985 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2696313985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.3936203348
Short name T504
Test name
Test status
Simulation time 129241305 ps
CPU time 1.88 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:04 AM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936203348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.3936203348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.1399698741
Short name T492
Test name
Test status
Simulation time 90902398 ps
CPU time 0.82 seconds
Started Aug 25 04:10:01 AM UTC 24
Finished Aug 25 04:10:03 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399698741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.1399698741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4029200158
Short name T156
Test name
Test status
Simulation time 67115940 ps
CPU time 1.17 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029200158 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4029200158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4043657871
Short name T37
Test name
Test status
Simulation time 1946262964 ps
CPU time 9.58 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043657871 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4043657871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3536529205
Short name T129
Test name
Test status
Simulation time 301481555 ps
CPU time 2.19 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:08 AM UTC 24
Peak memory 237828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536529205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3536529205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2375706276
Short name T17
Test name
Test status
Simulation time 96065179 ps
CPU time 1.18 seconds
Started Aug 25 04:08:04 AM UTC 24
Finished Aug 25 04:08:06 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375706276 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2375706276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2887236696
Short name T122
Test name
Test status
Simulation time 1155788335 ps
CPU time 7.84 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:14 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887236696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2887236696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.4026366659
Short name T157
Test name
Test status
Simulation time 107992095 ps
CPU time 1.52 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026366659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.4026366659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.280298950
Short name T112
Test name
Test status
Simulation time 191165455 ps
CPU time 2.19 seconds
Started Aug 25 04:08:04 AM UTC 24
Finished Aug 25 04:08:07 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280298950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.280298950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.2623845062
Short name T173
Test name
Test status
Simulation time 9211487702 ps
CPU time 36.04 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:42 AM UTC 24
Peak memory 218144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623845062 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.2623845062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3524356247
Short name T113
Test name
Test status
Simulation time 301989220 ps
CPU time 3.14 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:09 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524356247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3524356247
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.4038988595
Short name T109
Test name
Test status
Simulation time 257202606 ps
CPU time 2.3 seconds
Started Aug 25 04:08:05 AM UTC 24
Finished Aug 25 04:08:08 AM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038988595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4038988595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1796808097
Short name T158
Test name
Test status
Simulation time 63858671 ps
CPU time 1.1 seconds
Started Aug 25 04:08:08 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796808097 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1796808097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.29666477
Short name T159
Test name
Test status
Simulation time 302331175 ps
CPU time 1.65 seconds
Started Aug 25 04:08:08 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29666477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.29666477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.3561057815
Short name T18
Test name
Test status
Simulation time 123955773 ps
CPU time 1.19 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:08 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561057815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3561057815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2320885960
Short name T124
Test name
Test status
Simulation time 1539957818 ps
CPU time 9.94 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320885960 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2320885960
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1820410400
Short name T130
Test name
Test status
Simulation time 158405996 ps
CPU time 1.82 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:09 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820410400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1820410400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2930596874
Short name T114
Test name
Test status
Simulation time 247362179 ps
CPU time 2.55 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930596874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2930596874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.704272045
Short name T133
Test name
Test status
Simulation time 8260506160 ps
CPU time 34.35 seconds
Started Aug 25 04:08:08 AM UTC 24
Finished Aug 25 04:08:43 AM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704272045 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.704272045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.134348087
Short name T63
Test name
Test status
Simulation time 349905101 ps
CPU time 3.53 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:11 AM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134348087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.134348087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3344801020
Short name T110
Test name
Test status
Simulation time 107154110 ps
CPU time 1.42 seconds
Started Aug 25 04:08:06 AM UTC 24
Finished Aug 25 04:08:09 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344801020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.3344801020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.806991443
Short name T53
Test name
Test status
Simulation time 74063697 ps
CPU time 1.19 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:12 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806991443 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.806991443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.2949219627
Short name T59
Test name
Test status
Simulation time 2444600027 ps
CPU time 12.59 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:23 AM UTC 24
Peak memory 242308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949219627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.2949219627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.7478222
Short name T52
Test name
Test status
Simulation time 302988319 ps
CPU time 2.02 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:12 AM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7478222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.7478222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.101319153
Short name T19
Test name
Test status
Simulation time 199208384 ps
CPU time 1.66 seconds
Started Aug 25 04:08:08 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101319153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.101319153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.252535132
Short name T125
Test name
Test status
Simulation time 1903496559 ps
CPU time 10.92 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:21 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252535132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.252535132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.2938135509
Short name T50
Test name
Test status
Simulation time 169413500 ps
CPU time 1.82 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:12 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938135509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.2938135509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.51424185
Short name T160
Test name
Test status
Simulation time 114111544 ps
CPU time 1.51 seconds
Started Aug 25 04:08:08 AM UTC 24
Finished Aug 25 04:08:10 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51424185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.51424185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.463201482
Short name T174
Test name
Test status
Simulation time 8511850933 ps
CPU time 31.8 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:42 AM UTC 24
Peak memory 220152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463201482 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.463201482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1519181022
Short name T51
Test name
Test status
Simulation time 113744504 ps
CPU time 2.15 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:12 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519181022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.1519181022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2849084093
Short name T49
Test name
Test status
Simulation time 180414000 ps
CPU time 1.87 seconds
Started Aug 25 04:08:09 AM UTC 24
Finished Aug 25 04:08:12 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849084093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2849084093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.2837636967
Short name T150
Test name
Test status
Simulation time 66105214 ps
CPU time 1.18 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:14 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837636967 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2837636967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.4119460410
Short name T29
Test name
Test status
Simulation time 1976747955 ps
CPU time 9.94 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:23 AM UTC 24
Peak memory 241928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119460410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4119460410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3164968424
Short name T152
Test name
Test status
Simulation time 309285251 ps
CPU time 1.97 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:15 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164968424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3164968424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.3317977606
Short name T20
Test name
Test status
Simulation time 226241899 ps
CPU time 1.66 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:13 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317977606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.3317977606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.758433206
Short name T151
Test name
Test status
Simulation time 107277459 ps
CPU time 1.5 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:14 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758433206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.758433206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.1577302437
Short name T149
Test name
Test status
Simulation time 248987670 ps
CPU time 2.32 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:14 AM UTC 24
Peak memory 209036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577302437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.1577302437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4259097411
Short name T42
Test name
Test status
Simulation time 474193379 ps
CPU time 3.66 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259097411 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4259097411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1088639936
Short name T38
Test name
Test status
Simulation time 557859273 ps
CPU time 4.56 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088639936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1088639936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.565679805
Short name T55
Test name
Test status
Simulation time 125605998 ps
CPU time 1.58 seconds
Started Aug 25 04:08:10 AM UTC 24
Finished Aug 25 04:08:13 AM UTC 24
Peak memory 208204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565679805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.565679805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.717768129
Short name T43
Test name
Test status
Simulation time 68650800 ps
CPU time 1.23 seconds
Started Aug 25 04:08:15 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717768129 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.717768129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.2166902263
Short name T31
Test name
Test status
Simulation time 1954625620 ps
CPU time 12.8 seconds
Started Aug 25 04:08:13 AM UTC 24
Finished Aug 25 04:08:27 AM UTC 24
Peak memory 251968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166902263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2166902263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.2954734188
Short name T41
Test name
Test status
Simulation time 301290109 ps
CPU time 2.06 seconds
Started Aug 25 04:08:13 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 237764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954734188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.2954734188
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1180185981
Short name T21
Test name
Test status
Simulation time 144911485 ps
CPU time 1.31 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:14 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180185981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1180185981
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.2634341598
Short name T126
Test name
Test status
Simulation time 1463966225 ps
CPU time 8.24 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:21 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634341598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.2634341598
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2654393915
Short name T40
Test name
Test status
Simulation time 160522273 ps
CPU time 1.8 seconds
Started Aug 25 04:08:13 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654393915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2654393915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2166836138
Short name T36
Test name
Test status
Simulation time 198122901 ps
CPU time 2.2 seconds
Started Aug 25 04:08:12 AM UTC 24
Finished Aug 25 04:08:15 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166836138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.2166836138
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1161882168
Short name T144
Test name
Test status
Simulation time 15650938621 ps
CPU time 50.75 seconds
Started Aug 25 04:08:14 AM UTC 24
Finished Aug 25 04:09:07 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161882168 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1161882168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.862905127
Short name T153
Test name
Test status
Simulation time 345690658 ps
CPU time 3.03 seconds
Started Aug 25 04:08:13 AM UTC 24
Finished Aug 25 04:08:17 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862905127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.862905127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1098542662
Short name T39
Test name
Test status
Simulation time 167483773 ps
CPU time 1.92 seconds
Started Aug 25 04:08:13 AM UTC 24
Finished Aug 25 04:08:16 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098542662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1098542662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest
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