Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::alert_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8719

1

T4

6

T8

28

T9

18

auto[1]

11749

1

T2

4

T4

1

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6251	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6861	1			T1	1		T2	2		T3	1
reset_info_cp[2]	3190	1			T2	1		T5	1		T8	10
reset_info_cp[4]	4246	1			T2	1		T5	1		T8	9
reset_info_cp[8]	113	1			T65	1		T44	2		T37	1
reset_info_cp[16]	114	1			T4	1		T38	1		T81	2
reset_info_cp[32]	108	1			T13	2		T79	1		T44	1
reset_info_cp[64]	98	1			T4	1		T26	1		T36	1
reset_info_cp[128]	107	1			T9	1		T13	1		T44	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3290	1			T8	9		T9	18		T77	9
reset_info_cp[1]	auto[1]	2951	1			T2	1		T5	1		T8	10
reset_info_cp[2]	auto[0]	1024	1			T8	3		T77	3		T36	3
reset_info_cp[2]	auto[1]	2166	1			T2	1		T5	1		T8	7
reset_info_cp[4]	auto[0]	1507	1			T8	5		T77	4		T36	6
reset_info_cp[4]	auto[1]	2739	1			T2	1		T5	1		T8	4
reset_info_cp[8]	auto[0]	40	1			T37	1		T83	1		T86	1
reset_info_cp[8]	auto[1]	73	1			T65	1		T44	2		T102	1
reset_info_cp[16]	auto[0]	49	1			T38	1		T81	1		T100	1
reset_info_cp[16]	auto[1]	65	1			T4	1		T81	1		T83	1
reset_info_cp[32]	auto[0]	43	1			T13	1		T79	1		T100	1
reset_info_cp[32]	auto[1]	65	1			T13	1		T44	1		T26	1
reset_info_cp[64]	auto[0]	35	1			T4	1		T36	1		T86	1
reset_info_cp[64]	auto[1]	63	1			T26	1		T102	1		T27	1
reset_info_cp[128]	auto[0]	51	1			T13	1		T81	1		T83	1
reset_info_cp[128]	auto[1]	56	1			T9	1		T44	1		T38	1