Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total tests in report: 620
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.60 82.60 95.35 95.35 85.43 85.43 80.27 80.27 94.33 94.33 88.96 88.96 51.23 51.23 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.4203199604
89.02 6.43 97.26 1.91 93.13 7.70 91.41 11.14 97.50 3.17 90.31 1.35 64.53 13.30 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.382138111
91.97 2.95 97.68 0.42 93.34 0.21 95.18 3.77 97.83 0.33 90.44 0.13 77.34 12.81 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2175107011
93.98 2.01 98.21 0.54 95.49 2.15 95.60 0.42 99.00 1.17 90.85 0.40 84.73 7.39 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.706140177
95.78 1.80 98.63 0.42 96.11 0.62 98.53 2.93 99.33 0.33 94.89 4.04 87.19 2.46 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2384804176
96.99 1.21 98.75 0.12 96.25 0.14 98.53 0.00 99.50 0.17 98.25 3.36 90.64 3.45 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3087461246
97.95 0.97 99.11 0.36 97.64 1.39 98.70 0.17 99.67 0.17 98.52 0.27 94.09 3.45 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3089694286
98.32 0.37 99.11 0.00 97.64 0.00 98.70 0.00 99.67 0.00 98.52 0.00 96.31 2.22 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2339634991
98.59 0.27 99.40 0.30 98.13 0.49 99.04 0.34 99.67 0.00 98.52 0.00 96.80 0.49 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.434451662
98.83 0.24 99.40 0.00 98.27 0.14 99.16 0.13 99.83 0.17 98.52 0.00 97.78 0.99 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.640114199
99.03 0.21 99.40 0.00 98.27 0.00 99.75 0.59 99.83 0.00 98.92 0.40 98.03 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.2965512288
99.15 0.12 99.40 0.00 98.47 0.21 99.75 0.00 99.83 0.00 98.92 0.00 98.52 0.49 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.52717974
99.23 0.08 99.40 0.00 98.54 0.07 99.75 0.00 99.83 0.00 99.06 0.13 98.77 0.25 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.3058542243
99.30 0.07 99.40 0.00 98.96 0.42 99.75 0.00 99.83 0.00 99.06 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4031328927
99.33 0.03 99.40 0.00 99.03 0.07 99.75 0.00 99.83 0.00 99.19 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.914825285
99.36 0.03 99.40 0.00 99.03 0.00 99.92 0.17 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1611001346
99.38 0.02 99.40 0.00 99.17 0.14 99.92 0.00 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.915687393
99.40 0.02 99.40 0.00 99.17 0.00 99.92 0.00 99.83 0.00 99.33 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3848033837
99.43 0.02 99.40 0.00 99.17 0.00 99.92 0.00 99.83 0.00 99.46 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.2200442381
99.44 0.01 99.40 0.00 99.17 0.00 100.00 0.08 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1800746597
99.45 0.01 99.40 0.00 99.24 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2517317673
99.46 0.01 99.40 0.00 99.31 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1110893712

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3146143386
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.582605665
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.419426683
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3445777861
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3954545203
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.3540215721
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.985541773
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.311043659
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2268663790
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1946015488
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1283144904
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1110143418
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4002172360
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1970705304
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3150340223
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.720110225
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4161964136
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1777145121
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.410674955
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2568566694
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2071562838
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1027808990
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.530859215
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2563344761
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4255026120
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1678481418
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2351129177
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4187551005
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2323482510
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3319831464
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3818546373
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1304409584
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1475639588
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3884295898
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2101940869
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3151623260
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3202857716
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3080919081
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2425587795
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1568104981
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1729327626
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1730860380
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1308980784
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1314122904
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3646035214
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.156108451
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3122758824
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1383771941
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2723878731
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1434771169
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.564595847
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3718559653
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1203550125
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2117005411
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3735373444
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2741116510
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1719441220
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2954540914
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1722996940
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2875148041
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3762192934
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4153217732
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2567381221
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3541487227
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.534047518
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.447621098
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1729172295
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2203637941
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2093076967
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2358632706
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2027685617
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.4257947797
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1411975420
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.3323856215
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3810815079
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1186750265
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4272084457
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3975917412
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1392168355
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3985552074
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3765300873
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.3050416560
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3032590948
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.926397578
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3919871634
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2569110977
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.542718322
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2096093347
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1037725719
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4291400866
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.945377774
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3004253756
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2632443293
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1930294325
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4105069003
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3393488077
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1680736892
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4001956973
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/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3972190071
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3902486976
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.83334979
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3968259155
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.2891319798
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2539808626
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.161280356
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1006173061
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.641368769
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3476380944
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2924145733
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1813747889
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.2440627189
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.1353471539
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.3590443216
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1903850782
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2837693689
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.35944996
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.222708862
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2073039175
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3258119574
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3162443337
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1303692379
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.14300532
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1909041265
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3701628242
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.655337456
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3327670166
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1142209508
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3596764220
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.2221001708
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.331522402
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.651125569
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2527426223
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3980694556
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1980496696
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1573688722
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1459538839
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3125118833
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.3780233414
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2194977822
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2561162401
/workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.3247279865



Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.2200442381 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:10 PM UTC 24 222567227 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.4203199604 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:10 PM UTC 24 203747919 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.434451662 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:10 PM UTC 24 68564973 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1483743208 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:10 PM UTC 24 135407525 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3889779957 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:10 PM UTC 24 173957068 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.4008195457 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:11 PM UTC 24 153455579 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1800746597 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:11 PM UTC 24 300995799 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1831187814 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:14 PM UTC 24 932037903 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1454512146 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:16 PM UTC 24 1267505879 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2384804176 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:22 PM UTC 24 8300019968 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3375750160 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 162821428 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3596764220 Aug 27 02:47:38 PM UTC 24 Aug 27 02:47:40 PM UTC 24 194283668 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1903850782 Aug 27 02:47:37 PM UTC 24 Aug 27 02:47:40 PM UTC 24 302870178 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1927293748 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 169370078 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.817367072 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 201363448 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1173964914 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 78771674 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.306228255 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 82577501 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3255758600 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:25 PM UTC 24 145106785 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2643886018 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 75911178 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2609192926 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 301498143 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.640114199 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 176278347 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3198807725 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 85119755 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.238128955 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 100952091 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2319727260 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 261863286 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2614582859 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 115193633 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3017079029 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 301533406 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.382138111 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 271782882 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.67383758 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:26 PM UTC 24 337190757 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.914825285 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:28 PM UTC 24 775293502 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2175107011 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:29 PM UTC 24 1280406175 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.353819613 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:30 PM UTC 24 1274123255 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3717070268 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:31 PM UTC 24 1609425427 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.3005947500 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:31 PM UTC 24 1866592599 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3698123498 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:32 PM UTC 24 89914427 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.331522402 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:43 PM UTC 24 352401725 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3727129905 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:33 PM UTC 24 106482921 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1850884085 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 103855691 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.2556732165 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:33 PM UTC 24 72869650 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.101788296 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:33 PM UTC 24 121360255 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.951095867 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 174455258 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.2784728871 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 74450331 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3390850116 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:33 PM UTC 24 138906635 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1699196645 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 102986498 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2701360146 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 108032091 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3968259155 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 78164797 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3954004127 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:33 PM UTC 24 301916801 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2781633662 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:33 PM UTC 24 302525708 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3972190071 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:34 PM UTC 24 126486185 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.1897679036 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:34 PM UTC 24 299284200 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1962520558 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:36 PM UTC 24 904203084 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.794963582 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:36 PM UTC 24 193580193 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1006173061 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:37 PM UTC 24 101082003 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1588976822 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:37 PM UTC 24 72748200 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.2891319798 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:37 PM UTC 24 71901624 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1303692379 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:37 PM UTC 24 82820770 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2339634991 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:37 PM UTC 24 133328725 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2837693689 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:37 PM UTC 24 79244482 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2924145733 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:37 PM UTC 24 226825349 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.161280356 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:38 PM UTC 24 301117317 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2073039175 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:38 PM UTC 24 128199154 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2497932699 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:38 PM UTC 24 301905709 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3476380944 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:38 PM UTC 24 164939509 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.83334979 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:38 PM UTC 24 369616307 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.4006010300 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:38 PM UTC 24 1758464664 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.70739722 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:38 PM UTC 24 1965166647 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3087461246 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:38 PM UTC 24 1853624144 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.2440627189 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:39 PM UTC 24 375084775 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.2965512288 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:39 PM UTC 24 1990007211 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.1353471539 Aug 27 02:47:38 PM UTC 24 Aug 27 02:47:40 PM UTC 24 63325916 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.222708862 Aug 27 02:47:37 PM UTC 24 Aug 27 02:47:40 PM UTC 24 177873195 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.3800791779 Aug 27 02:47:08 PM UTC 24 Aug 27 02:47:40 PM UTC 24 8899814689 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.14300532 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:41 PM UTC 24 63147889 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.655337456 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:41 PM UTC 24 185374001 ps
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T156 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.651125569 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:41 PM UTC 24 100577372 ps
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T23 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1573688722 Aug 27 02:47:41 PM UTC 24 Aug 27 02:47:43 PM UTC 24 189738316 ps
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T160 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3125118833 Aug 27 02:47:41 PM UTC 24 Aug 27 02:47:43 PM UTC 24 111067116 ps
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T161 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2527426223 Aug 27 02:47:42 PM UTC 24 Aug 27 02:47:44 PM UTC 24 85286291 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1980496696 Aug 27 02:47:42 PM UTC 24 Aug 27 02:47:44 PM UTC 24 301914921 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2906612341 Aug 27 02:47:42 PM UTC 24 Aug 27 02:47:45 PM UTC 24 160115256 ps
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T107 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1813747889 Aug 27 02:47:35 PM UTC 24 Aug 27 02:47:45 PM UTC 24 1974919230 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1909041265 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:46 PM UTC 24 1261828684 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.3590443216 Aug 27 02:47:37 PM UTC 24 Aug 27 02:47:47 PM UTC 24 1963465571 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1498416448 Aug 27 02:47:53 PM UTC 24 Aug 27 02:48:00 PM UTC 24 1442288789 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3652445049 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 113284344 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.3209689190 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 76828241 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2710429718 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 323279112 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3327670166 Aug 27 02:47:39 PM UTC 24 Aug 27 02:47:48 PM UTC 24 2161205703 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2076398824 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 149993668 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3287728458 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 110566663 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1459538839 Aug 27 02:47:41 PM UTC 24 Aug 27 02:47:48 PM UTC 24 1535870090 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.2516372621 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 107695965 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3495485689 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 109707618 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.4052038563 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 201114075 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2700066333 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 73354854 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2243437846 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:48 PM UTC 24 113361746 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3853456376 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:49 PM UTC 24 301946060 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2619728301 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:49 PM UTC 24 139315281 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.603143321 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:49 PM UTC 24 244784354 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2219940343 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:49 PM UTC 24 283284548 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3258119574 Aug 27 02:47:37 PM UTC 24 Aug 27 02:47:50 PM UTC 24 3472969778 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2929681895 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:50 PM UTC 24 16575240678 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3980694556 Aug 27 02:47:42 PM UTC 24 Aug 27 02:47:50 PM UTC 24 1984038386 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3902486976 Aug 27 02:47:34 PM UTC 24 Aug 27 02:47:51 PM UTC 24 3260508144 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1875102483 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:51 PM UTC 24 114611433 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.2376152571 Aug 27 02:47:54 PM UTC 24 Aug 27 02:48:00 PM UTC 24 833952061 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.2158433770 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:51 PM UTC 24 73984834 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3876994893 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:51 PM UTC 24 302783976 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.3413205991 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:51 PM UTC 24 204527849 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2788699429 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 102578647 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2551421267 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 67610663 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.2536950326 Aug 27 02:47:23 PM UTC 24 Aug 27 02:47:52 PM UTC 24 7533959988 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.15547503 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 301487870 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4242332072 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 101026774 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.1132215645 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 191988851 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3143638499 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:52 PM UTC 24 271328869 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1281381409 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:53 PM UTC 24 399612584 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.635228074 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:53 PM UTC 24 147118097 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3674546053 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:53 PM UTC 24 1730882116 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.1803255134 Aug 27 02:47:51 PM UTC 24 Aug 27 02:47:53 PM UTC 24 188246017 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2257538040 Aug 27 02:47:51 PM UTC 24 Aug 27 02:47:53 PM UTC 24 69897749 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.40342045 Aug 27 02:47:51 PM UTC 24 Aug 27 02:47:54 PM UTC 24 154233158 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3241895258 Aug 27 02:47:51 PM UTC 24 Aug 27 02:47:54 PM UTC 24 199193988 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3103561162 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:54 PM UTC 24 1616917599 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1611001346 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:54 PM UTC 24 1978340610 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.1903312709 Aug 27 02:47:53 PM UTC 24 Aug 27 02:47:55 PM UTC 24 95654558 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.4239251467 Aug 27 02:47:52 PM UTC 24 Aug 27 02:47:55 PM UTC 24 68488877 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.18703434 Aug 27 02:47:52 PM UTC 24 Aug 27 02:47:55 PM UTC 24 301154806 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3909720528 Aug 27 02:47:52 PM UTC 24 Aug 27 02:47:55 PM UTC 24 142164134 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.4030799396 Aug 27 02:47:52 PM UTC 24 Aug 27 02:47:55 PM UTC 24 183822442 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3576095793 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:55 PM UTC 24 2103712349 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.1155561373 Aug 27 02:47:53 PM UTC 24 Aug 27 02:47:55 PM UTC 24 264613088 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.3666737414 Aug 27 02:47:52 PM UTC 24 Aug 27 02:47:56 PM UTC 24 128904353 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.784835656 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:56 PM UTC 24 2271839305 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.948801400 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:56 PM UTC 24 99527145 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2684543551 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:56 PM UTC 24 59786811 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.36455109 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:56 PM UTC 24 301319534 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.144827739 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:57 PM UTC 24 124196377 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2605560659 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:57 PM UTC 24 182865694 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2546538177 Aug 27 02:47:46 PM UTC 24 Aug 27 02:47:57 PM UTC 24 2233598647 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3946500176 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:57 PM UTC 24 1950913100 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3363341553 Aug 27 02:47:30 PM UTC 24 Aug 27 02:47:57 PM UTC 24 16645034876 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1776575679 Aug 27 02:47:51 PM UTC 24 Aug 27 02:47:57 PM UTC 24 1026874353 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.1217862361 Aug 27 02:47:54 PM UTC 24 Aug 27 02:47:57 PM UTC 24 125025294 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1455137347 Aug 27 02:47:31 PM UTC 24 Aug 27 02:47:57 PM UTC 24 16759001208 ps
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T31 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.2622520911 Aug 27 02:47:49 PM UTC 24 Aug 27 02:47:58 PM UTC 24 1955720660 ps
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T212 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.1824340535 Aug 27 02:47:57 PM UTC 24 Aug 27 02:47:59 PM UTC 24 81576069 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2194977822 Aug 27 02:47:42 PM UTC 24 Aug 27 02:47:59 PM UTC 24 3740272446 ps
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T215 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.508948634 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:00 PM UTC 24 301448315 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.408673514 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:00 PM UTC 24 178362229 ps
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T218 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3961463737 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:00 PM UTC 24 175828236 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3102735211 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:00 PM UTC 24 185947133 ps
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T233 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2735396882 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:03 PM UTC 24 69779959 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1055641169 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:03 PM UTC 24 302400239 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.2412953544 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:03 PM UTC 24 157148561 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3780876757 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:04 PM UTC 24 301405605 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1255063844 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:04 PM UTC 24 199157395 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3930784499 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:04 PM UTC 24 1485335616 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.887215241 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:04 PM UTC 24 164109213 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.3614506982 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:04 PM UTC 24 256749458 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.446065369 Aug 27 02:48:02 PM UTC 24 Aug 27 02:48:05 PM UTC 24 196409761 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.2985225408 Aug 27 02:48:02 PM UTC 24 Aug 27 02:48:05 PM UTC 24 92078464 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.1303180467 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:05 PM UTC 24 568376466 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2544254822 Aug 27 02:48:03 PM UTC 24 Aug 27 02:48:05 PM UTC 24 138194787 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.757949663 Aug 27 02:48:03 PM UTC 24 Aug 27 02:48:05 PM UTC 24 302661788 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3074377025 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:05 PM UTC 24 155872589 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.602062437 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:05 PM UTC 24 1962456749 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.4260151144 Aug 27 02:48:02 PM UTC 24 Aug 27 02:48:06 PM UTC 24 126406360 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.4272402980 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:06 PM UTC 24 70857104 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3089599556 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:06 PM UTC 24 97577336 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1876177235 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:06 PM UTC 24 97278131 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3713890226 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:06 PM UTC 24 75576437 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2664914089 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:07 PM UTC 24 234165653 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.983659451 Aug 27 02:47:57 PM UTC 24 Aug 27 02:48:07 PM UTC 24 2452795739 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.450545590 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:07 PM UTC 24 895241187 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3518326732 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:07 PM UTC 24 231282116 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1240337449 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:07 PM UTC 24 302359344 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2809135112 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:07 PM UTC 24 400409661 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1163588039 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:08 PM UTC 24 1470965547 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2861737103 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 169526600 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.2853216425 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:08 PM UTC 24 1268078739 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1332348520 Aug 27 02:47:54 PM UTC 24 Aug 27 02:48:08 PM UTC 24 3101170787 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.2819001847 Aug 27 02:48:02 PM UTC 24 Aug 27 02:48:08 PM UTC 24 909945102 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3834980924 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 111700641 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1815857188 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 84822043 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.3571778427 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 218747611 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.485319900 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 201583538 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.2272796285 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 123119724 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.968621888 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:08 PM UTC 24 138863202 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1194866044 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:09 PM UTC 24 302200335 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.3116856509 Aug 27 02:47:49 PM UTC 24 Aug 27 02:48:09 PM UTC 24 5591915041 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3780372794 Aug 27 02:48:03 PM UTC 24 Aug 27 02:48:09 PM UTC 24 1266746559 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.119554127 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:10 PM UTC 24 803417103 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.1446220192 Aug 27 02:48:01 PM UTC 24 Aug 27 02:48:10 PM UTC 24 1979721030 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.655799588 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:11 PM UTC 24 169982041 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.348049316 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:11 PM UTC 24 59198819 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.1138989709 Aug 27 02:48:04 PM UTC 24 Aug 27 02:48:11 PM UTC 24 1278032058 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.1539852238 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:11 PM UTC 24 130208284 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.3300589573 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 149189362 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.1405464252 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 109698788 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1357883962 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 301654491 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.1349032202 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 92414562 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.2860159980 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 128275021 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2995178548 Aug 27 02:48:09 PM UTC 24 Aug 27 02:48:12 PM UTC 24 170360384 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.136470225 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 77329661 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.1844275996 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 199533281 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.4289657641 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:12 PM UTC 24 1283997616 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1094558522 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 302209484 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2103319884 Aug 27 02:48:06 PM UTC 24 Aug 27 02:48:12 PM UTC 24 1547495120 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.667814199 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 142458345 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1654408510 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 79782170 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2445059454 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:12 PM UTC 24 125788453 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1725601542 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:13 PM UTC 24 160607671 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3332102425 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:14 PM UTC 24 401441462 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.2566231520 Aug 27 02:48:11 PM UTC 24 Aug 27 02:48:14 PM UTC 24 61605309 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2255394366 Aug 27 02:48:11 PM UTC 24 Aug 27 02:48:14 PM UTC 24 301982609 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.782607712 Aug 27 02:48:11 PM UTC 24 Aug 27 02:48:14 PM UTC 24 111867991 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.530824015 Aug 27 02:48:10 PM UTC 24 Aug 27 02:48:15 PM UTC 24 854696816 ps
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