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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T540 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.1260115807 Aug 27 02:48:50 PM UTC 24 Aug 27 02:49:41 PM UTC 24 1267209187 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.1862145157 Aug 27 02:48:50 PM UTC 24 Aug 27 02:49:41 PM UTC 24 1827176790 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.698805431 Aug 27 02:48:50 PM UTC 24 Aug 27 02:49:46 PM UTC 24 4416022572 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.2349616292 Aug 27 02:48:48 PM UTC 24 Aug 27 02:49:58 PM UTC 24 16583788295 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.964655022 Aug 27 02:48:53 PM UTC 24 Aug 27 02:50:10 PM UTC 24 12588998840 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3848033837 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:12 PM UTC 24 263780608 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3146143386 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:12 PM UTC 24 205527339 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3089694286 Aug 27 02:49:11 PM UTC 24 Aug 27 02:49:16 PM UTC 24 202403474 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.582605665 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:19 PM UTC 24 2274930429 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.419426683 Aug 27 02:48:54 PM UTC 24 Aug 27 02:49:26 PM UTC 24 99777435 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3954545203 Aug 27 02:48:54 PM UTC 24 Aug 27 02:49:26 PM UTC 24 88481401 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.3540215721 Aug 27 02:48:53 PM UTC 24 Aug 27 02:49:26 PM UTC 24 94118745 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2027685617 Aug 27 02:49:14 PM UTC 24 Aug 27 02:49:26 PM UTC 24 108278302 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.985541773 Aug 27 02:49:04 PM UTC 24 Aug 27 02:49:27 PM UTC 24 207448641 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1411975420 Aug 27 02:49:13 PM UTC 24 Aug 27 02:49:27 PM UTC 24 285487915 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2517317673 Aug 27 02:48:54 PM UTC 24 Aug 27 02:49:27 PM UTC 24 501570841 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2203637941 Aug 27 02:49:13 PM UTC 24 Aug 27 02:49:28 PM UTC 24 400369408 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.706140177 Aug 27 02:49:18 PM UTC 24 Aug 27 02:49:29 PM UTC 24 971376360 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3985552074 Aug 27 02:49:19 PM UTC 24 Aug 27 02:49:31 PM UTC 24 75704850 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1283144904 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:31 PM UTC 24 58271440 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.534047518 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:31 PM UTC 24 67356038 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2567381221 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:31 PM UTC 24 92199123 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2268663790 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:31 PM UTC 24 123734273 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3445777861 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:31 PM UTC 24 128029875 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2358632706 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:31 PM UTC 24 114779083 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1304409584 Aug 27 02:49:38 PM UTC 24 Aug 27 02:49:41 PM UTC 24 67731837 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.447621098 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:32 PM UTC 24 129455681 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.4257947797 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:32 PM UTC 24 65033544 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1186750265 Aug 27 02:49:26 PM UTC 24 Aug 27 02:49:32 PM UTC 24 238583709 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1037725719 Aug 27 02:49:29 PM UTC 24 Aug 27 02:49:32 PM UTC 24 72615679 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3032590948 Aug 27 02:49:28 PM UTC 24 Aug 27 02:49:32 PM UTC 24 130361705 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3919871634 Aug 27 02:49:28 PM UTC 24 Aug 27 02:49:32 PM UTC 24 131946900 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3541487227 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:32 PM UTC 24 160865034 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3762192934 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:32 PM UTC 24 255957035 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.945377774 Aug 27 02:49:29 PM UTC 24 Aug 27 02:49:32 PM UTC 24 231248533 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4291400866 Aug 27 02:49:30 PM UTC 24 Aug 27 02:49:33 PM UTC 24 243875448 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.3323856215 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:33 PM UTC 24 348409390 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1729172295 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:33 PM UTC 24 912368796 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4031328927 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:33 PM UTC 24 210816648 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3810815079 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:34 PM UTC 24 908404324 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.542718322 Aug 27 02:49:27 PM UTC 24 Aug 27 02:49:34 PM UTC 24 489993787 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3004253756 Aug 27 02:49:29 PM UTC 24 Aug 27 02:49:34 PM UTC 24 784363868 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.915687393 Aug 27 02:48:58 PM UTC 24 Aug 27 02:49:35 PM UTC 24 1893168902 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2093076967 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:35 PM UTC 24 812828577 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4153217732 Aug 27 02:49:12 PM UTC 24 Aug 27 02:49:36 PM UTC 24 492365662 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.926397578 Aug 27 02:49:27 PM UTC 24 Aug 27 02:49:36 PM UTC 24 63694535 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3765300873 Aug 27 02:49:27 PM UTC 24 Aug 27 02:49:36 PM UTC 24 146324973 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1392168355 Aug 27 02:49:27 PM UTC 24 Aug 27 02:49:36 PM UTC 24 172156733 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2569110977 Aug 27 02:49:27 PM UTC 24 Aug 27 02:49:36 PM UTC 24 103439532 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2329069542 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:36 PM UTC 24 77245717 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2198726714 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 76830251 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4272084457 Aug 27 02:49:20 PM UTC 24 Aug 27 02:49:37 PM UTC 24 483948100 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3150340223 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 83649808 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1970705304 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 62745132 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.798709976 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 120113797 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4002172360 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 119541317 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.802091434 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 174872914 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1838545809 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 420368359 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3768494798 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 196817270 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3417665105 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:37 PM UTC 24 143828548 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4001956973 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:38 PM UTC 24 184898334 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1110893712 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:38 PM UTC 24 232454349 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2568566694 Aug 27 02:49:36 PM UTC 24 Aug 27 02:49:38 PM UTC 24 101612618 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3393488077 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:38 PM UTC 24 147447744 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2632443293 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:38 PM UTC 24 174830617 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.863884326 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:38 PM UTC 24 878194578 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4161964136 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:39 PM UTC 24 908747654 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.4090038335 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:39 PM UTC 24 280373993 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.52717974 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:39 PM UTC 24 821492160 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.720110225 Aug 27 02:49:34 PM UTC 24 Aug 27 02:49:39 PM UTC 24 422152845 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1027808990 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:39 PM UTC 24 61037811 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4105069003 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:41 PM UTC 24 137748524 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1930294325 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:40 PM UTC 24 90190987 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2096093347 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:41 PM UTC 24 206081539 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4187551005 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:41 PM UTC 24 131483688 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3884295898 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:41 PM UTC 24 162111806 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1777145121 Aug 27 02:49:36 PM UTC 24 Aug 27 02:49:42 PM UTC 24 171321525 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1730860380 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 63188652 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3202857716 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 79900350 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4255026120 Aug 27 02:49:36 PM UTC 24 Aug 27 02:49:42 PM UTC 24 526166241 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2323482510 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:42 PM UTC 24 182648161 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3122758824 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 80112423 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3718559653 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 63363765 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1308980784 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 120947114 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1680736892 Aug 27 02:49:32 PM UTC 24 Aug 27 02:49:42 PM UTC 24 496238198 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3818546373 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 131125080 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.564595847 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 137237088 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2425587795 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 216440514 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3151623260 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:42 PM UTC 24 164031082 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1568104981 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:43 PM UTC 24 494074033 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.311043659 Aug 27 02:49:00 PM UTC 24 Aug 27 02:49:44 PM UTC 24 2314849679 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.156108451 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:45 PM UTC 24 125577809 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1383771941 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:45 PM UTC 24 88454351 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1203550125 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:46 PM UTC 24 107737409 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2071562838 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:46 PM UTC 24 120441818 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1434771169 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:46 PM UTC 24 426328219 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2117005411 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:47 PM UTC 24 193119793 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3735373444 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:47 PM UTC 24 928713439 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1719441220 Aug 27 02:49:42 PM UTC 24 Aug 27 02:49:51 PM UTC 24 82899737 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2741116510 Aug 27 02:49:42 PM UTC 24 Aug 27 02:49:51 PM UTC 24 183240343 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2954540914 Aug 27 02:49:42 PM UTC 24 Aug 27 02:49:51 PM UTC 24 244037447 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1722996940 Aug 27 02:49:42 PM UTC 24 Aug 27 02:49:52 PM UTC 24 129317888 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3080919081 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:52 PM UTC 24 84409452 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1314122904 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:52 PM UTC 24 113456407 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2875148041 Aug 27 02:49:42 PM UTC 24 Aug 27 02:49:53 PM UTC 24 795695404 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1729327626 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:53 PM UTC 24 174069830 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3646035214 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:53 PM UTC 24 467498639 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2723878731 Aug 27 02:49:40 PM UTC 24 Aug 27 02:49:53 PM UTC 24 276415999 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2101940869 Aug 27 02:49:38 PM UTC 24 Aug 27 02:49:54 PM UTC 24 885658536 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1678481418 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:56 PM UTC 24 99279414 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1475639588 Aug 27 02:49:38 PM UTC 24 Aug 27 02:49:56 PM UTC 24 151031950 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2351129177 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:56 PM UTC 24 78659810 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3975917412 Aug 27 02:49:18 PM UTC 24 Aug 27 02:49:57 PM UTC 24 145484270 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.530859215 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:57 PM UTC 24 95076121 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1946015488 Aug 27 02:49:08 PM UTC 24 Aug 27 02:49:57 PM UTC 24 105652586 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.410674955 Aug 27 02:49:35 PM UTC 24 Aug 27 02:49:57 PM UTC 24 79702556 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3319831464 Aug 27 02:49:37 PM UTC 24 Aug 27 02:49:57 PM UTC 24 477835341 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1110143418 Aug 27 02:49:05 PM UTC 24 Aug 27 02:49:57 PM UTC 24 77739324 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2563344761 Aug 27 02:49:36 PM UTC 24 Aug 27 02:49:58 PM UTC 24 91248818 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.3050416560 Aug 27 02:49:16 PM UTC 24 Aug 27 02:49:59 PM UTC 24 186374904 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.4203199604
Short name T2
Test name
Test status
Simulation time 203747919 ps
CPU time 1.4 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:10 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203199604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.4203199604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.382138111
Short name T57
Test name
Test status
Simulation time 271782882 ps
CPU time 1.86 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382138111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.382138111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2175107011
Short name T44
Test name
Test status
Simulation time 1280406175 ps
CPU time 5.15 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:29 PM UTC 24
Peak memory 241608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175107011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.2175107011
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.706140177
Short name T71
Test name
Test status
Simulation time 971376360 ps
CPU time 3.04 seconds
Started Aug 27 02:49:18 PM UTC 24
Finished Aug 27 02:49:29 PM UTC 24
Peak memory 208536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706140177 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.706140177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2384804176
Short name T10
Test name
Test status
Simulation time 8300019968 ps
CPU time 12.91 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:22 PM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384804176 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2384804176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3087461246
Short name T102
Test name
Test status
Simulation time 1853624144 ps
CPU time 6.9 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087461246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3087461246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3089694286
Short name T61
Test name
Test status
Simulation time 202403474 ps
CPU time 1.44 seconds
Started Aug 27 02:49:11 PM UTC 24
Finished Aug 27 02:49:16 PM UTC 24
Peak memory 223940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089694286 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.3089694286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2339634991
Short name T83
Test name
Test status
Simulation time 133328725 ps
CPU time 1.32 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339634991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2339634991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.434451662
Short name T3
Test name
Test status
Simulation time 68564973 ps
CPU time 1.04 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:10 PM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434451662 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.434451662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.640114199
Short name T25
Test name
Test status
Simulation time 176278347 ps
CPU time 1.21 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640114199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.640114199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.2965512288
Short name T27
Test name
Test status
Simulation time 1990007211 ps
CPU time 7.16 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:39 PM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965512288 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2965512288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.52717974
Short name T126
Test name
Test status
Simulation time 821492160 ps
CPU time 2.63 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:39 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52717974 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.52717974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.3058542243
Short name T91
Test name
Test status
Simulation time 2228929005 ps
CPU time 10.98 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 209220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058542243 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3058542243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4031328927
Short name T97
Test name
Test status
Simulation time 210816648 ps
CPU time 2.89 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 220920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031328927 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.4031328927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.914825285
Short name T77
Test name
Test status
Simulation time 775293502 ps
CPU time 4.26 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:28 PM UTC 24
Peak memory 209280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914825285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.914825285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1611001346
Short name T56
Test name
Test status
Simulation time 1978340610 ps
CPU time 7.26 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:54 PM UTC 24
Peak memory 242404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611001346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1611001346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.915687393
Short name T128
Test name
Test status
Simulation time 1893168902 ps
CPU time 4.72 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:35 PM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915687393 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.915687393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.3848033837
Short name T59
Test name
Test status
Simulation time 263780608 ps
CPU time 1.38 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:12 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848033837 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.3848033837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.2200442381
Short name T1
Test name
Test status
Simulation time 222567227 ps
CPU time 1.25 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:10 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200442381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2200442381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1800746597
Short name T7
Test name
Test status
Simulation time 300995799 ps
CPU time 1.9 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:11 PM UTC 24
Peak memory 237584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800746597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1800746597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2517317673
Short name T70
Test name
Test status
Simulation time 501570841 ps
CPU time 1.73 seconds
Started Aug 27 02:48:54 PM UTC 24
Finished Aug 27 02:49:27 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517317673 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.2517317673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.1110893712
Short name T568
Test name
Test status
Simulation time 232454349 ps
CPU time 1.65 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 221716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110893712 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.1110893712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3146143386
Short name T60
Test name
Test status
Simulation time 205527339 ps
CPU time 1.39 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:12 PM UTC 24
Peak memory 208460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146143386 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3146143386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.582605665
Short name T62
Test name
Test status
Simulation time 2274930429 ps
CPU time 8.46 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:19 PM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582605665 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.582605665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.419426683
Short name T64
Test name
Test status
Simulation time 99777435 ps
CPU time 0.72 seconds
Started Aug 27 02:48:54 PM UTC 24
Finished Aug 27 02:49:26 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419426683 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.419426683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3445777861
Short name T92
Test name
Test status
Simulation time 128029875 ps
CPU time 1.01 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 217572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3445777861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w
ith_rand_reset.3445777861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.3954545203
Short name T63
Test name
Test status
Simulation time 88481401 ps
CPU time 0.77 seconds
Started Aug 27 02:48:54 PM UTC 24
Finished Aug 27 02:49:26 PM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954545203 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.3954545203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.3540215721
Short name T68
Test name
Test status
Simulation time 94118745 ps
CPU time 1.18 seconds
Started Aug 27 02:48:53 PM UTC 24
Finished Aug 27 02:49:26 PM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540215721 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3540215721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.985541773
Short name T545
Test name
Test status
Simulation time 207448641 ps
CPU time 1.38 seconds
Started Aug 27 02:49:04 PM UTC 24
Finished Aug 27 02:49:27 PM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985541773 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.985541773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.311043659
Short name T594
Test name
Test status
Simulation time 2314849679 ps
CPU time 8.89 seconds
Started Aug 27 02:49:00 PM UTC 24
Finished Aug 27 02:49:44 PM UTC 24
Peak memory 208840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311043659 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.311043659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2268663790
Short name T549
Test name
Test status
Simulation time 123734273 ps
CPU time 0.79 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 205636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268663790 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.2268663790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1946015488
Short name T616
Test name
Test status
Simulation time 105652586 ps
CPU time 0.98 seconds
Started Aug 27 02:49:08 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1946015488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w
ith_rand_reset.1946015488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.1283144904
Short name T116
Test name
Test status
Simulation time 58271440 ps
CPU time 0.7 seconds
Started Aug 27 02:48:58 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283144904 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.1283144904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.1110143418
Short name T618
Test name
Test status
Simulation time 77739324 ps
CPU time 0.91 seconds
Started Aug 27 02:49:05 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110143418 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.1110143418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4002172360
Short name T563
Test name
Test status
Simulation time 119541317 ps
CPU time 0.94 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4002172360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_
with_rand_reset.4002172360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1970705304
Short name T561
Test name
Test status
Simulation time 62745132 ps
CPU time 0.88 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970705304 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1970705304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3150340223
Short name T560
Test name
Test status
Simulation time 83649808 ps
CPU time 0.84 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150340223 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.3150340223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.720110225
Short name T574
Test name
Test status
Simulation time 422152845 ps
CPU time 3.18 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:39 PM UTC 24
Peak memory 217720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720110225 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.720110225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.4161964136
Short name T143
Test name
Test status
Simulation time 908747654 ps
CPU time 2.8 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:39 PM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161964136 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.4161964136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1777145121
Short name T581
Test name
Test status
Simulation time 171321525 ps
CPU time 1.58 seconds
Started Aug 27 02:49:36 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 217044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1777145121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_
with_rand_reset.1777145121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.410674955
Short name T617
Test name
Test status
Simulation time 79702556 ps
CPU time 0.77 seconds
Started Aug 27 02:49:35 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410674955 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.410674955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.2568566694
Short name T569
Test name
Test status
Simulation time 101612618 ps
CPU time 1.11 seconds
Started Aug 27 02:49:36 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568566694 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.2568566694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2071562838
Short name T598
Test name
Test status
Simulation time 120441818 ps
CPU time 1.13 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:46 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2071562838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_
with_rand_reset.2071562838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1027808990
Short name T575
Test name
Test status
Simulation time 61037811 ps
CPU time 0.7 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:39 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027808990 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1027808990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.530859215
Short name T615
Test name
Test status
Simulation time 95076121 ps
CPU time 1.09 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530859215 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.530859215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2563344761
Short name T619
Test name
Test status
Simulation time 91248818 ps
CPU time 1.19 seconds
Started Aug 27 02:49:36 PM UTC 24
Finished Aug 27 02:49:58 PM UTC 24
Peak memory 217696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563344761 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2563344761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4255026120
Short name T127
Test name
Test status
Simulation time 526166241 ps
CPU time 1.99 seconds
Started Aug 27 02:49:36 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255026120 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.4255026120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1678481418
Short name T611
Test name
Test status
Simulation time 99279414 ps
CPU time 0.85 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:56 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1678481418 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_
with_rand_reset.1678481418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2351129177
Short name T613
Test name
Test status
Simulation time 78659810 ps
CPU time 0.82 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:56 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351129177 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2351129177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.4187551005
Short name T579
Test name
Test status
Simulation time 131483688 ps
CPU time 1 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187551005 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.4187551005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.2323482510
Short name T584
Test name
Test status
Simulation time 182648161 ps
CPU time 2.21 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 217716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323482510 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2323482510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3319831464
Short name T129
Test name
Test status
Simulation time 477835341 ps
CPU time 1.76 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319831464 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3319831464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.3818546373
Short name T589
Test name
Test status
Simulation time 131125080 ps
CPU time 1.31 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3818546373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_
with_rand_reset.3818546373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.1304409584
Short name T117
Test name
Test status
Simulation time 67731837 ps
CPU time 0.71 seconds
Started Aug 27 02:49:38 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 207564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304409584 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.1304409584
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.1475639588
Short name T612
Test name
Test status
Simulation time 151031950 ps
CPU time 0.99 seconds
Started Aug 27 02:49:38 PM UTC 24
Finished Aug 27 02:49:56 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475639588 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.1475639588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3884295898
Short name T580
Test name
Test status
Simulation time 162111806 ps
CPU time 1.25 seconds
Started Aug 27 02:49:37 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884295898 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3884295898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2101940869
Short name T610
Test name
Test status
Simulation time 885658536 ps
CPU time 2.89 seconds
Started Aug 27 02:49:38 PM UTC 24
Finished Aug 27 02:49:54 PM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101940869 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.2101940869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3151623260
Short name T592
Test name
Test status
Simulation time 164031082 ps
CPU time 1.33 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3151623260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_
with_rand_reset.3151623260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.3202857716
Short name T583
Test name
Test status
Simulation time 79900350 ps
CPU time 0.77 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202857716 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.3202857716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3080919081
Short name T605
Test name
Test status
Simulation time 84409452 ps
CPU time 0.94 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:52 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080919081 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3080919081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2425587795
Short name T591
Test name
Test status
Simulation time 216440514 ps
CPU time 1.53 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425587795 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2425587795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1568104981
Short name T593
Test name
Test status
Simulation time 494074033 ps
CPU time 1.67 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:43 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568104981 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.1568104981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1729327626
Short name T607
Test name
Test status
Simulation time 174069830 ps
CPU time 1.53 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:53 PM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1729327626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_
with_rand_reset.1729327626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1730860380
Short name T582
Test name
Test status
Simulation time 63188652 ps
CPU time 0.66 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730860380 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1730860380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.1308980784
Short name T587
Test name
Test status
Simulation time 120947114 ps
CPU time 0.96 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308980784 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.1308980784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1314122904
Short name T606
Test name
Test status
Simulation time 113456407 ps
CPU time 1.42 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:52 PM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314122904 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1314122904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3646035214
Short name T608
Test name
Test status
Simulation time 467498639 ps
CPU time 1.9 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:53 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646035214 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.3646035214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.156108451
Short name T595
Test name
Test status
Simulation time 125577809 ps
CPU time 0.88 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:45 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=156108451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_w
ith_rand_reset.156108451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3122758824
Short name T585
Test name
Test status
Simulation time 80112423 ps
CPU time 0.72 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122758824 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.3122758824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1383771941
Short name T596
Test name
Test status
Simulation time 88454351 ps
CPU time 0.91 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:45 PM UTC 24
Peak memory 207844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383771941 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.1383771941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2723878731
Short name T609
Test name
Test status
Simulation time 276415999 ps
CPU time 1.93 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:53 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723878731 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2723878731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1434771169
Short name T132
Test name
Test status
Simulation time 426328219 ps
CPU time 1.59 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:46 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434771169 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.1434771169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.564595847
Short name T590
Test name
Test status
Simulation time 137237088 ps
CPU time 0.99 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=564595847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_w
ith_rand_reset.564595847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3718559653
Short name T586
Test name
Test status
Simulation time 63363765 ps
CPU time 0.72 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718559653 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.3718559653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1203550125
Short name T597
Test name
Test status
Simulation time 107737409 ps
CPU time 1.11 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:46 PM UTC 24
Peak memory 207792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203550125 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.1203550125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2117005411
Short name T599
Test name
Test status
Simulation time 193119793 ps
CPU time 2.36 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:47 PM UTC 24
Peak memory 217732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117005411 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.2117005411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3735373444
Short name T600
Test name
Test status
Simulation time 928713439 ps
CPU time 2.68 seconds
Started Aug 27 02:49:40 PM UTC 24
Finished Aug 27 02:49:47 PM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735373444 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.3735373444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.2741116510
Short name T602
Test name
Test status
Simulation time 183240343 ps
CPU time 1.12 seconds
Started Aug 27 02:49:42 PM UTC 24
Finished Aug 27 02:49:51 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2741116510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_
with_rand_reset.2741116510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1719441220
Short name T601
Test name
Test status
Simulation time 82899737 ps
CPU time 0.8 seconds
Started Aug 27 02:49:42 PM UTC 24
Finished Aug 27 02:49:51 PM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719441220 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1719441220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.2954540914
Short name T603
Test name
Test status
Simulation time 244037447 ps
CPU time 1.4 seconds
Started Aug 27 02:49:42 PM UTC 24
Finished Aug 27 02:49:51 PM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954540914 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.2954540914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1722996940
Short name T604
Test name
Test status
Simulation time 129317888 ps
CPU time 1.72 seconds
Started Aug 27 02:49:42 PM UTC 24
Finished Aug 27 02:49:52 PM UTC 24
Peak memory 217376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722996940 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1722996940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2875148041
Short name T131
Test name
Test status
Simulation time 795695404 ps
CPU time 2.6 seconds
Started Aug 27 02:49:42 PM UTC 24
Finished Aug 27 02:49:53 PM UTC 24
Peak memory 208560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875148041 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.2875148041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3762192934
Short name T553
Test name
Test status
Simulation time 255957035 ps
CPU time 1.62 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762192934 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3762192934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.4153217732
Short name T555
Test name
Test status
Simulation time 492365662 ps
CPU time 5.15 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153217732 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.4153217732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2567381221
Short name T548
Test name
Test status
Simulation time 92199123 ps
CPU time 0.74 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 207652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567381221 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2567381221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3541487227
Short name T93
Test name
Test status
Simulation time 160865034 ps
CPU time 1.46 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 217064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3541487227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w
ith_rand_reset.3541487227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.534047518
Short name T547
Test name
Test status
Simulation time 67356038 ps
CPU time 0.74 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534047518 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.534047518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.447621098
Short name T118
Test name
Test status
Simulation time 129455681 ps
CPU time 0.99 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447621098 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.447621098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.1729172295
Short name T96
Test name
Test status
Simulation time 912368796 ps
CPU time 3.06 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 208752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729172295 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.1729172295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2203637941
Short name T144
Test name
Test status
Simulation time 400369408 ps
CPU time 2.28 seconds
Started Aug 27 02:49:13 PM UTC 24
Finished Aug 27 02:49:28 PM UTC 24
Peak memory 208856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203637941 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2203637941
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2093076967
Short name T554
Test name
Test status
Simulation time 812828577 ps
CPU time 4.31 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:35 PM UTC 24
Peak memory 208800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093076967 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2093076967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2358632706
Short name T550
Test name
Test status
Simulation time 114779083 ps
CPU time 0.81 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358632706 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.2358632706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2027685617
Short name T69
Test name
Test status
Simulation time 108278302 ps
CPU time 0.79 seconds
Started Aug 27 02:49:14 PM UTC 24
Finished Aug 27 02:49:26 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2027685617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w
ith_rand_reset.2027685617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.4257947797
Short name T119
Test name
Test status
Simulation time 65033544 ps
CPU time 0.72 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257947797 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4257947797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.1411975420
Short name T115
Test name
Test status
Simulation time 285487915 ps
CPU time 1.45 seconds
Started Aug 27 02:49:13 PM UTC 24
Finished Aug 27 02:49:27 PM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411975420 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.1411975420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.3323856215
Short name T95
Test name
Test status
Simulation time 348409390 ps
CPU time 1.97 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323856215 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3323856215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3810815079
Short name T130
Test name
Test status
Simulation time 908404324 ps
CPU time 2.83 seconds
Started Aug 27 02:49:12 PM UTC 24
Finished Aug 27 02:49:34 PM UTC 24
Peak memory 208828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810815079 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.3810815079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1186750265
Short name T551
Test name
Test status
Simulation time 238583709 ps
CPU time 1.53 seconds
Started Aug 27 02:49:26 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186750265 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.1186750265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.4272084457
Short name T559
Test name
Test status
Simulation time 483948100 ps
CPU time 5.21 seconds
Started Aug 27 02:49:20 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272084457 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.4272084457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.3975917412
Short name T614
Test name
Test status
Simulation time 145484270 ps
CPU time 0.81 seconds
Started Aug 27 02:49:18 PM UTC 24
Finished Aug 27 02:49:57 PM UTC 24
Peak memory 207412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975917412 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.3975917412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1392168355
Short name T557
Test name
Test status
Simulation time 172156733 ps
CPU time 1 seconds
Started Aug 27 02:49:27 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1392168355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w
ith_rand_reset.1392168355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.3985552074
Short name T546
Test name
Test status
Simulation time 75704850 ps
CPU time 0.64 seconds
Started Aug 27 02:49:19 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985552074 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3985552074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3765300873
Short name T122
Test name
Test status
Simulation time 146324973 ps
CPU time 1.01 seconds
Started Aug 27 02:49:27 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765300873 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.3765300873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.3050416560
Short name T620
Test name
Test status
Simulation time 186374904 ps
CPU time 2.6 seconds
Started Aug 27 02:49:16 PM UTC 24
Finished Aug 27 02:49:59 PM UTC 24
Peak memory 225208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050416560 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3050416560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3032590948
Short name T98
Test name
Test status
Simulation time 130361705 ps
CPU time 0.97 seconds
Started Aug 27 02:49:28 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 217412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3032590948 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w
ith_rand_reset.3032590948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.926397578
Short name T556
Test name
Test status
Simulation time 63694535 ps
CPU time 0.7 seconds
Started Aug 27 02:49:27 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926397578 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.926397578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3919871634
Short name T120
Test name
Test status
Simulation time 131946900 ps
CPU time 1.02 seconds
Started Aug 27 02:49:28 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919871634 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.3919871634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2569110977
Short name T125
Test name
Test status
Simulation time 103439532 ps
CPU time 1.24 seconds
Started Aug 27 02:49:27 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 223468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569110977 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2569110977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.542718322
Short name T99
Test name
Test status
Simulation time 489993787 ps
CPU time 1.97 seconds
Started Aug 27 02:49:27 PM UTC 24
Finished Aug 27 02:49:34 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542718322 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.542718322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.2096093347
Short name T578
Test name
Test status
Simulation time 206081539 ps
CPU time 1.21 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2096093347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w
ith_rand_reset.2096093347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1037725719
Short name T552
Test name
Test status
Simulation time 72615679 ps
CPU time 0.85 seconds
Started Aug 27 02:49:29 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037725719 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.1037725719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4291400866
Short name T121
Test name
Test status
Simulation time 243875448 ps
CPU time 1.46 seconds
Started Aug 27 02:49:30 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291400866 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.4291400866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.945377774
Short name T94
Test name
Test status
Simulation time 231248533 ps
CPU time 1.53 seconds
Started Aug 27 02:49:29 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 217704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945377774 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.945377774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3004253756
Short name T133
Test name
Test status
Simulation time 784363868 ps
CPU time 2.73 seconds
Started Aug 27 02:49:29 PM UTC 24
Finished Aug 27 02:49:34 PM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004253756 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.3004253756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2632443293
Short name T571
Test name
Test status
Simulation time 174830617 ps
CPU time 1.53 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2632443293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w
ith_rand_reset.2632443293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1930294325
Short name T577
Test name
Test status
Simulation time 90190987 ps
CPU time 0.78 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:40 PM UTC 24
Peak memory 207572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930294325 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.1930294325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4105069003
Short name T576
Test name
Test status
Simulation time 137748524 ps
CPU time 1.05 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105069003 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.4105069003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3393488077
Short name T570
Test name
Test status
Simulation time 147447744 ps
CPU time 1.81 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 217696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393488077 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3393488077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1680736892
Short name T588
Test name
Test status
Simulation time 496238198 ps
CPU time 1.96 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:42 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680736892 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1680736892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.4001956973
Short name T567
Test name
Test status
Simulation time 184898334 ps
CPU time 1.89 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 217628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4001956973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w
ith_rand_reset.4001956973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2329069542
Short name T123
Test name
Test status
Simulation time 77245717 ps
CPU time 0.73 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329069542 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2329069542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.3768494798
Short name T566
Test name
Test status
Simulation time 196817270 ps
CPU time 1.73 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768494798 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.3768494798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.4090038335
Short name T573
Test name
Test status
Simulation time 280373993 ps
CPU time 1.79 seconds
Started Aug 27 02:49:32 PM UTC 24
Finished Aug 27 02:49:39 PM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090038335 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.4090038335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.863884326
Short name T572
Test name
Test status
Simulation time 878194578 ps
CPU time 2.83 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 208832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863884326 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.863884326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.798709976
Short name T562
Test name
Test status
Simulation time 120113797 ps
CPU time 1.07 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=798709976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_wi
th_rand_reset.798709976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.2198726714
Short name T558
Test name
Test status
Simulation time 76830251 ps
CPU time 0.76 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198726714 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.2198726714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.802091434
Short name T564
Test name
Test status
Simulation time 174872914 ps
CPU time 1.26 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802091434 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.802091434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.3417665105
Short name T124
Test name
Test status
Simulation time 143828548 ps
CPU time 1.93 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 221724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417665105 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.3417665105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1838545809
Short name T565
Test name
Test status
Simulation time 420368359 ps
CPU time 1.67 seconds
Started Aug 27 02:49:34 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838545809 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.1838545809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1454512146
Short name T9
Test name
Test status
Simulation time 1267505879 ps
CPU time 6.74 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:16 PM UTC 24
Peak memory 241612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454512146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.1454512146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1831187814
Short name T8
Test name
Test status
Simulation time 932037903 ps
CPU time 5.29 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:14 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831187814 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1831187814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.3889779957
Short name T5
Test name
Test status
Simulation time 173957068 ps
CPU time 1.42 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:10 PM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889779957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.3889779957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.3800791779
Short name T86
Test name
Test status
Simulation time 8899814689 ps
CPU time 31.01 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:40 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800791779 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3800791779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.4008195457
Short name T6
Test name
Test status
Simulation time 153455579 ps
CPU time 1.91 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:11 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008195457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.4008195457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1483743208
Short name T4
Test name
Test status
Simulation time 135407525 ps
CPU time 1.4 seconds
Started Aug 27 02:47:08 PM UTC 24
Finished Aug 27 02:47:10 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483743208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1483743208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1173964914
Short name T54
Test name
Test status
Simulation time 78771674 ps
CPU time 1.1 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173964914 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1173964914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2609192926
Short name T75
Test name
Test status
Simulation time 301498143 ps
CPU time 1.51 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 237564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609192926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2609192926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3375750160
Short name T11
Test name
Test status
Simulation time 162821428 ps
CPU time 0.84 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375750160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3375750160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.2929681895
Short name T66
Test name
Test status
Simulation time 16575240678 ps
CPU time 25.8 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:50 PM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929681895 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.2929681895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.3255758600
Short name T24
Test name
Test status
Simulation time 145106785 ps
CPU time 1.36 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255758600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3255758600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.817367072
Short name T14
Test name
Test status
Simulation time 201363448 ps
CPU time 1.43 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817367072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.817367072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.3005947500
Short name T37
Test name
Test status
Simulation time 1866592599 ps
CPU time 7.15 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:31 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005947500 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.3005947500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.67383758
Short name T58
Test name
Test status
Simulation time 337190757 ps
CPU time 2.38 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67383758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.67383758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1927293748
Short name T13
Test name
Test status
Simulation time 169370078 ps
CPU time 1.14 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927293748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1927293748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.3209689190
Short name T166
Test name
Test status
Simulation time 76828241 ps
CPU time 1.13 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209689190 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.3209689190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.2710429718
Short name T167
Test name
Test status
Simulation time 323279112 ps
CPU time 1.32 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710429718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.2710429718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.2906612341
Short name T163
Test name
Test status
Simulation time 160115256 ps
CPU time 1.22 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:45 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906612341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2906612341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3576095793
Short name T136
Test name
Test status
Simulation time 2103712349 ps
CPU time 8.59 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576095793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3576095793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.3652445049
Short name T165
Test name
Test status
Simulation time 113284344 ps
CPU time 1.13 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652445049 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.3652445049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.579639965
Short name T164
Test name
Test status
Simulation time 204869016 ps
CPU time 1.53 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:45 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579639965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.579639965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2546538177
Short name T208
Test name
Test status
Simulation time 2233598647 ps
CPU time 9.61 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546538177 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2546538177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.2219940343
Short name T178
Test name
Test status
Simulation time 283284548 ps
CPU time 2.16 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:49 PM UTC 24
Peak memory 208912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219940343 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2219940343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2076398824
Short name T168
Test name
Test status
Simulation time 149993668 ps
CPU time 1.51 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076398824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.2076398824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2700066333
Short name T173
Test name
Test status
Simulation time 73354854 ps
CPU time 1.02 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700066333 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2700066333
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.784835656
Short name T29
Test name
Test status
Simulation time 2271839305 ps
CPU time 8.53 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:56 PM UTC 24
Peak memory 242468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784835656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.784835656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3853456376
Short name T175
Test name
Test status
Simulation time 301946060 ps
CPU time 1.54 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:49 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853456376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.3853456376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3287728458
Short name T169
Test name
Test status
Simulation time 110566663 ps
CPU time 1.26 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287728458 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3287728458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3103561162
Short name T195
Test name
Test status
Simulation time 1616917599 ps
CPU time 6.94 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:54 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103561162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.3103561162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.3495485689
Short name T171
Test name
Test status
Simulation time 109707618 ps
CPU time 1.29 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495485689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.3495485689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.4052038563
Short name T172
Test name
Test status
Simulation time 201114075 ps
CPU time 1.5 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052038563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4052038563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.2789609470
Short name T223
Test name
Test status
Simulation time 3564758662 ps
CPU time 13.98 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:48:01 PM UTC 24
Peak memory 209300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789609470 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2789609470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.2619728301
Short name T176
Test name
Test status
Simulation time 139315281 ps
CPU time 1.73 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:49 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619728301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2619728301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.2243437846
Short name T174
Test name
Test status
Simulation time 113361746 ps
CPU time 1.32 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243437846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.2243437846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.2158433770
Short name T180
Test name
Test status
Simulation time 73984834 ps
CPU time 0.85 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:51 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158433770 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2158433770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3946500176
Short name T30
Test name
Test status
Simulation time 1950913100 ps
CPU time 6.83 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946500176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3946500176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3876994893
Short name T181
Test name
Test status
Simulation time 302783976 ps
CPU time 1.38 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:51 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876994893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3876994893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.2516372621
Short name T170
Test name
Test status
Simulation time 107695965 ps
CPU time 1.02 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516372621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.2516372621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3674546053
Short name T112
Test name
Test status
Simulation time 1730882116 ps
CPU time 5.8 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:53 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674546053 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.3674546053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1875102483
Short name T179
Test name
Test status
Simulation time 114611433 ps
CPU time 1.1 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:51 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875102483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1875102483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.603143321
Short name T177
Test name
Test status
Simulation time 244784354 ps
CPU time 1.48 seconds
Started Aug 27 02:47:46 PM UTC 24
Finished Aug 27 02:47:49 PM UTC 24
Peak memory 208316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603143321 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.603143321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.3116856509
Short name T268
Test name
Test status
Simulation time 5591915041 ps
CPU time 18.79 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:48:09 PM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116856509 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.3116856509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.635228074
Short name T190
Test name
Test status
Simulation time 147118097 ps
CPU time 2.23 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:53 PM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635228074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.635228074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.3413205991
Short name T182
Test name
Test status
Simulation time 204527849 ps
CPU time 1.61 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:51 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413205991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3413205991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2257538040
Short name T192
Test name
Test status
Simulation time 69897749 ps
CPU time 1.01 seconds
Started Aug 27 02:47:51 PM UTC 24
Finished Aug 27 02:47:53 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257538040 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2257538040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.2622520911
Short name T31
Test name
Test status
Simulation time 1955720660 ps
CPU time 7.4 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:58 PM UTC 24
Peak memory 241908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622520911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.2622520911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.15547503
Short name T185
Test name
Test status
Simulation time 301487870 ps
CPU time 1.37 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15547503 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.15547503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2788699429
Short name T183
Test name
Test status
Simulation time 102578647 ps
CPU time 1.14 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788699429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2788699429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.763373285
Short name T211
Test name
Test status
Simulation time 1824053338 ps
CPU time 6.95 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763373285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.763373285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.4242332072
Short name T186
Test name
Test status
Simulation time 101026774 ps
CPU time 1.42 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242332072 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.4242332072
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.1132215645
Short name T187
Test name
Test status
Simulation time 191988851 ps
CPU time 1.68 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132215645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1132215645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.1281381409
Short name T189
Test name
Test status
Simulation time 399612584 ps
CPU time 1.93 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:53 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281381409 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1281381409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3143638499
Short name T188
Test name
Test status
Simulation time 271328869 ps
CPU time 1.73 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143638499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.3143638499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2551421267
Short name T184
Test name
Test status
Simulation time 67610663 ps
CPU time 1.1 seconds
Started Aug 27 02:47:49 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551421267 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2551421267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.4239251467
Short name T197
Test name
Test status
Simulation time 68488877 ps
CPU time 1.07 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239251467 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4239251467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.3775879422
Short name T47
Test name
Test status
Simulation time 1275785892 ps
CPU time 5.85 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:59 PM UTC 24
Peak memory 241240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775879422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3775879422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.18703434
Short name T198
Test name
Test status
Simulation time 301154806 ps
CPU time 1.28 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18703434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.18703434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.1803255134
Short name T191
Test name
Test status
Simulation time 188246017 ps
CPU time 0.96 seconds
Started Aug 27 02:47:51 PM UTC 24
Finished Aug 27 02:47:53 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803255134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1803255134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1776575679
Short name T209
Test name
Test status
Simulation time 1026874353 ps
CPU time 4.58 seconds
Started Aug 27 02:47:51 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776575679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1776575679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3909720528
Short name T199
Test name
Test status
Simulation time 142164134 ps
CPU time 1.32 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909720528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3909720528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.3241895258
Short name T194
Test name
Test status
Simulation time 199193988 ps
CPU time 1.47 seconds
Started Aug 27 02:47:51 PM UTC 24
Finished Aug 27 02:47:54 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241895258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.3241895258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.2103229697
Short name T425
Test name
Test status
Simulation time 14947065107 ps
CPU time 46.46 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:48:41 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103229697 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2103229697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.3666737414
Short name T202
Test name
Test status
Simulation time 128904353 ps
CPU time 2.03 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:56 PM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666737414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.3666737414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.40342045
Short name T193
Test name
Test status
Simulation time 154233158 ps
CPU time 1.31 seconds
Started Aug 27 02:47:51 PM UTC 24
Finished Aug 27 02:47:54 PM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40342045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.40342045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2684543551
Short name T204
Test name
Test status
Simulation time 59786811 ps
CPU time 1.05 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:56 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684543551 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2684543551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.1000206684
Short name T32
Test name
Test status
Simulation time 1969417244 ps
CPU time 7.45 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000206684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1000206684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.36455109
Short name T205
Test name
Test status
Simulation time 301319534 ps
CPU time 1.15 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:56 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36455109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.36455109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.1903312709
Short name T196
Test name
Test status
Simulation time 95654558 ps
CPU time 1.07 seconds
Started Aug 27 02:47:53 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 207948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903312709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.1903312709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1498416448
Short name T108
Test name
Test status
Simulation time 1442288789 ps
CPU time 6.29 seconds
Started Aug 27 02:47:53 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498416448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1498416448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.948801400
Short name T203
Test name
Test status
Simulation time 99527145 ps
CPU time 1.12 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:56 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948801400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.948801400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.4030799396
Short name T200
Test name
Test status
Simulation time 183822442 ps
CPU time 1.4 seconds
Started Aug 27 02:47:52 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030799396 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.4030799396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1332348520
Short name T259
Test name
Test status
Simulation time 3101170787 ps
CPU time 12.73 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332348520 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1332348520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.144827739
Short name T206
Test name
Test status
Simulation time 124196377 ps
CPU time 1.48 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144827739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.144827739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.1155561373
Short name T201
Test name
Test status
Simulation time 264613088 ps
CPU time 1.52 seconds
Started Aug 27 02:47:53 PM UTC 24
Finished Aug 27 02:47:55 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155561373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1155561373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.1824340535
Short name T212
Test name
Test status
Simulation time 81576069 ps
CPU time 0.76 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:47:59 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824340535 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1824340535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.602062437
Short name T33
Test name
Test status
Simulation time 1962456749 ps
CPU time 6.68 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 241296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602062437 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.602062437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.508948634
Short name T215
Test name
Test status
Simulation time 301448315 ps
CPU time 1.23 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 237684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508948634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.508948634
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2605560659
Short name T207
Test name
Test status
Simulation time 182865694 ps
CPU time 0.89 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605560659 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2605560659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.2376152571
Short name T111
Test name
Test status
Simulation time 833952061 ps
CPU time 4.3 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376152571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.2376152571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.408673514
Short name T216
Test name
Test status
Simulation time 178362229 ps
CPU time 1.21 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408673514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.408673514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.1217862361
Short name T210
Test name
Test status
Simulation time 125025294 ps
CPU time 1.62 seconds
Started Aug 27 02:47:54 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217862361 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.1217862361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3490735206
Short name T347
Test name
Test status
Simulation time 9157389799 ps
CPU time 29.12 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490735206 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3490735206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.1879977851
Short name T222
Test name
Test status
Simulation time 295362247 ps
CPU time 2.43 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:01 PM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879977851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.1879977851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.2730791442
Short name T217
Test name
Test status
Simulation time 180192598 ps
CPU time 1.29 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730791442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2730791442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.3050648520
Short name T224
Test name
Test status
Simulation time 67326529 ps
CPU time 0.71 seconds
Started Aug 27 02:48:00 PM UTC 24
Finished Aug 27 02:48:02 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050648520 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3050648520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.983659451
Short name T48
Test name
Test status
Simulation time 2452795739 ps
CPU time 7.82 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 241732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983659451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.983659451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1916138061
Short name T228
Test name
Test status
Simulation time 301078624 ps
CPU time 1.19 seconds
Started Aug 27 02:48:00 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 237688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916138061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1916138061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.3178350350
Short name T214
Test name
Test status
Simulation time 87860074 ps
CPU time 0.87 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:47:59 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178350350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3178350350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.3930784499
Short name T238
Test name
Test status
Simulation time 1485335616 ps
CPU time 5.1 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:04 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930784499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.3930784499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3102735211
Short name T219
Test name
Test status
Simulation time 185947133 ps
CPU time 1.2 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102735211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3102735211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.1273940
Short name T220
Test name
Test status
Simulation time 206028585 ps
CPU time 1.5 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273940 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1273940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.3495797987
Short name T340
Test name
Test status
Simulation time 5626790870 ps
CPU time 25.04 seconds
Started Aug 27 02:48:00 PM UTC 24
Finished Aug 27 02:48:27 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495797987 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.3495797987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.2331130685
Short name T221
Test name
Test status
Simulation time 156791369 ps
CPU time 2.06 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:01 PM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331130685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2331130685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.3961463737
Short name T218
Test name
Test status
Simulation time 175828236 ps
CPU time 1.25 seconds
Started Aug 27 02:47:57 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961463737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3961463737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.2406997781
Short name T229
Test name
Test status
Simulation time 70946560 ps
CPU time 0.8 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406997781 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.2406997781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.2853216425
Short name T34
Test name
Test status
Simulation time 1268078739 ps
CPU time 5.7 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 242040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853216425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2853216425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1055641169
Short name T234
Test name
Test status
Simulation time 302400239 ps
CPU time 1.26 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055641169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1055641169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.3709163761
Short name T227
Test name
Test status
Simulation time 166076829 ps
CPU time 0.93 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709163761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.3709163761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1163588039
Short name T257
Test name
Test status
Simulation time 1470965547 ps
CPU time 5.7 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163588039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1163588039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2921399825
Short name T230
Test name
Test status
Simulation time 161742947 ps
CPU time 1.14 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921399825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2921399825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.1162912852
Short name T232
Test name
Test status
Simulation time 127616120 ps
CPU time 1.29 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162912852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.1162912852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.4137106241
Short name T507
Test name
Test status
Simulation time 15735148896 ps
CPU time 54.22 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:57 PM UTC 24
Peak memory 218068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137106241 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.4137106241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.1303180467
Short name T243
Test name
Test status
Simulation time 568376466 ps
CPU time 2.66 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303180467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1303180467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.1255736221
Short name T226
Test name
Test status
Simulation time 94361563 ps
CPU time 0.85 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255736221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1255736221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.2735396882
Short name T233
Test name
Test status
Simulation time 69779959 ps
CPU time 0.73 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735396882 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.2735396882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.1446220192
Short name T270
Test name
Test status
Simulation time 1979721030 ps
CPU time 7.59 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:10 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446220192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1446220192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.3780876757
Short name T236
Test name
Test status
Simulation time 301405605 ps
CPU time 1.09 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:04 PM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780876757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.3780876757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.693658988
Short name T231
Test name
Test status
Simulation time 132658396 ps
CPU time 0.88 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693658988 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.693658988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.450545590
Short name T253
Test name
Test status
Simulation time 895241187 ps
CPU time 4.33 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 209372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450545590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.450545590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.887215241
Short name T239
Test name
Test status
Simulation time 164109213 ps
CPU time 1.27 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:04 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887215241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.887215241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.1255063844
Short name T237
Test name
Test status
Simulation time 199157395 ps
CPU time 1.32 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:04 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255063844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.1255063844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.1416472573
Short name T346
Test name
Test status
Simulation time 5925327701 ps
CPU time 25.02 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416472573 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.1416472573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3074377025
Short name T246
Test name
Test status
Simulation time 155872589 ps
CPU time 2.55 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074377025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3074377025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.2412953544
Short name T235
Test name
Test status
Simulation time 157148561 ps
CPU time 1.09 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:03 PM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412953544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2412953544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2643886018
Short name T72
Test name
Test status
Simulation time 75911178 ps
CPU time 0.84 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643886018 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2643886018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.353819613
Short name T26
Test name
Test status
Simulation time 1274123255 ps
CPU time 5.74 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:30 PM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353819613 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.353819613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3017079029
Short name T78
Test name
Test status
Simulation time 301533406 ps
CPU time 1.41 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017079029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3017079029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.306228255
Short name T16
Test name
Test status
Simulation time 82577501 ps
CPU time 1.02 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:25 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306228255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.306228255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.3717070268
Short name T36
Test name
Test status
Simulation time 1609425427 ps
CPU time 6.6 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:31 PM UTC 24
Peak memory 209244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717070268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3717070268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.4163197429
Short name T74
Test name
Test status
Simulation time 22714247211 ps
CPU time 35.25 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:48:00 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163197429 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.4163197429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.2319727260
Short name T65
Test name
Test status
Simulation time 261863286 ps
CPU time 1.59 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319727260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2319727260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.2536950326
Short name T135
Test name
Test status
Simulation time 7533959988 ps
CPU time 26.76 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:52 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536950326 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.2536950326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.238128955
Short name T79
Test name
Test status
Simulation time 100952091 ps
CPU time 1.29 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238128955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.238128955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.4272402980
Short name T248
Test name
Test status
Simulation time 70857104 ps
CPU time 0.86 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:06 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272402980 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.4272402980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.3780372794
Short name T35
Test name
Test status
Simulation time 1266746559 ps
CPU time 5.75 seconds
Started Aug 27 02:48:03 PM UTC 24
Finished Aug 27 02:48:09 PM UTC 24
Peak memory 241608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780372794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3780372794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.757949663
Short name T245
Test name
Test status
Simulation time 302661788 ps
CPU time 1.05 seconds
Started Aug 27 02:48:03 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757949663 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.757949663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.446065369
Short name T241
Test name
Test status
Simulation time 196409761 ps
CPU time 1.04 seconds
Started Aug 27 02:48:02 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 208080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446065369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.446065369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.2819001847
Short name T260
Test name
Test status
Simulation time 909945102 ps
CPU time 4.42 seconds
Started Aug 27 02:48:02 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 209384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819001847 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.2819001847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2544254822
Short name T244
Test name
Test status
Simulation time 138194787 ps
CPU time 1.21 seconds
Started Aug 27 02:48:03 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544254822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2544254822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.3614506982
Short name T240
Test name
Test status
Simulation time 256749458 ps
CPU time 1.56 seconds
Started Aug 27 02:48:01 PM UTC 24
Finished Aug 27 02:48:04 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614506982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.3614506982
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.750873663
Short name T321
Test name
Test status
Simulation time 5059939375 ps
CPU time 16.33 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:21 PM UTC 24
Peak memory 218164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750873663 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.750873663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.4260151144
Short name T247
Test name
Test status
Simulation time 126406360 ps
CPU time 1.87 seconds
Started Aug 27 02:48:02 PM UTC 24
Finished Aug 27 02:48:06 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260151144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.4260151144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.2985225408
Short name T242
Test name
Test status
Simulation time 92078464 ps
CPU time 1.19 seconds
Started Aug 27 02:48:02 PM UTC 24
Finished Aug 27 02:48:05 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985225408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2985225408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3713890226
Short name T251
Test name
Test status
Simulation time 75576437 ps
CPU time 0.88 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:06 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713890226 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3713890226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.1138989709
Short name T49
Test name
Test status
Simulation time 1278032058 ps
CPU time 6.12 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:11 PM UTC 24
Peak memory 242376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138989709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1138989709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1240337449
Short name T255
Test name
Test status
Simulation time 302359344 ps
CPU time 1.84 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240337449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1240337449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.1876177235
Short name T250
Test name
Test status
Simulation time 97278131 ps
CPU time 1.19 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:06 PM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876177235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.1876177235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.119554127
Short name T269
Test name
Test status
Simulation time 803417103 ps
CPU time 4.36 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:10 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119554127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.119554127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3089599556
Short name T249
Test name
Test status
Simulation time 97577336 ps
CPU time 0.93 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:06 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089599556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3089599556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2664914089
Short name T252
Test name
Test status
Simulation time 234165653 ps
CPU time 1.55 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664914089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2664914089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.2648176314
Short name T333
Test name
Test status
Simulation time 5277784781 ps
CPU time 19.74 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648176314 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.2648176314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2809135112
Short name T256
Test name
Test status
Simulation time 400409661 ps
CPU time 2.26 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809135112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2809135112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.3518326732
Short name T254
Test name
Test status
Simulation time 231282116 ps
CPU time 1.59 seconds
Started Aug 27 02:48:04 PM UTC 24
Finished Aug 27 02:48:07 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518326732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.3518326732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.1815857188
Short name T262
Test name
Test status
Simulation time 84822043 ps
CPU time 1.15 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815857188 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.1815857188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.4289657641
Short name T51
Test name
Test status
Simulation time 1283997616 ps
CPU time 5.25 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289657641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.4289657641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1194866044
Short name T267
Test name
Test status
Simulation time 302200335 ps
CPU time 1.8 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:09 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194866044 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1194866044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2861737103
Short name T258
Test name
Test status
Simulation time 169526600 ps
CPU time 1.02 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861737103 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2861737103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.2103319884
Short name T283
Test name
Test status
Simulation time 1547495120 ps
CPU time 5.42 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103319884 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.2103319884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.3834980924
Short name T261
Test name
Test status
Simulation time 111700641 ps
CPU time 1.31 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834980924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.3834980924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.485319900
Short name T264
Test name
Test status
Simulation time 201583538 ps
CPU time 1.55 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485319900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.485319900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.2600487932
Short name T429
Test name
Test status
Simulation time 11543003456 ps
CPU time 34.58 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:42 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600487932 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.2600487932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.968621888
Short name T266
Test name
Test status
Simulation time 138863202 ps
CPU time 1.56 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968621888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.968621888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.3571778427
Short name T263
Test name
Test status
Simulation time 218747611 ps
CPU time 1.43 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571778427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.3571778427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.1349032202
Short name T277
Test name
Test status
Simulation time 92414562 ps
CPU time 1.1 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349032202 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.1349032202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.3432654123
Short name T52
Test name
Test status
Simulation time 1266460790 ps
CPU time 5.84 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432654123 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3432654123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1357883962
Short name T276
Test name
Test status
Simulation time 301654491 ps
CPU time 1.18 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357883962 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1357883962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.655799588
Short name T271
Test name
Test status
Simulation time 169982041 ps
CPU time 0.83 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:11 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655799588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.655799588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.3203844677
Short name T295
Test name
Test status
Simulation time 851825574 ps
CPU time 4.68 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 209156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203844677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.3203844677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.2995178548
Short name T279
Test name
Test status
Simulation time 170360384 ps
CPU time 1.52 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995178548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.2995178548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.2272796285
Short name T265
Test name
Test status
Simulation time 123119724 ps
CPU time 1.38 seconds
Started Aug 27 02:48:06 PM UTC 24
Finished Aug 27 02:48:08 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272796285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.2272796285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3840943132
Short name T297
Test name
Test status
Simulation time 952790267 ps
CPU time 4.72 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840943132 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3840943132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.1405464252
Short name T275
Test name
Test status
Simulation time 109698788 ps
CPU time 1.37 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405464252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1405464252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.3300589573
Short name T274
Test name
Test status
Simulation time 149189362 ps
CPU time 1.22 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300589573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.3300589573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.136470225
Short name T280
Test name
Test status
Simulation time 77329661 ps
CPU time 0.84 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136470225 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.136470225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.1816515942
Short name T306
Test name
Test status
Simulation time 1267207605 ps
CPU time 5.35 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 242340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816515942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.1816515942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1094558522
Short name T282
Test name
Test status
Simulation time 302209484 ps
CPU time 1.36 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094558522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1094558522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.1539852238
Short name T273
Test name
Test status
Simulation time 130208284 ps
CPU time 0.85 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:11 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539852238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1539852238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.477891453
Short name T300
Test name
Test status
Simulation time 1256658321 ps
CPU time 4.87 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477891453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.477891453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.667814199
Short name T284
Test name
Test status
Simulation time 142458345 ps
CPU time 1.52 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667814199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.667814199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.2860159980
Short name T278
Test name
Test status
Simulation time 128275021 ps
CPU time 1.15 seconds
Started Aug 27 02:48:09 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860159980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.2860159980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.530824015
Short name T292
Test name
Test status
Simulation time 854696816 ps
CPU time 3.74 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530824015 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.530824015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.1223494196
Short name T225
Test name
Test status
Simulation time 536192916 ps
CPU time 3.14 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:14 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223494196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.1223494196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.348049316
Short name T272
Test name
Test status
Simulation time 59198819 ps
CPU time 0.69 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:11 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348049316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.348049316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.2566231520
Short name T289
Test name
Test status
Simulation time 61605309 ps
CPU time 1.12 seconds
Started Aug 27 02:48:11 PM UTC 24
Finished Aug 27 02:48:14 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566231520 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.2566231520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.42176775
Short name T318
Test name
Test status
Simulation time 2438876976 ps
CPU time 7.75 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:19 PM UTC 24
Peak memory 242304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42176775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.42176775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2255394366
Short name T290
Test name
Test status
Simulation time 301982609 ps
CPU time 1.26 seconds
Started Aug 27 02:48:11 PM UTC 24
Finished Aug 27 02:48:14 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255394366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2255394366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.1844275996
Short name T281
Test name
Test status
Simulation time 199533281 ps
CPU time 0.9 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844275996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.1844275996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1445679236
Short name T315
Test name
Test status
Simulation time 1499336904 ps
CPU time 6.91 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:18 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445679236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1445679236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1725601542
Short name T287
Test name
Test status
Simulation time 160607671 ps
CPU time 1.27 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:13 PM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725601542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1725601542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2445059454
Short name T286
Test name
Test status
Simulation time 125788453 ps
CPU time 1.32 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445059454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2445059454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.3780312207
Short name T496
Test name
Test status
Simulation time 9776739600 ps
CPU time 38.12 seconds
Started Aug 27 02:48:11 PM UTC 24
Finished Aug 27 02:48:51 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780312207 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.3780312207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3332102425
Short name T288
Test name
Test status
Simulation time 401441462 ps
CPU time 2.2 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:14 PM UTC 24
Peak memory 208864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332102425 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3332102425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.1654408510
Short name T285
Test name
Test status
Simulation time 79782170 ps
CPU time 0.95 seconds
Started Aug 27 02:48:10 PM UTC 24
Finished Aug 27 02:48:12 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654408510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.1654408510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.4080275817
Short name T298
Test name
Test status
Simulation time 73913205 ps
CPU time 1.15 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080275817 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.4080275817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2194657454
Short name T50
Test name
Test status
Simulation time 2441967667 ps
CPU time 7.67 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:22 PM UTC 24
Peak memory 242240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194657454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2194657454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.1082285719
Short name T301
Test name
Test status
Simulation time 301787115 ps
CPU time 1.67 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 237440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082285719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.1082285719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.2002964815
Short name T294
Test name
Test status
Simulation time 202955544 ps
CPU time 1.13 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002964815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.2002964815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.4029505901
Short name T316
Test name
Test status
Simulation time 1020708625 ps
CPU time 4.7 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:19 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029505901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.4029505901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.28378590
Short name T296
Test name
Test status
Simulation time 152362942 ps
CPU time 1.16 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28378590 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.28378590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.782607712
Short name T291
Test name
Test status
Simulation time 111867991 ps
CPU time 1.49 seconds
Started Aug 27 02:48:11 PM UTC 24
Finished Aug 27 02:48:14 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782607712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.782607712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.471891219
Short name T341
Test name
Test status
Simulation time 3364683861 ps
CPU time 13.27 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 218076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471891219 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.471891219
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.1140070149
Short name T304
Test name
Test status
Simulation time 116982913 ps
CPU time 2.03 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140070149 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.1140070149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.1449488066
Short name T293
Test name
Test status
Simulation time 88484020 ps
CPU time 0.91 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449488066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.1449488066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.2270347929
Short name T305
Test name
Test status
Simulation time 63946582 ps
CPU time 0.82 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270347929 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2270347929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.2684379314
Short name T322
Test name
Test status
Simulation time 1973301353 ps
CPU time 7.03 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:23 PM UTC 24
Peak memory 241344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684379314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.2684379314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2961758344
Short name T308
Test name
Test status
Simulation time 301749339 ps
CPU time 1.27 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:17 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961758344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2961758344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.3485290353
Short name T299
Test name
Test status
Simulation time 158647132 ps
CPU time 1.22 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:15 PM UTC 24
Peak memory 207688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485290353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.3485290353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.3839026190
Short name T320
Test name
Test status
Simulation time 2072966375 ps
CPU time 6.81 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:21 PM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839026190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.3839026190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2757224124
Short name T307
Test name
Test status
Simulation time 104534956 ps
CPU time 1.16 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:17 PM UTC 24
Peak memory 207836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757224124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2757224124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.2364849674
Short name T302
Test name
Test status
Simulation time 120276598 ps
CPU time 1.57 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364849674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.2364849674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.2082118699
Short name T389
Test name
Test status
Simulation time 4590438347 ps
CPU time 18.22 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 209308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082118699 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.2082118699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.149075159
Short name T310
Test name
Test status
Simulation time 124739858 ps
CPU time 1.59 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:17 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149075159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.149075159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.1218203166
Short name T303
Test name
Test status
Simulation time 191027821 ps
CPU time 1.5 seconds
Started Aug 27 02:48:13 PM UTC 24
Finished Aug 27 02:48:16 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218203166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1218203166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.2327568509
Short name T324
Test name
Test status
Simulation time 109944304 ps
CPU time 0.86 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:24 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327568509 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2327568509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.2722739192
Short name T53
Test name
Test status
Simulation time 1270038210 ps
CPU time 5.1 seconds
Started Aug 27 02:48:16 PM UTC 24
Finished Aug 27 02:48:22 PM UTC 24
Peak memory 241940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722739192 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.2722739192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.773279688
Short name T313
Test name
Test status
Simulation time 306618484 ps
CPU time 1.18 seconds
Started Aug 27 02:48:16 PM UTC 24
Finished Aug 27 02:48:18 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773279688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.773279688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.3817317648
Short name T314
Test name
Test status
Simulation time 224481824 ps
CPU time 1.52 seconds
Started Aug 27 02:48:15 PM UTC 24
Finished Aug 27 02:48:18 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817317648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3817317648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.170498190
Short name T319
Test name
Test status
Simulation time 912948748 ps
CPU time 4.23 seconds
Started Aug 27 02:48:15 PM UTC 24
Finished Aug 27 02:48:21 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170498190 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.170498190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.4231910831
Short name T312
Test name
Test status
Simulation time 111201587 ps
CPU time 0.97 seconds
Started Aug 27 02:48:16 PM UTC 24
Finished Aug 27 02:48:18 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231910831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.4231910831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.1329916387
Short name T309
Test name
Test status
Simulation time 117999349 ps
CPU time 1.19 seconds
Started Aug 27 02:48:14 PM UTC 24
Finished Aug 27 02:48:17 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329916387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1329916387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.1497596939
Short name T502
Test name
Test status
Simulation time 6791580310 ps
CPU time 29.23 seconds
Started Aug 27 02:48:22 PM UTC 24
Finished Aug 27 02:48:53 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497596939 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.1497596939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.1287858327
Short name T317
Test name
Test status
Simulation time 389406485 ps
CPU time 2.21 seconds
Started Aug 27 02:48:15 PM UTC 24
Finished Aug 27 02:48:19 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287858327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1287858327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.1192543685
Short name T311
Test name
Test status
Simulation time 88492038 ps
CPU time 0.9 seconds
Started Aug 27 02:48:15 PM UTC 24
Finished Aug 27 02:48:18 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192543685 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1192543685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.185669960
Short name T327
Test name
Test status
Simulation time 75743476 ps
CPU time 0.79 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185669960 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.185669960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.749203260
Short name T359
Test name
Test status
Simulation time 1278208774 ps
CPU time 5.21 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 242104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749203260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.749203260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.1558459475
Short name T337
Test name
Test status
Simulation time 302404651 ps
CPU time 1.6 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 237284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558459475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.1558459475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.908943610
Short name T325
Test name
Test status
Simulation time 208408515 ps
CPU time 0.95 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908943610 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.908943610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.178824915
Short name T362
Test name
Test status
Simulation time 1549003373 ps
CPU time 5.63 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 209272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178824915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.178824915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3004683222
Short name T328
Test name
Test status
Simulation time 151109305 ps
CPU time 1.02 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004683222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3004683222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.626192937
Short name T330
Test name
Test status
Simulation time 128314207 ps
CPU time 1.25 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626192937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.626192937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.2558792410
Short name T477
Test name
Test status
Simulation time 6413131659 ps
CPU time 24.19 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:48 PM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558792410 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.2558792410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.3296802008
Short name T338
Test name
Test status
Simulation time 143985239 ps
CPU time 2.16 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:26 PM UTC 24
Peak memory 208936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296802008 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3296802008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.3941803059
Short name T331
Test name
Test status
Simulation time 153163106 ps
CPU time 1.17 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941803059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.3941803059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.2556732165
Short name T42
Test name
Test status
Simulation time 72869650 ps
CPU time 1.18 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556732165 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2556732165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.70739722
Short name T45
Test name
Test status
Simulation time 1965166647 ps
CPU time 6.75 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 241344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70739722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.70739722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.3954004127
Short name T145
Test name
Test status
Simulation time 301916801 ps
CPU time 1.77 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954004127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.3954004127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3198807725
Short name T17
Test name
Test status
Simulation time 85119755 ps
CPU time 1.04 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198807725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.3198807725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3363341553
Short name T67
Test name
Test status
Simulation time 16645034876 ps
CPU time 25.01 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 242336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363341553 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3363341553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3727129905
Short name T40
Test name
Test status
Simulation time 106482921 ps
CPU time 1.13 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727129905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3727129905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2614582859
Short name T76
Test name
Test status
Simulation time 115193633 ps
CPU time 1.22 seconds
Started Aug 27 02:47:23 PM UTC 24
Finished Aug 27 02:47:26 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614582859 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2614582859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.3863798440
Short name T105
Test name
Test status
Simulation time 2741217465 ps
CPU time 11.96 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:44 PM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863798440 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3863798440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3390850116
Short name T80
Test name
Test status
Simulation time 138906635 ps
CPU time 1.66 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390850116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3390850116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3698123498
Short name T38
Test name
Test status
Simulation time 89914427 ps
CPU time 0.81 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:32 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698123498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.3698123498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.3431606996
Short name T342
Test name
Test status
Simulation time 72373090 ps
CPU time 0.86 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431606996 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.3431606996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.2625065606
Short name T376
Test name
Test status
Simulation time 2257554941 ps
CPU time 8.07 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 242468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625065606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2625065606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.2911660210
Short name T334
Test name
Test status
Simulation time 301616835 ps
CPU time 1.09 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911660210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.2911660210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2919065565
Short name T329
Test name
Test status
Simulation time 161030289 ps
CPU time 0.94 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919065565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2919065565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.3523163440
Short name T365
Test name
Test status
Simulation time 2010677428 ps
CPU time 6.68 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:31 PM UTC 24
Peak memory 209108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523163440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.3523163440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.2320709900
Short name T335
Test name
Test status
Simulation time 153870196 ps
CPU time 1.26 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320709900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.2320709900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.1744572627
Short name T336
Test name
Test status
Simulation time 254444241 ps
CPU time 1.5 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744572627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.1744572627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.3433558875
Short name T372
Test name
Test status
Simulation time 2087340540 ps
CPU time 7.68 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433558875 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3433558875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.4223633329
Short name T339
Test name
Test status
Simulation time 309333746 ps
CPU time 1.91 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:26 PM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223633329 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4223633329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.852245570
Short name T332
Test name
Test status
Simulation time 122788033 ps
CPU time 0.86 seconds
Started Aug 27 02:48:23 PM UTC 24
Finished Aug 27 02:48:25 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852245570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.852245570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.500143779
Short name T349
Test name
Test status
Simulation time 80564587 ps
CPU time 1.18 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500143779 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.500143779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.3038051255
Short name T381
Test name
Test status
Simulation time 1273289591 ps
CPU time 5.96 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 241696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038051255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.3038051255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.2716115912
Short name T350
Test name
Test status
Simulation time 301869196 ps
CPU time 1.33 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716115912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.2716115912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.946189769
Short name T344
Test name
Test status
Simulation time 89660576 ps
CPU time 0.84 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946189769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.946189769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.3986483869
Short name T367
Test name
Test status
Simulation time 847874164 ps
CPU time 4.22 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:31 PM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986483869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.3986483869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.2086078259
Short name T352
Test name
Test status
Simulation time 106987652 ps
CPU time 1.4 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086078259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.2086078259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.3547834894
Short name T348
Test name
Test status
Simulation time 257119497 ps
CPU time 1.4 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:28 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547834894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.3547834894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.2361958376
Short name T458
Test name
Test status
Simulation time 5405573459 ps
CPU time 18.19 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:46 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361958376 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.2361958376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.3322286268
Short name T363
Test name
Test status
Simulation time 524372498 ps
CPU time 2.7 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:30 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322286268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3322286268
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.1919203713
Short name T356
Test name
Test status
Simulation time 146399682 ps
CPU time 1.59 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919203713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.1919203713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.3730762149
Short name T355
Test name
Test status
Simulation time 66696379 ps
CPU time 0.98 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730762149 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3730762149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.2111438371
Short name T393
Test name
Test status
Simulation time 1979628950 ps
CPU time 7.26 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 241664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111438371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.2111438371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.1202881207
Short name T361
Test name
Test status
Simulation time 302781830 ps
CPU time 1.77 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202881207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.1202881207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.1561231882
Short name T357
Test name
Test status
Simulation time 221953827 ps
CPU time 1.45 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561231882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.1561231882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1110122100
Short name T384
Test name
Test status
Simulation time 1755637480 ps
CPU time 6.02 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110122100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1110122100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.2152370975
Short name T351
Test name
Test status
Simulation time 142445232 ps
CPU time 1.03 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152370975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.2152370975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2625858991
Short name T353
Test name
Test status
Simulation time 193777979 ps
CPU time 1.38 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625858991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2625858991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.3468462930
Short name T388
Test name
Test status
Simulation time 1685303726 ps
CPU time 6.18 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468462930 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3468462930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.3042271139
Short name T364
Test name
Test status
Simulation time 363001902 ps
CPU time 3.09 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:31 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042271139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3042271139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.2769399020
Short name T358
Test name
Test status
Simulation time 212523812 ps
CPU time 1.43 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769399020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.2769399020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.800251293
Short name T370
Test name
Test status
Simulation time 72188399 ps
CPU time 1.07 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800251293 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.800251293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.2112758074
Short name T401
Test name
Test status
Simulation time 1275589037 ps
CPU time 5.89 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:36 PM UTC 24
Peak memory 241656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112758074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2112758074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1117549270
Short name T373
Test name
Test status
Simulation time 302494080 ps
CPU time 1.58 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117549270 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1117549270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.1537563638
Short name T354
Test name
Test status
Simulation time 198564697 ps
CPU time 0.92 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537563638 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.1537563638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.3297829319
Short name T387
Test name
Test status
Simulation time 1528994102 ps
CPU time 6.06 seconds
Started Aug 27 02:48:27 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297829319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.3297829319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.3715045913
Short name T371
Test name
Test status
Simulation time 179538857 ps
CPU time 1.3 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715045913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.3715045913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.93851725
Short name T360
Test name
Test status
Simulation time 193826434 ps
CPU time 1.43 seconds
Started Aug 27 02:48:26 PM UTC 24
Finished Aug 27 02:48:29 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93851725 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.93851725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.406175377
Short name T490
Test name
Test status
Simulation time 4553851730 ps
CPU time 19.45 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406175377 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.406175377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.802237211
Short name T378
Test name
Test status
Simulation time 317732634 ps
CPU time 2.2 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802237211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.802237211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.1412696525
Short name T369
Test name
Test status
Simulation time 142658626 ps
CPU time 1.12 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:31 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412696525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1412696525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3290169985
Short name T323
Test name
Test status
Simulation time 76990915 ps
CPU time 0.84 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290169985 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3290169985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.802711720
Short name T406
Test name
Test status
Simulation time 2469379746 ps
CPU time 8.27 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 242472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802711720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.802711720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3832215134
Short name T379
Test name
Test status
Simulation time 301821657 ps
CPU time 1.72 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832215134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3832215134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1060022823
Short name T326
Test name
Test status
Simulation time 151000206 ps
CPU time 1.17 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060022823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1060022823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.4170759468
Short name T402
Test name
Test status
Simulation time 1433783458 ps
CPU time 6.54 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:37 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170759468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.4170759468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1924917189
Short name T375
Test name
Test status
Simulation time 160412984 ps
CPU time 1.56 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924917189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1924917189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.386508228
Short name T377
Test name
Test status
Simulation time 252073827 ps
CPU time 1.99 seconds
Started Aug 27 02:48:29 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386508228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.386508228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.3646290701
Short name T493
Test name
Test status
Simulation time 5281112895 ps
CPU time 19.36 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646290701 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3646290701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.418222681
Short name T368
Test name
Test status
Simulation time 273068808 ps
CPU time 1.69 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 207856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418222681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.418222681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.2121108830
Short name T366
Test name
Test status
Simulation time 76540968 ps
CPU time 1.08 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121108830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2121108830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.536754191
Short name T382
Test name
Test status
Simulation time 60161575 ps
CPU time 0.81 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536754191 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.536754191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.440377084
Short name T404
Test name
Test status
Simulation time 1266549883 ps
CPU time 6.35 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 242272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440377084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.440377084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.2897883996
Short name T385
Test name
Test status
Simulation time 302320236 ps
CPU time 1.4 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897883996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.2897883996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.214712096
Short name T345
Test name
Test status
Simulation time 91540695 ps
CPU time 0.74 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214712096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.214712096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.2035260067
Short name T396
Test name
Test status
Simulation time 1119005442 ps
CPU time 4.2 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035260067 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2035260067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.1390623743
Short name T386
Test name
Test status
Simulation time 188907705 ps
CPU time 1.45 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390623743 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.1390623743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.789526427
Short name T343
Test name
Test status
Simulation time 228957494 ps
CPU time 1.27 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789526427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.789526427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.2546153620
Short name T511
Test name
Test status
Simulation time 8631761390 ps
CPU time 32.1 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:49:05 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546153620 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2546153620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.2597026813
Short name T380
Test name
Test status
Simulation time 147576380 ps
CPU time 1.82 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597026813 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.2597026813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.3858690922
Short name T374
Test name
Test status
Simulation time 147082475 ps
CPU time 1.05 seconds
Started Aug 27 02:48:30 PM UTC 24
Finished Aug 27 02:48:32 PM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858690922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.3858690922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.2145240985
Short name T391
Test name
Test status
Simulation time 68151034 ps
CPU time 0.78 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145240985 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2145240985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.597802422
Short name T407
Test name
Test status
Simulation time 1276506318 ps
CPU time 5.36 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 241896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597802422 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.597802422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.405636293
Short name T395
Test name
Test status
Simulation time 302076053 ps
CPU time 1.36 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405636293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.405636293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.2620565207
Short name T383
Test name
Test status
Simulation time 76816604 ps
CPU time 0.93 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:33 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620565207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2620565207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.1260255395
Short name T428
Test name
Test status
Simulation time 1914795671 ps
CPU time 7.71 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:41 PM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260255395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.1260255395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1999830703
Short name T397
Test name
Test status
Simulation time 155665931 ps
CPU time 1.39 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999830703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1999830703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.2489295952
Short name T390
Test name
Test status
Simulation time 257485758 ps
CPU time 1.81 seconds
Started Aug 27 02:48:31 PM UTC 24
Finished Aug 27 02:48:34 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489295952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.2489295952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.2058970226
Short name T459
Test name
Test status
Simulation time 3440559743 ps
CPU time 12.32 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:46 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058970226 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.2058970226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.1589155984
Short name T398
Test name
Test status
Simulation time 136320981 ps
CPU time 1.68 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589155984 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1589155984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3482704202
Short name T392
Test name
Test status
Simulation time 167323962 ps
CPU time 1.11 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482704202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3482704202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.790233621
Short name T405
Test name
Test status
Simulation time 66442390 ps
CPU time 0.72 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790233621 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.790233621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.1066034906
Short name T460
Test name
Test status
Simulation time 2264048268 ps
CPU time 8.09 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:46 PM UTC 24
Peak memory 242464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066034906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.1066034906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.43756298
Short name T415
Test name
Test status
Simulation time 301789962 ps
CPU time 1.55 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43756298 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.43756298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.1791302301
Short name T394
Test name
Test status
Simulation time 213648493 ps
CPU time 0.96 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791302301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.1791302301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.3329999442
Short name T403
Test name
Test status
Simulation time 927792059 ps
CPU time 4.01 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:38 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329999442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.3329999442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.1508070152
Short name T408
Test name
Test status
Simulation time 103747965 ps
CPU time 1.2 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508070152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.1508070152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.1181825600
Short name T399
Test name
Test status
Simulation time 191910522 ps
CPU time 1.37 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:35 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181825600 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1181825600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.4093557639
Short name T509
Test name
Test status
Simulation time 5501326216 ps
CPU time 18.71 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:57 PM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093557639 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.4093557639
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.4270458527
Short name T416
Test name
Test status
Simulation time 244400536 ps
CPU time 1.71 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270458527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.4270458527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.2037211095
Short name T400
Test name
Test status
Simulation time 163330800 ps
CPU time 1.46 seconds
Started Aug 27 02:48:33 PM UTC 24
Finished Aug 27 02:48:36 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037211095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.2037211095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.3999811347
Short name T413
Test name
Test status
Simulation time 58532095 ps
CPU time 0.93 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999811347 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3999811347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.2400951032
Short name T457
Test name
Test status
Simulation time 1965638748 ps
CPU time 6.48 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 241536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400951032 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2400951032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1794130429
Short name T422
Test name
Test status
Simulation time 301821590 ps
CPU time 1.47 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794130429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1794130429
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.283287154
Short name T409
Test name
Test status
Simulation time 216107531 ps
CPU time 0.97 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:39 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283287154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.283287154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.2303721277
Short name T430
Test name
Test status
Simulation time 815588219 ps
CPU time 4.16 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 209384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303721277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.2303721277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.1515730423
Short name T414
Test name
Test status
Simulation time 159320777 ps
CPU time 1.31 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515730423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.1515730423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1096381647
Short name T410
Test name
Test status
Simulation time 113331064 ps
CPU time 1.12 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096381647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1096381647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.3827158082
Short name T454
Test name
Test status
Simulation time 1358421338 ps
CPU time 6.4 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 218056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827158082 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3827158082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.497938315
Short name T426
Test name
Test status
Simulation time 345782139 ps
CPU time 2.07 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:41 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497938315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.497938315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.3838429473
Short name T411
Test name
Test status
Simulation time 119150301 ps
CPU time 1.08 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838429473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3838429473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.3349485426
Short name T418
Test name
Test status
Simulation time 65696815 ps
CPU time 0.94 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349485426 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3349485426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.2341468465
Short name T456
Test name
Test status
Simulation time 1268704048 ps
CPU time 6.07 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 241672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341468465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.2341468465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2612216779
Short name T423
Test name
Test status
Simulation time 302657206 ps
CPU time 1.16 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612216779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2612216779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.2671533510
Short name T412
Test name
Test status
Simulation time 92695249 ps
CPU time 0.84 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 207824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671533510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.2671533510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.2417127712
Short name T435
Test name
Test status
Simulation time 1693421336 ps
CPU time 6.1 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 209140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417127712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.2417127712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2296057208
Short name T420
Test name
Test status
Simulation time 107822349 ps
CPU time 0.99 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296057208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2296057208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.3767167157
Short name T421
Test name
Test status
Simulation time 114704360 ps
CPU time 1.21 seconds
Started Aug 27 02:48:37 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767167157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.3767167157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.3550830809
Short name T478
Test name
Test status
Simulation time 2227046566 ps
CPU time 9.34 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 218148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550830809 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.3550830809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.181832801
Short name T427
Test name
Test status
Simulation time 141695004 ps
CPU time 1.72 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:41 PM UTC 24
Peak memory 208040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181832801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.181832801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.4239731191
Short name T417
Test name
Test status
Simulation time 81735318 ps
CPU time 0.91 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239731191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.4239731191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.2784728871
Short name T104
Test name
Test status
Simulation time 74450331 ps
CPU time 1.11 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784728871 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.2784728871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2781633662
Short name T146
Test name
Test status
Simulation time 302525708 ps
CPU time 1.42 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 237284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781633662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.2781633662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.951095867
Short name T18
Test name
Test status
Simulation time 174455258 ps
CPU time 1.28 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951095867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.951095867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.4006010300
Short name T101
Test name
Test status
Simulation time 1758464664 ps
CPU time 6.33 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006010300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4006010300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1455137347
Short name T73
Test name
Test status
Simulation time 16759001208 ps
CPU time 25.26 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:57 PM UTC 24
Peak memory 242336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455137347 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1455137347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1850884085
Short name T41
Test name
Test status
Simulation time 103855691 ps
CPU time 1.01 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850884085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1850884085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.101788296
Short name T43
Test name
Test status
Simulation time 121360255 ps
CPU time 1.23 seconds
Started Aug 27 02:47:30 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101788296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.101788296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.1897679036
Short name T82
Test name
Test status
Simulation time 299284200 ps
CPU time 2.07 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:34 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897679036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1897679036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1699196645
Short name T81
Test name
Test status
Simulation time 102986498 ps
CPU time 1.39 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699196645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1699196645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.2292480713
Short name T431
Test name
Test status
Simulation time 72149998 ps
CPU time 0.76 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292480713 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.2292480713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.3215475917
Short name T486
Test name
Test status
Simulation time 1965797766 ps
CPU time 7.14 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 242368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215475917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.3215475917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.1299886106
Short name T438
Test name
Test status
Simulation time 300914313 ps
CPU time 1.4 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299886106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.1299886106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.3576692295
Short name T419
Test name
Test status
Simulation time 109906267 ps
CPU time 0.82 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576692295 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.3576692295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.1642903045
Short name T433
Test name
Test status
Simulation time 887737501 ps
CPU time 3.85 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642903045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.1642903045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3671711110
Short name T434
Test name
Test status
Simulation time 100368613 ps
CPU time 1.07 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 208364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671711110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3671711110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.3935587364
Short name T424
Test name
Test status
Simulation time 121447369 ps
CPU time 1.19 seconds
Started Aug 27 02:48:38 PM UTC 24
Finished Aug 27 02:48:40 PM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935587364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3935587364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.2700528088
Short name T529
Test name
Test status
Simulation time 10652202380 ps
CPU time 34.92 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:49:17 PM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700528088 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.2700528088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.3796831923
Short name T443
Test name
Test status
Simulation time 125870814 ps
CPU time 1.77 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 216812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796831923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.3796831923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.3388085489
Short name T432
Test name
Test status
Simulation time 108731140 ps
CPU time 0.9 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388085489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3388085489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.2893202523
Short name T437
Test name
Test status
Simulation time 66822862 ps
CPU time 0.91 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893202523 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.2893202523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.2556184464
Short name T489
Test name
Test status
Simulation time 1971588384 ps
CPU time 7.49 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556184464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.2556184464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.3811728926
Short name T442
Test name
Test status
Simulation time 301315154 ps
CPU time 1.25 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811728926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.3811728926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.3275379588
Short name T436
Test name
Test status
Simulation time 180151449 ps
CPU time 1.15 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:43 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275379588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.3275379588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.1986130231
Short name T462
Test name
Test status
Simulation time 702752342 ps
CPU time 4.19 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:46 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986130231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1986130231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1252134118
Short name T444
Test name
Test status
Simulation time 161580741 ps
CPU time 1.59 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252134118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1252134118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.1461543983
Short name T439
Test name
Test status
Simulation time 198244110 ps
CPU time 1.31 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461543983 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.1461543983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.4034053786
Short name T528
Test name
Test status
Simulation time 8583802200 ps
CPU time 33.78 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:49:17 PM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034053786 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4034053786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.523548877
Short name T449
Test name
Test status
Simulation time 146999792 ps
CPU time 1.95 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523548877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.523548877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.3906101085
Short name T440
Test name
Test status
Simulation time 133191131 ps
CPU time 1.21 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906101085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3906101085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.2563447870
Short name T453
Test name
Test status
Simulation time 81907184 ps
CPU time 1.2 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563447870 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2563447870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.1034654156
Short name T498
Test name
Test status
Simulation time 2455415770 ps
CPU time 8.76 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:52 PM UTC 24
Peak memory 241788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034654156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1034654156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.3001270618
Short name T446
Test name
Test status
Simulation time 301990802 ps
CPU time 1.13 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001270618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.3001270618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.2506673093
Short name T441
Test name
Test status
Simulation time 230248660 ps
CPU time 1.15 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506673093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.2506673093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.2499933520
Short name T476
Test name
Test status
Simulation time 1548010225 ps
CPU time 5.26 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:48 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499933520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2499933520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.819696979
Short name T448
Test name
Test status
Simulation time 173409723 ps
CPU time 1.4 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819696979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.819696979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.3984668575
Short name T447
Test name
Test status
Simulation time 198492536 ps
CPU time 1.52 seconds
Started Aug 27 02:48:41 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 206632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984668575 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3984668575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2039741466
Short name T513
Test name
Test status
Simulation time 7819388893 ps
CPU time 25.85 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:49:10 PM UTC 24
Peak memory 209220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039741466 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2039741466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.1421806392
Short name T450
Test name
Test status
Simulation time 144242763 ps
CPU time 1.79 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421806392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1421806392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.1855690059
Short name T445
Test name
Test status
Simulation time 73781664 ps
CPU time 1.13 seconds
Started Aug 27 02:48:42 PM UTC 24
Finished Aug 27 02:48:44 PM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855690059 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1855690059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.295558580
Short name T463
Test name
Test status
Simulation time 87486222 ps
CPU time 0.85 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295558580 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.295558580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.1267405675
Short name T503
Test name
Test status
Simulation time 1973385791 ps
CPU time 8.3 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:54 PM UTC 24
Peak memory 241432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267405675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.1267405675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2576384735
Short name T472
Test name
Test status
Simulation time 303956831 ps
CPU time 1.69 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 237608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576384735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2576384735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.1832353433
Short name T455
Test name
Test status
Simulation time 128078755 ps
CPU time 1.16 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832353433 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.1832353433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.2325564339
Short name T494
Test name
Test status
Simulation time 1765962676 ps
CPU time 6.53 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:48:51 PM UTC 24
Peak memory 209196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325564339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2325564339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.940648251
Short name T466
Test name
Test status
Simulation time 154408065 ps
CPU time 1.11 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940648251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.940648251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.2224117021
Short name T452
Test name
Test status
Simulation time 249746512 ps
CPU time 1.47 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224117021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2224117021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.1170152782
Short name T508
Test name
Test status
Simulation time 2813755940 ps
CPU time 11.37 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:57 PM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170152782 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1170152782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.2847108405
Short name T470
Test name
Test status
Simulation time 139247008 ps
CPU time 1.73 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847108405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2847108405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.3383193199
Short name T451
Test name
Test status
Simulation time 63364860 ps
CPU time 0.82 seconds
Started Aug 27 02:48:43 PM UTC 24
Finished Aug 27 02:48:45 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383193199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3383193199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.2378641126
Short name T469
Test name
Test status
Simulation time 72372043 ps
CPU time 1.18 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378641126 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2378641126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.1237459444
Short name T500
Test name
Test status
Simulation time 1270126721 ps
CPU time 6.06 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:52 PM UTC 24
Peak memory 242316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237459444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1237459444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1167145056
Short name T471
Test name
Test status
Simulation time 303783263 ps
CPU time 1.27 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167145056 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1167145056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.2161422536
Short name T467
Test name
Test status
Simulation time 159166415 ps
CPU time 1.24 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161422536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2161422536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.670364618
Short name T499
Test name
Test status
Simulation time 1481376170 ps
CPU time 5.97 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:52 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670364618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.670364618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.3281954689
Short name T475
Test name
Test status
Simulation time 177451813 ps
CPU time 1.63 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:48 PM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281954689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.3281954689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.3764975299
Short name T468
Test name
Test status
Simulation time 111699538 ps
CPU time 1.42 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764975299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3764975299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.3740268771
Short name T512
Test name
Test status
Simulation time 6578418223 ps
CPU time 20.18 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:49:06 PM UTC 24
Peak memory 218236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740268771 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3740268771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.2355995633
Short name T473
Test name
Test status
Simulation time 126314157 ps
CPU time 1.54 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:47 PM UTC 24
Peak memory 216868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355995633 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.2355995633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.2959747694
Short name T474
Test name
Test status
Simulation time 241109391 ps
CPU time 1.61 seconds
Started Aug 27 02:48:45 PM UTC 24
Finished Aug 27 02:48:48 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959747694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2959747694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.3845877894
Short name T479
Test name
Test status
Simulation time 62821110 ps
CPU time 0.79 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845877894 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.3845877894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.853003571
Short name T501
Test name
Test status
Simulation time 1265965547 ps
CPU time 4.96 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:53 PM UTC 24
Peak memory 242272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853003571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.853003571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1754628102
Short name T483
Test name
Test status
Simulation time 301824426 ps
CPU time 1.15 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754628102 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1754628102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.322460145
Short name T480
Test name
Test status
Simulation time 183287638 ps
CPU time 1.15 seconds
Started Aug 27 02:48:46 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322460145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.322460145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.1546166328
Short name T506
Test name
Test status
Simulation time 2185756758 ps
CPU time 7.47 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:55 PM UTC 24
Peak memory 209260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546166328 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1546166328
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.363377273
Short name T484
Test name
Test status
Simulation time 138150214 ps
CPU time 1.29 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 207904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363377273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.363377273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.2268584464
Short name T481
Test name
Test status
Simulation time 135164735 ps
CPU time 1.26 seconds
Started Aug 27 02:48:46 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268584464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.2268584464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.667738061
Short name T510
Test name
Test status
Simulation time 3741402122 ps
CPU time 15.86 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:49:04 PM UTC 24
Peak memory 209308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667738061 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.667738061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.3771959208
Short name T488
Test name
Test status
Simulation time 279491572 ps
CPU time 2.22 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771959208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.3771959208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.685291612
Short name T485
Test name
Test status
Simulation time 139445463 ps
CPU time 1.5 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685291612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.685291612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.2850225184
Short name T492
Test name
Test status
Simulation time 80198697 ps
CPU time 0.83 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850225184 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.2850225184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.3545715443
Short name T505
Test name
Test status
Simulation time 1275698529 ps
CPU time 5.14 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:55 PM UTC 24
Peak memory 241664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545715443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.3545715443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2812832410
Short name T515
Test name
Test status
Simulation time 301861464 ps
CPU time 1.2 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 237636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812832410 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2812832410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2059818769
Short name T482
Test name
Test status
Simulation time 156321965 ps
CPU time 1.03 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:49 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059818769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2059818769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.2314984086
Short name T504
Test name
Test status
Simulation time 1003743346 ps
CPU time 4.93 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:54 PM UTC 24
Peak memory 209324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314984086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.2314984086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.535111980
Short name T495
Test name
Test status
Simulation time 179446206 ps
CPU time 1.44 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:51 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535111980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.535111980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.3571470089
Short name T487
Test name
Test status
Simulation time 234827104 ps
CPU time 1.74 seconds
Started Aug 27 02:48:47 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 207912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571470089 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.3571470089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.2349616292
Short name T543
Test name
Test status
Simulation time 16583788295 ps
CPU time 48.35 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:49:58 PM UTC 24
Peak memory 218112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349616292 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.2349616292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.3043760835
Short name T497
Test name
Test status
Simulation time 134237748 ps
CPU time 1.79 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:51 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043760835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.3043760835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.1535137667
Short name T491
Test name
Test status
Simulation time 90533497 ps
CPU time 0.89 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:48:50 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535137667 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.1535137667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.143845326
Short name T533
Test name
Test status
Simulation time 72570009 ps
CPU time 0.81 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:32 PM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143845326 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.143845326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.3877975052
Short name T539
Test name
Test status
Simulation time 1272046129 ps
CPU time 5.55 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 242332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877975052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.3877975052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3545442771
Short name T465
Test name
Test status
Simulation time 301958497 ps
CPU time 1.2 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545442771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3545442771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3296925937
Short name T514
Test name
Test status
Simulation time 216872642 ps
CPU time 0.89 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296925937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3296925937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.1056205
Short name T526
Test name
Test status
Simulation time 897241981 ps
CPU time 3.98 seconds
Started Aug 27 02:48:49 PM UTC 24
Finished Aug 27 02:49:14 PM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1056205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4084169933
Short name T519
Test name
Test status
Simulation time 174945518 ps
CPU time 1.15 seconds
Started Aug 27 02:48:49 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084169933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4084169933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.104703027
Short name T517
Test name
Test status
Simulation time 119614972 ps
CPU time 1.15 seconds
Started Aug 27 02:48:48 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104703027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.104703027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.698805431
Short name T542
Test name
Test status
Simulation time 4416022572 ps
CPU time 14.47 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:46 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698805431 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.698805431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.3262393036
Short name T523
Test name
Test status
Simulation time 125992270 ps
CPU time 1.42 seconds
Started Aug 27 02:48:49 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 216552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262393036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.3262393036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.911591642
Short name T520
Test name
Test status
Simulation time 217985822 ps
CPU time 1.38 seconds
Started Aug 27 02:48:49 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911591642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.911591642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.724433195
Short name T516
Test name
Test status
Simulation time 85649436 ps
CPU time 0.78 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724433195 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.724433195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.1260115807
Short name T540
Test name
Test status
Simulation time 1267209187 ps
CPU time 5.83 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 241288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260115807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1260115807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.647585229
Short name T461
Test name
Test status
Simulation time 303492703 ps
CPU time 1.16 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 237572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647585229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.647585229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.2702961694
Short name T464
Test name
Test status
Simulation time 183989285 ps
CPU time 0.86 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702961694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.2702961694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.1862145157
Short name T541
Test name
Test status
Simulation time 1827176790 ps
CPU time 6.36 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:41 PM UTC 24
Peak memory 209136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862145157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1862145157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.1751978467
Short name T536
Test name
Test status
Simulation time 187356400 ps
CPU time 1.15 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 207624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751978467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.1751978467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2228854417
Short name T534
Test name
Test status
Simulation time 116444190 ps
CPU time 1.2 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:33 PM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228854417 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2228854417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.419288591
Short name T531
Test name
Test status
Simulation time 4227055194 ps
CPU time 17.04 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:27 PM UTC 24
Peak memory 217072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419288591 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.419288591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.1481754384
Short name T537
Test name
Test status
Simulation time 151499106 ps
CPU time 2 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:37 PM UTC 24
Peak memory 208280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481754384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1481754384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.1056212919
Short name T535
Test name
Test status
Simulation time 111649944 ps
CPU time 1.05 seconds
Started Aug 27 02:48:50 PM UTC 24
Finished Aug 27 02:49:36 PM UTC 24
Peak memory 208292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056212919 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.1056212919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.2029826724
Short name T530
Test name
Test status
Simulation time 74790188 ps
CPU time 0.75 seconds
Started Aug 27 02:48:53 PM UTC 24
Finished Aug 27 02:49:26 PM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029826724 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.2029826724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.238219214
Short name T538
Test name
Test status
Simulation time 2455754847 ps
CPU time 7.97 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:38 PM UTC 24
Peak memory 241776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238219214 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.238219214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.2152754629
Short name T532
Test name
Test status
Simulation time 301902644 ps
CPU time 1.01 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:31 PM UTC 24
Peak memory 237456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152754629 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.2152754629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.987218062
Short name T518
Test name
Test status
Simulation time 168452609 ps
CPU time 0.87 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987218062 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.987218062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.3088731868
Short name T527
Test name
Test status
Simulation time 1161579192 ps
CPU time 4.25 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:14 PM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088731868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.3088731868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.1525980468
Short name T522
Test name
Test status
Simulation time 95541058 ps
CPU time 0.94 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525980468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.1525980468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.2889646273
Short name T521
Test name
Test status
Simulation time 124194349 ps
CPU time 1.11 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889646273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2889646273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.964655022
Short name T544
Test name
Test status
Simulation time 12588998840 ps
CPU time 44.61 seconds
Started Aug 27 02:48:53 PM UTC 24
Finished Aug 27 02:50:10 PM UTC 24
Peak memory 209220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964655022 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.964655022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.673600265
Short name T525
Test name
Test status
Simulation time 474246873 ps
CPU time 2.47 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:13 PM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673600265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.673600265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.997523096
Short name T524
Test name
Test status
Simulation time 267486873 ps
CPU time 1.3 seconds
Started Aug 27 02:48:52 PM UTC 24
Finished Aug 27 02:49:11 PM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997523096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.997523096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.1588976822
Short name T148
Test name
Test status
Simulation time 72748200 ps
CPU time 1.06 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588976822 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.1588976822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.1444347255
Short name T140
Test name
Test status
Simulation time 1276878299 ps
CPU time 7.54 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 241368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444347255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1444347255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2497932699
Short name T152
Test name
Test status
Simulation time 301905709 ps
CPU time 2.14 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 237832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497932699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2497932699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2701360146
Short name T19
Test name
Test status
Simulation time 108032091 ps
CPU time 1.01 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701360146 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2701360146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1962520558
Short name T100
Test name
Test status
Simulation time 904203084 ps
CPU time 3.82 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:36 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962520558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1962520558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.794963582
Short name T147
Test name
Test status
Simulation time 193580193 ps
CPU time 1.22 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:36 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794963582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.794963582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3972190071
Short name T88
Test name
Test status
Simulation time 126486185 ps
CPU time 1.63 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:34 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972190071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.3972190071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3902486976
Short name T110
Test name
Test status
Simulation time 3260508144 ps
CPU time 15.33 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:51 PM UTC 24
Peak memory 209224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902486976 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3902486976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.83334979
Short name T84
Test name
Test status
Simulation time 369616307 ps
CPU time 2.34 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83334979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.83334979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.3968259155
Short name T138
Test name
Test status
Simulation time 78164797 ps
CPU time 1.03 seconds
Started Aug 27 02:47:31 PM UTC 24
Finished Aug 27 02:47:33 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968259155 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.3968259155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.2891319798
Short name T149
Test name
Test status
Simulation time 71901624 ps
CPU time 0.84 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891319798 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2891319798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2539808626
Short name T55
Test name
Test status
Simulation time 1964715021 ps
CPU time 7.69 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:44 PM UTC 24
Peak memory 242380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539808626 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2539808626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.161280356
Short name T151
Test name
Test status
Simulation time 301117317 ps
CPU time 1.65 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 237684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161280356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.161280356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1006173061
Short name T20
Test name
Test status
Simulation time 101082003 ps
CPU time 0.92 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006173061 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1006173061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.641368769
Short name T103
Test name
Test status
Simulation time 1540756330 ps
CPU time 6.57 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:42 PM UTC 24
Peak memory 209220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641368769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.641368769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3476380944
Short name T153
Test name
Test status
Simulation time 164939509 ps
CPU time 1.81 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476380944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3476380944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2924145733
Short name T89
Test name
Test status
Simulation time 226825349 ps
CPU time 1.59 seconds
Started Aug 27 02:47:34 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924145733 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.2924145733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.1813747889
Short name T107
Test name
Test status
Simulation time 1974919230 ps
CPU time 9.37 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:45 PM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813747889 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.1813747889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.2440627189
Short name T85
Test name
Test status
Simulation time 375084775 ps
CPU time 2.74 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:39 PM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440627189 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.2440627189
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.1353471539
Short name T154
Test name
Test status
Simulation time 63325916 ps
CPU time 0.99 seconds
Started Aug 27 02:47:38 PM UTC 24
Finished Aug 27 02:47:40 PM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353471539 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.1353471539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.3590443216
Short name T28
Test name
Test status
Simulation time 1963465571 ps
CPU time 8.7 seconds
Started Aug 27 02:47:37 PM UTC 24
Finished Aug 27 02:47:47 PM UTC 24
Peak memory 242044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590443216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.3590443216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1903850782
Short name T15
Test name
Test status
Simulation time 302870178 ps
CPU time 1.82 seconds
Started Aug 27 02:47:37 PM UTC 24
Finished Aug 27 02:47:40 PM UTC 24
Peak memory 237060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903850782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1903850782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2837693689
Short name T21
Test name
Test status
Simulation time 79244482 ps
CPU time 0.98 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837693689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2837693689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.35944996
Short name T106
Test name
Test status
Simulation time 1916587697 ps
CPU time 7.5 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:44 PM UTC 24
Peak memory 209156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35944996 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.35944996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.222708862
Short name T142
Test name
Test status
Simulation time 177873195 ps
CPU time 1.27 seconds
Started Aug 27 02:47:37 PM UTC 24
Finished Aug 27 02:47:40 PM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222708862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.222708862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2073039175
Short name T90
Test name
Test status
Simulation time 128199154 ps
CPU time 1.57 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:38 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073039175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.2073039175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.3258119574
Short name T114
Test name
Test status
Simulation time 3472969778 ps
CPU time 11.28 seconds
Started Aug 27 02:47:37 PM UTC 24
Finished Aug 27 02:47:50 PM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258119574 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3258119574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3162443337
Short name T87
Test name
Test status
Simulation time 448537704 ps
CPU time 2.9 seconds
Started Aug 27 02:47:37 PM UTC 24
Finished Aug 27 02:47:41 PM UTC 24
Peak memory 209056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162443337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3162443337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.1303692379
Short name T150
Test name
Test status
Simulation time 82820770 ps
CPU time 0.86 seconds
Started Aug 27 02:47:35 PM UTC 24
Finished Aug 27 02:47:37 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303692379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.1303692379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.14300532
Short name T155
Test name
Test status
Simulation time 63147889 ps
CPU time 0.75 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:41 PM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14300532 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.14300532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1909041265
Short name T46
Test name
Test status
Simulation time 1261828684 ps
CPU time 5.77 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:46 PM UTC 24
Peak memory 241736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909041265 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1909041265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.3701628242
Short name T158
Test name
Test status
Simulation time 301247124 ps
CPU time 2.21 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:42 PM UTC 24
Peak memory 237772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701628242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.3701628242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.655337456
Short name T22
Test name
Test status
Simulation time 185374001 ps
CPU time 1.31 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:41 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655337456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.655337456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3327670166
Short name T109
Test name
Test status
Simulation time 2161205703 ps
CPU time 8.15 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327670166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3327670166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1142209508
Short name T157
Test name
Test status
Simulation time 166905868 ps
CPU time 1.68 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:42 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142209508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.1142209508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3596764220
Short name T12
Test name
Test status
Simulation time 194283668 ps
CPU time 1.49 seconds
Started Aug 27 02:47:38 PM UTC 24
Finished Aug 27 02:47:40 PM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596764220 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3596764220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.2221001708
Short name T113
Test name
Test status
Simulation time 949278463 ps
CPU time 4.77 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:45 PM UTC 24
Peak memory 209160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221001708 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.2221001708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.331522402
Short name T39
Test name
Test status
Simulation time 352401725 ps
CPU time 3.15 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331522402 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.331522402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.651125569
Short name T156
Test name
Test status
Simulation time 100577372 ps
CPU time 1.34 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:41 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651125569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.651125569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2527426223
Short name T161
Test name
Test status
Simulation time 85286291 ps
CPU time 0.96 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:44 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527426223 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.2527426223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3980694556
Short name T141
Test name
Test status
Simulation time 1984038386 ps
CPU time 7.26 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:50 PM UTC 24
Peak memory 241940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980694556 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3980694556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1980496696
Short name T162
Test name
Test status
Simulation time 301914921 ps
CPU time 1.32 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:44 PM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980496696 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1980496696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1573688722
Short name T23
Test name
Test status
Simulation time 189738316 ps
CPU time 1.34 seconds
Started Aug 27 02:47:41 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 207868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573688722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1573688722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.1459538839
Short name T134
Test name
Test status
Simulation time 1535870090 ps
CPU time 6.66 seconds
Started Aug 27 02:47:41 PM UTC 24
Finished Aug 27 02:47:48 PM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459538839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1459538839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.3125118833
Short name T160
Test name
Test status
Simulation time 111067116 ps
CPU time 1.53 seconds
Started Aug 27 02:47:41 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125118833 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.3125118833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.3780233414
Short name T137
Test name
Test status
Simulation time 249738226 ps
CPU time 2.14 seconds
Started Aug 27 02:47:39 PM UTC 24
Finished Aug 27 02:47:42 PM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780233414 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.3780233414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.2194977822
Short name T213
Test name
Test status
Simulation time 3740272446 ps
CPU time 16.1 seconds
Started Aug 27 02:47:42 PM UTC 24
Finished Aug 27 02:47:59 PM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194977822 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2194977822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2561162401
Short name T159
Test name
Test status
Simulation time 124619908 ps
CPU time 1.73 seconds
Started Aug 27 02:47:41 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561162401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2561162401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.3247279865
Short name T139
Test name
Test status
Simulation time 191578099 ps
CPU time 1.72 seconds
Started Aug 27 02:47:41 PM UTC 24
Finished Aug 27 02:47:43 PM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247279865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3247279865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest
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