Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7895

1

T3

10

T8

30

T9

21

auto[1]

11073

1

T3

1

T5

4

T8

22

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5848	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6467	1			T1	1		T2	1		T3	1
reset_info_cp[2]	2891	1			T5	1		T8	7		T9	15
reset_info_cp[4]	3854	1			T5	1		T8	10		T9	17
reset_info_cp[8]	107	1			T9	1		T49	1		T86	2
reset_info_cp[16]	93	1			T3	1		T49	1		T85	1
reset_info_cp[32]	114	1			T9	1		T49	2		T52	1
reset_info_cp[64]	108	1			T9	1		T49	2		T86	1
reset_info_cp[128]	99	1			T3	1		T24	1		T49	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3072	1			T8	12		T9	21		T49	32
reset_info_cp[1]	auto[1]	2782	1			T5	1		T8	7		T9	6
reset_info_cp[2]	auto[0]	893	1			T8	4		T49	18		T44	7
reset_info_cp[2]	auto[1]	1998	1			T5	1		T8	3		T9	15
reset_info_cp[4]	auto[0]	1344	1			T8	3		T49	16		T44	4
reset_info_cp[4]	auto[1]	2510	1			T5	1		T8	7		T9	17
reset_info_cp[8]	auto[0]	45	1			T86	2		T135	1		T98	1
reset_info_cp[8]	auto[1]	62	1			T9	1		T49	1		T37	1
reset_info_cp[16]	auto[0]	39	1			T3	1		T85	1		T44	1
reset_info_cp[16]	auto[1]	54	1			T49	1		T36	2		T27	2
reset_info_cp[32]	auto[0]	38	1			T49	2		T105	1		T137	1
reset_info_cp[32]	auto[1]	76	1			T9	1		T52	1		T43	1
reset_info_cp[64]	auto[0]	54	1			T86	1		T45	1		T138	1
reset_info_cp[64]	auto[1]	54	1			T9	1		T49	2		T36	1
reset_info_cp[128]	auto[0]	40	1			T3	1		T24	1		T49	1
reset_info_cp[128]	auto[1]	59	1			T136	1		T36	1		T26	1