Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.40 99.24 100.00 99.83 99.46 98.77


Total tests in report: 613
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.62 82.62 95.53 95.53 88.69 88.69 90.28 90.28 94.83 94.83 88.96 88.96 37.44 37.44 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.259242175
90.21 7.59 97.26 1.73 93.48 4.79 91.29 1.01 97.50 2.67 90.31 1.35 71.43 33.99 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.155765294
92.45 2.24 97.92 0.66 96.04 2.57 91.62 0.34 98.33 0.83 90.98 0.67 79.80 8.37 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2465703247
94.68 2.23 98.51 0.60 96.81 0.76 94.81 3.18 99.17 0.83 95.02 4.04 83.74 3.94 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.956573408
96.34 1.67 98.63 0.12 97.02 0.21 95.60 0.80 99.33 0.17 96.10 1.08 91.38 7.64 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1540423226
97.41 1.07 99.05 0.42 97.22 0.21 99.08 3.48 99.67 0.33 96.37 0.27 93.10 1.72 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3397103553
97.96 0.55 99.05 0.00 97.22 0.00 99.08 0.00 99.67 0.00 98.92 2.56 93.84 0.74 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.3594302605
98.45 0.48 99.11 0.06 97.85 0.62 99.08 0.00 99.67 0.00 98.92 0.00 96.06 2.22 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.510788410
98.64 0.19 99.11 0.00 97.85 0.00 99.08 0.00 99.83 0.17 98.92 0.00 97.04 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3412140174
98.80 0.16 99.11 0.00 97.85 0.00 99.08 0.00 99.83 0.00 98.92 0.00 98.03 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1306959805
98.95 0.15 99.11 0.00 97.99 0.14 99.08 0.00 99.83 0.00 98.92 0.00 98.77 0.74 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.996521784
99.08 0.14 99.40 0.30 98.33 0.35 99.25 0.17 99.83 0.00 98.92 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.870781156
99.21 0.13 99.40 0.00 98.33 0.00 99.75 0.50 99.83 0.00 99.19 0.27 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1287665897
99.34 0.13 99.40 0.00 99.10 0.76 99.75 0.00 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.756852541
99.37 0.03 99.40 0.00 99.10 0.00 99.92 0.17 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4016887765
99.39 0.02 99.40 0.00 99.10 0.00 99.92 0.00 99.83 0.00 99.33 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1666284550
99.41 0.02 99.40 0.00 99.10 0.00 99.92 0.00 99.83 0.00 99.46 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1596153382
99.43 0.01 99.40 0.00 99.10 0.00 100.00 0.08 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.607851346
99.44 0.01 99.40 0.00 99.17 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3652505474
99.45 0.01 99.40 0.00 99.24 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2565459726

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3828019828
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.600587768
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1643990838
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4099723713
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2493964454
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3521016704
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2894227984
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3329747645
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3938118766
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.274715590
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3666300601
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2456345718
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4288409544
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1081660368
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158172592
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.247154388
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3691891755
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1701029671
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1414546489
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.784845046
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2861004088
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2729335424
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2540413134
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1794203961
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2815850948
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2491249296
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4031526376
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2830462632
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2406289668
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2224052897
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3443690193
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3198418243
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.458262603
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3346732896
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4275695735
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.413214859
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.578551987
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3220667022
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.4048752569
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3867092386
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2707173983
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1380081925
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2222651693
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2569368035
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.848352425
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1424725955
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2102354568
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.279368584
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.798311928
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3360248648
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.964006826
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3100223576
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2246395609
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1773440407
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.478227309
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.3703844828
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3079029451
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.505660531
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1168989475
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.390227756
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1071963677
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.618117755
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3548811614
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1277436496
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1181512726
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.195619045
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1668843453
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2121663341
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.73065412
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4078576035
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.34017977
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3376224700
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3195782559
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.2083747395
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.829984465
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2572187277
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.537552884
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2987768957
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2933436855
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4280878666
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3238653756
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1386640018
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3927547226
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.1978946883
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3229214202
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1353269135
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2087591169
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.260046806
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1480405316
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.47445398
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.126745800
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2346511968
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3483759375
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.4170723744
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3931730044
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2999140574
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.720544411
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4070564539
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3428317600
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2399837694
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2521100812
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2272295722
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/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3105986153
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.847867284
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.3545564628
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3139517071
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2590818252
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.3623782650
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.205426860
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1820795780
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.18362677
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.351019099
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1871272923
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.3632980454
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.844151555
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3554959440
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.782296323
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.4167682102
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1192725932
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.1242072872
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2719500340
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2162994375
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2365820378
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4045016898
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1094361875
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.527953060
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3901459273
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.4087911869
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1080428862
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.2574684634
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.313859721
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2680034551
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1545128768
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2562525931
/workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1346820904



Total test records in report: 613
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.870781156 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:17 AM UTC 24 62027765 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.987254548 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:17 AM UTC 24 188785913 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1480143083 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:17 AM UTC 24 149791678 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1596153382 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:17 AM UTC 24 166071883 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4116268282 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:17 AM UTC 24 203440013 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.155765294 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:17 AM UTC 24 145739752 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.2757027797 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:18 AM UTC 24 141416873 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1142996168 Aug 29 10:57:12 AM UTC 24 Aug 29 10:57:21 AM UTC 24 1401007175 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.607851346 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:21 AM UTC 24 1267996156 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.259242175 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:37 AM UTC 24 119397651 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3568118370 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:22 AM UTC 24 253900021 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2345946048 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:22 AM UTC 24 89105610 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2025775106 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:22 AM UTC 24 301539984 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.647858853 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:22 AM UTC 24 101105454 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2629215579 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:22 AM UTC 24 187702272 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.956573408 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:23 AM UTC 24 8803766460 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1050917658 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:23 AM UTC 24 246740125 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2323077 Aug 29 10:57:18 AM UTC 24 Aug 29 10:57:26 AM UTC 24 85454818 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1540423226 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:33 AM UTC 24 3136341819 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.1208089917 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:26 AM UTC 24 82316117 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.3118964732 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:26 AM UTC 24 61114262 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3412140174 Aug 29 10:57:18 AM UTC 24 Aug 29 10:57:26 AM UTC 24 172078061 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.731903719 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:26 AM UTC 24 162153025 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3937176144 Aug 29 10:57:18 AM UTC 24 Aug 29 10:57:26 AM UTC 24 123123759 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2500120608 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:26 AM UTC 24 304023720 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1878632950 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:27 AM UTC 24 302697523 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.4275942858 Aug 29 10:57:25 AM UTC 24 Aug 29 10:57:27 AM UTC 24 84658335 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.763246177 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:27 AM UTC 24 187040462 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2444623619 Aug 29 10:57:25 AM UTC 24 Aug 29 10:57:27 AM UTC 24 152151929 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.2693371895 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:27 AM UTC 24 102077049 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2772017941 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:27 AM UTC 24 251826537 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1306959805 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:27 AM UTC 24 164122226 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.1349199973 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:27 AM UTC 24 136455796 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.600842630 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:27 AM UTC 24 101244620 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.4280263241 Aug 29 10:57:25 AM UTC 24 Aug 29 10:57:27 AM UTC 24 247914136 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2663329346 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:28 AM UTC 24 301456480 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.450724526 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:28 AM UTC 24 65524656 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3685447493 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:28 AM UTC 24 144694223 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2375582693 Aug 29 10:57:18 AM UTC 24 Aug 29 10:57:28 AM UTC 24 432329767 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3397103553 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:28 AM UTC 24 1966628948 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4283295133 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:29 AM UTC 24 64369141 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2575120705 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:29 AM UTC 24 100988104 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3669777830 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:29 AM UTC 24 860379455 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4016887765 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:29 AM UTC 24 1971625794 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2657460198 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:29 AM UTC 24 132814125 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.4254454255 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:29 AM UTC 24 187162267 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3595851357 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:29 AM UTC 24 302246978 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3026867034 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:30 AM UTC 24 450485799 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2417746070 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:30 AM UTC 24 55200630 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.847867284 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:30 AM UTC 24 249573556 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1153961947 Aug 29 10:57:18 AM UTC 24 Aug 29 10:57:30 AM UTC 24 839497484 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4162082344 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:30 AM UTC 24 300492801 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3866112411 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:30 AM UTC 24 301249611 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.449832283 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:31 AM UTC 24 1266787552 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.2460025812 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 73951271 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.18362677 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 108578253 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2590818252 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 101942582 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3105986153 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 143614783 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.3623782650 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 68818892 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3139517071 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 111397815 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.1242072872 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 94284524 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4000513364 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 300832230 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2191252135 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:31 AM UTC 24 1776619236 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.782296323 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 133946307 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1820795780 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 302659042 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.3632980454 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:31 AM UTC 24 117865776 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1871272923 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:32 AM UTC 24 159696849 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2365820378 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:32 AM UTC 24 199908577 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3554959440 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:32 AM UTC 24 347199592 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.498474346 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:32 AM UTC 24 1748303310 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.3594302605 Aug 29 10:57:25 AM UTC 24 Aug 29 10:57:33 AM UTC 24 1932877375 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4282179978 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:34 AM UTC 24 1270458868 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.3823646455 Aug 29 10:57:08 AM UTC 24 Aug 29 10:57:34 AM UTC 24 7172994870 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3036583300 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:34 AM UTC 24 2463376143 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2719500340 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:35 AM UTC 24 1138249524 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.351019099 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:35 AM UTC 24 1126279962 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2162994375 Aug 29 10:57:33 AM UTC 24 Aug 29 10:57:35 AM UTC 24 102287804 ps
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T29 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.205426860 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:36 AM UTC 24 1261083969 ps
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T150 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.4167682102 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:36 AM UTC 24 71581688 ps
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T151 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1192725932 Aug 29 10:57:34 AM UTC 24 Aug 29 10:57:37 AM UTC 24 301904763 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1346820904 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:37 AM UTC 24 153078195 ps
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T153 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4045016898 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:39 AM UTC 24 781754239 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4176425491 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:39 AM UTC 24 2726057808 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1287665897 Aug 29 10:57:33 AM UTC 24 Aug 29 10:57:41 AM UTC 24 1960385821 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.1102853873 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 75160749 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1607965552 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 103358828 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2510424838 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 150606425 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1208610186 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 301667442 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2862822870 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 107738799 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2242710665 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 173315127 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2796091045 Aug 29 10:57:39 AM UTC 24 Aug 29 10:57:42 AM UTC 24 96248992 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.3978398609 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 119789168 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.3545564628 Aug 29 10:57:29 AM UTC 24 Aug 29 10:57:42 AM UTC 24 3113395499 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2955829886 Aug 29 10:57:39 AM UTC 24 Aug 29 10:57:42 AM UTC 24 303403800 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.1317214065 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:42 AM UTC 24 133075439 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.736114577 Aug 29 10:57:39 AM UTC 24 Aug 29 10:57:43 AM UTC 24 325792196 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.2538842861 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:45 AM UTC 24 895697189 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.3720129395 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:45 AM UTC 24 899119161 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.4101792490 Aug 29 10:57:41 AM UTC 24 Aug 29 10:57:46 AM UTC 24 190288305 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2510019726 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:46 AM UTC 24 7304966453 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3942917046 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:46 AM UTC 24 95606137 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.4069956124 Aug 29 10:57:41 AM UTC 24 Aug 29 10:57:46 AM UTC 24 111693125 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2627346944 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:47 AM UTC 24 302068949 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.379294020 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:47 AM UTC 24 210410459 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.160202101 Aug 29 10:57:17 AM UTC 24 Aug 29 10:57:47 AM UTC 24 16639754845 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.1020061800 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:47 AM UTC 24 253821721 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.1994659625 Aug 29 10:57:19 AM UTC 24 Aug 29 10:57:47 AM UTC 24 16515212463 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3834354771 Aug 29 10:57:37 AM UTC 24 Aug 29 10:57:47 AM UTC 24 1952252866 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1028295820 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:48 AM UTC 24 358541332 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.278421992 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:48 AM UTC 24 656280468 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.2572763821 Aug 29 10:57:23 AM UTC 24 Aug 29 10:57:49 AM UTC 24 16542864276 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1767989679 Aug 29 10:57:44 AM UTC 24 Aug 29 10:57:49 AM UTC 24 739290532 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.4213302462 Aug 29 10:57:39 AM UTC 24 Aug 29 10:57:50 AM UTC 24 2450932373 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1511268473 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:51 AM UTC 24 1538842043 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.244440968 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:51 AM UTC 24 78356473 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.161815112 Aug 29 10:57:24 AM UTC 24 Aug 29 10:57:52 AM UTC 24 16520910954 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.1850502687 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 79192593 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.4060607156 Aug 29 10:57:47 AM UTC 24 Aug 29 10:57:52 AM UTC 24 82405725 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4212831331 Aug 29 10:57:47 AM UTC 24 Aug 29 10:57:52 AM UTC 24 112023805 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1247759383 Aug 29 10:57:47 AM UTC 24 Aug 29 10:57:52 AM UTC 24 302080683 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.1053768205 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:52 AM UTC 24 199486289 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2205517922 Aug 29 10:57:39 AM UTC 24 Aug 29 10:57:52 AM UTC 24 98275069 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3836828156 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:52 AM UTC 24 302358959 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.473452051 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:52 AM UTC 24 170617983 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.2540771651 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:52 AM UTC 24 208242182 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3698453372 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:52 AM UTC 24 260899421 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.577136065 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:53 AM UTC 24 2261794647 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.3955761762 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:53 AM UTC 24 274357756 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.1029963756 Aug 29 10:57:51 AM UTC 24 Aug 29 10:57:53 AM UTC 24 84871945 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1766087840 Aug 29 10:57:51 AM UTC 24 Aug 29 10:57:53 AM UTC 24 180150975 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.1899690330 Aug 29 10:57:51 AM UTC 24 Aug 29 10:57:53 AM UTC 24 116152132 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3020576095 Aug 29 10:57:44 AM UTC 24 Aug 29 10:57:54 AM UTC 24 153291516 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.2202638512 Aug 29 10:57:44 AM UTC 24 Aug 29 10:57:54 AM UTC 24 262282136 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.15046218 Aug 29 10:57:44 AM UTC 24 Aug 29 10:57:55 AM UTC 24 155023426 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3126563104 Aug 29 10:57:49 AM UTC 24 Aug 29 10:57:55 AM UTC 24 967822937 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.4075773395 Aug 29 10:57:47 AM UTC 24 Aug 29 10:57:56 AM UTC 24 1272669953 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.135797551 Aug 29 10:57:51 AM UTC 24 Aug 29 10:57:58 AM UTC 24 1402758410 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.971609797 Aug 29 10:57:43 AM UTC 24 Aug 29 10:57:56 AM UTC 24 57446289 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.69030582 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 106736530 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.967136201 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 189693140 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1135004118 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 77036736 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3901459273 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 66197372 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.78671198 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 102524682 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3463857130 Aug 29 10:57:27 AM UTC 24 Aug 29 10:57:57 AM UTC 24 9355155745 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.156878000 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 68484358 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.226400238 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 123161354 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.217406740 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 153480949 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.3937061413 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 145367611 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1584021248 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 135857770 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3317433931 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 192997176 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3761545609 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 301108868 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1094049193 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 301698970 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1881941661 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 124153058 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2680034551 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 149116688 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1883660091 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 182574333 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1314923127 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 73064226 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3936962373 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:57 AM UTC 24 265788262 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3236695542 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:57 AM UTC 24 301824051 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3189868147 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 103279167 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3678408125 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 258459436 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1745522132 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 187785735 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.1024942083 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 210776211 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1080428862 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 301947535 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1429923456 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 170615091 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.446498344 Aug 29 10:57:35 AM UTC 24 Aug 29 10:57:58 AM UTC 24 302278052 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.2370902182 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:58 AM UTC 24 273029016 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.807706362 Aug 29 10:57:56 AM UTC 24 Aug 29 10:57:58 AM UTC 24 92152528 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2155595666 Aug 29 10:57:56 AM UTC 24 Aug 29 10:57:58 AM UTC 24 158022444 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.529255888 Aug 29 10:57:54 AM UTC 24 Aug 29 10:57:58 AM UTC 24 377819204 ps
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T237 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2504601371 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:01 AM UTC 24 153736814 ps
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T239 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.697246138 Aug 29 10:57:37 AM UTC 24 Aug 29 10:58:01 AM UTC 24 5340279582 ps
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T241 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.1146418169 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:01 AM UTC 24 193078094 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.641273598 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:01 AM UTC 24 123484766 ps
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T244 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3385685927 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:01 AM UTC 24 301988255 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.1302449816 Aug 29 10:57:54 AM UTC 24 Aug 29 10:58:02 AM UTC 24 1269535537 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.3761439078 Aug 29 10:57:54 AM UTC 24 Aug 29 10:58:02 AM UTC 24 1263883437 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2950323438 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:02 AM UTC 24 302036320 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2414367868 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:02 AM UTC 24 120832933 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.3232413335 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:02 AM UTC 24 113150324 ps
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T249 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.2394987717 Aug 29 10:57:35 AM UTC 24 Aug 29 10:58:02 AM UTC 24 1373300141 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2811985653 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:02 AM UTC 24 255152176 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.845565956 Aug 29 10:57:35 AM UTC 24 Aug 29 10:58:02 AM UTC 24 1270034853 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.711723846 Aug 29 10:57:54 AM UTC 24 Aug 29 10:58:02 AM UTC 24 1571412174 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2007147313 Aug 29 10:58:00 AM UTC 24 Aug 29 10:58:03 AM UTC 24 138073061 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.1936791530 Aug 29 10:57:56 AM UTC 24 Aug 29 10:58:03 AM UTC 24 1407802049 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.1967130341 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:03 AM UTC 24 380279045 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.3259993901 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:03 AM UTC 24 361495208 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3192243785 Aug 29 10:58:01 AM UTC 24 Aug 29 10:58:03 AM UTC 24 197654262 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1435715464 Aug 29 10:58:00 AM UTC 24 Aug 29 10:58:03 AM UTC 24 301277163 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.4087911869 Aug 29 10:57:35 AM UTC 24 Aug 29 10:58:04 AM UTC 24 2238551704 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.528337205 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:04 AM UTC 24 762213164 ps
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T262 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3630430424 Aug 29 10:57:58 AM UTC 24 Aug 29 10:58:05 AM UTC 24 1275698996 ps
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T264 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2163966180 Aug 29 10:58:01 AM UTC 24 Aug 29 10:58:05 AM UTC 24 70774221 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1648286830 Aug 29 10:57:35 AM UTC 24 Aug 29 10:58:06 AM UTC 24 2440374734 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.2298049798 Aug 29 10:58:01 AM UTC 24 Aug 29 10:58:06 AM UTC 24 163997108 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.3684515594 Aug 29 10:58:00 AM UTC 24 Aug 29 10:58:06 AM UTC 24 1072298285 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2715418243 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:07 AM UTC 24 112773154 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3831887771 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:07 AM UTC 24 77412372 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.3682383543 Aug 29 10:57:59 AM UTC 24 Aug 29 10:58:07 AM UTC 24 1641420368 ps
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T273 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.570056279 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:07 AM UTC 24 109527286 ps
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T275 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3497050736 Aug 29 10:58:02 AM UTC 24 Aug 29 10:58:07 AM UTC 24 301574669 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2390789832 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:07 AM UTC 24 161152009 ps
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T281 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.578952077 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:08 AM UTC 24 300150813 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.844151555 Aug 29 10:57:29 AM UTC 24 Aug 29 10:58:08 AM UTC 24 12861708903 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2210826449 Aug 29 10:57:35 AM UTC 24 Aug 29 10:58:09 AM UTC 24 3676731210 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.2845185215 Aug 29 10:57:49 AM UTC 24 Aug 29 10:58:10 AM UTC 24 6307873406 ps
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T285 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.1455857502 Aug 29 10:58:01 AM UTC 24 Aug 29 10:58:11 AM UTC 24 1749628928 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2982199647 Aug 29 10:58:02 AM UTC 24 Aug 29 10:58:12 AM UTC 24 205743733 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.3777661004 Aug 29 10:58:04 AM UTC 24 Aug 29 10:58:12 AM UTC 24 1490452389 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.181639955 Aug 29 10:58:06 AM UTC 24 Aug 29 10:58:12 AM UTC 24 123195097 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1353445344 Aug 29 10:58:06 AM UTC 24 Aug 29 10:58:12 AM UTC 24 128611404 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.616274074 Aug 29 10:58:09 AM UTC 24 Aug 29 10:58:13 AM UTC 24 120908966 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3375830043 Aug 29 10:58:06 AM UTC 24 Aug 29 10:58:12 AM UTC 24 95814033 ps
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