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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.40 99.24 100.00 99.83 99.46 98.77


Total test records in report: 613
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T56 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1666284550 Aug 29 10:59:16 AM UTC 24 Aug 29 10:59:22 AM UTC 24 228332931 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.600587768 Aug 29 10:59:12 AM UTC 24 Aug 29 10:59:24 AM UTC 24 804838554 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3329747645 Aug 29 10:59:21 AM UTC 24 Aug 29 10:59:26 AM UTC 24 146249577 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.195619045 Aug 29 10:59:24 AM UTC 24 Aug 29 10:59:27 AM UTC 24 71153430 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1668843453 Aug 29 10:59:24 AM UTC 24 Aug 29 10:59:27 AM UTC 24 149485984 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.510788410 Aug 29 10:59:30 AM UTC 24 Aug 29 10:59:34 AM UTC 24 482317351 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3828019828 Aug 29 10:59:14 AM UTC 24 Aug 29 10:59:27 AM UTC 24 156082051 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1643990838 Aug 29 10:59:12 AM UTC 24 Aug 29 10:59:27 AM UTC 24 136909498 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2456345718 Aug 29 10:59:21 AM UTC 24 Aug 29 10:59:27 AM UTC 24 418067437 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1277436496 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:28 AM UTC 24 89860024 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1181512726 Aug 29 10:59:24 AM UTC 24 Aug 29 10:59:28 AM UTC 24 176315474 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.274715590 Aug 29 10:59:22 AM UTC 24 Aug 29 10:59:28 AM UTC 24 92533428 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3666300601 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:28 AM UTC 24 126483225 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3938118766 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:28 AM UTC 24 131775512 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3652505474 Aug 29 10:59:17 AM UTC 24 Aug 29 10:59:28 AM UTC 24 190533654 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.618117755 Aug 29 10:59:24 AM UTC 24 Aug 29 10:59:29 AM UTC 24 471825446 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.537552884 Aug 29 10:59:25 AM UTC 24 Aug 29 10:59:29 AM UTC 24 863528736 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.756852541 Aug 29 10:59:12 AM UTC 24 Aug 29 10:59:29 AM UTC 24 179824680 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3521016704 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:29 AM UTC 24 159874748 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1865209256 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:34 AM UTC 24 653086867 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2121663341 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:29 AM UTC 24 306951819 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3376224700 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:29 AM UTC 24 117107688 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.2083747395 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:29 AM UTC 24 72072883 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.73065412 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:30 AM UTC 24 771406138 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4280878666 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:30 AM UTC 24 149788979 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.829984465 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:30 AM UTC 24 197651005 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2493964454 Aug 29 10:59:12 AM UTC 24 Aug 29 10:59:30 AM UTC 24 922074238 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2572187277 Aug 29 10:59:25 AM UTC 24 Aug 29 10:59:30 AM UTC 24 542874367 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3195782559 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:30 AM UTC 24 202330551 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4078576035 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:30 AM UTC 24 114898074 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3229214202 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:30 AM UTC 24 417996209 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1386640018 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:30 AM UTC 24 75790345 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3548811614 Aug 29 10:59:24 AM UTC 24 Aug 29 10:59:30 AM UTC 24 803455752 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2087591169 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 58151156 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3238653756 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 143613679 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1353269135 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 124818921 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3927547226 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 81650815 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2346511968 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 66206104 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.1978946883 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:31 AM UTC 24 442942780 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.720544411 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 54567634 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.260046806 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 125868726 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3483759375 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 149693191 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2987768957 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:31 AM UTC 24 166287743 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.126745800 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:32 AM UTC 24 136278186 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4070564539 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:32 AM UTC 24 217914417 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1480405316 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:32 AM UTC 24 170828546 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.4170723744 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:32 AM UTC 24 254317490 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3428317600 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:32 AM UTC 24 160582760 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2521100812 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:32 AM UTC 24 55993196 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1188626124 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 83286138 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2399837694 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 113236043 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1081660368 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 69151058 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2038000844 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 113451999 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2594079554 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 148122455 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3931730044 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:33 AM UTC 24 938294140 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2272295722 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 108037257 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.996521784 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:33 AM UTC 24 872075587 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1414546489 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 62110272 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.47445398 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:33 AM UTC 24 875373839 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.247154388 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 106898153 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.784845046 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 153618628 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2999140574 Aug 29 10:59:30 AM UTC 24 Aug 29 10:59:33 AM UTC 24 173320826 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4288409544 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:33 AM UTC 24 176818782 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158172592 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:34 AM UTC 24 264617753 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.1059382022 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:34 AM UTC 24 265152262 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2729335424 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:34 AM UTC 24 459618495 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2933436855 Aug 29 10:59:29 AM UTC 24 Aug 29 10:59:34 AM UTC 24 1043584437 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3691891755 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:34 AM UTC 24 787712763 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1701029671 Aug 29 10:59:32 AM UTC 24 Aug 29 10:59:35 AM UTC 24 189035547 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2894227984 Aug 29 10:59:23 AM UTC 24 Aug 29 10:59:35 AM UTC 24 1545423714 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.2236416485 Aug 29 10:59:30 AM UTC 24 Aug 29 10:59:35 AM UTC 24 519869463 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2815850948 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:35 AM UTC 24 231613136 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1794203961 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:35 AM UTC 24 66949506 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2861004088 Aug 29 10:59:31 AM UTC 24 Aug 29 10:59:35 AM UTC 24 547748075 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2406289668 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 71533750 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.4048752569 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 65572466 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2830462632 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 147700894 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3346732896 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 73616109 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2224052897 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 86916064 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2540413134 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 196784106 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3867092386 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 114069818 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.458262603 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 171870079 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4275695735 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 156605855 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4031526376 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 768580200 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.413214859 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:36 AM UTC 24 107786941 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3443690193 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:37 AM UTC 24 258867231 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1424725955 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:37 AM UTC 24 114874671 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.34017977 Aug 29 10:59:27 AM UTC 24 Aug 29 10:59:37 AM UTC 24 1570918515 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.578551987 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:38 AM UTC 24 802988612 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3198418243 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:38 AM UTC 24 940922772 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2707173983 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:38 AM UTC 24 198833654 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1380081925 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:38 AM UTC 24 953695995 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2491249296 Aug 29 10:59:32 AM UTC 24 Aug 29 10:59:38 AM UTC 24 598574542 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3220667022 Aug 29 10:59:33 AM UTC 24 Aug 29 10:59:56 AM UTC 24 119320002 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.848352425 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 143234896 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2569368035 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 73027913 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.798311928 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 75660553 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1773440407 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 68648366 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1168989475 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 78124319 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3360248648 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 149490530 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2222651693 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 163909492 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.279368584 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:57 AM UTC 24 182493807 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2246395609 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 122949894 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.478227309 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 114663397 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.390227756 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 149871293 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2102354568 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 465369291 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3100223576 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 463362567 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1071963677 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 215985394 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.964006826 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 269666292 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.505660531 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:58 AM UTC 24 190405284 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.3703844828 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:59 AM UTC 24 363774906 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3079029451 Aug 29 10:59:35 AM UTC 24 Aug 29 10:59:59 AM UTC 24 804364920 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2565459726 Aug 29 10:59:35 AM UTC 24 Aug 29 11:00:00 AM UTC 24 903705800 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.259242175
Short name T10
Test name
Test status
Simulation time 119397651 ps
CPU time 1.22 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:37 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259242175 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.259242175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.155765294
Short name T6
Test name
Test status
Simulation time 145739752 ps
CPU time 1.62 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155765294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.155765294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2465703247
Short name T55
Test name
Test status
Simulation time 132861345 ps
CPU time 1.26 seconds
Started Aug 29 10:59:16 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2465703247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w
ith_rand_reset.2465703247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.956573408
Short name T35
Test name
Test status
Simulation time 8803766460 ps
CPU time 12.34 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:23 AM UTC 24
Peak memory 242116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956573408 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.956573408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.1540423226
Short name T49
Test name
Test status
Simulation time 3136341819 ps
CPU time 12.07 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:33 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540423226 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1540423226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3397103553
Short name T36
Test name
Test status
Simulation time 1966628948 ps
CPU time 7.17 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 242400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397103553 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3397103553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.3594302605
Short name T97
Test name
Test status
Simulation time 1932877375 ps
CPU time 6.88 seconds
Started Aug 29 10:57:25 AM UTC 24
Finished Aug 29 10:57:33 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594302605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.3594302605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.510788410
Short name T62
Test name
Test status
Simulation time 482317351 ps
CPU time 2.24 seconds
Started Aug 29 10:59:30 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510788410 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.510788410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.3412140174
Short name T50
Test name
Test status
Simulation time 172078061 ps
CPU time 1 seconds
Started Aug 29 10:57:18 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412140174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.3412140174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1306959805
Short name T86
Test name
Test status
Simulation time 164122226 ps
CPU time 0.99 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306959805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1306959805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.996521784
Short name T77
Test name
Test status
Simulation time 872075587 ps
CPU time 2.95 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996521784 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.996521784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.870781156
Short name T1
Test name
Test status
Simulation time 62027765 ps
CPU time 0.68 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870781156 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.870781156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1287665897
Short name T30
Test name
Test status
Simulation time 1960385821 ps
CPU time 6.91 seconds
Started Aug 29 10:57:33 AM UTC 24
Finished Aug 29 10:57:41 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287665897 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1287665897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.756852541
Short name T71
Test name
Test status
Simulation time 179824680 ps
CPU time 2.46 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 217748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756852541 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.756852541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4016887765
Short name T37
Test name
Test status
Simulation time 1971625794 ps
CPU time 7.28 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 241720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016887765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.4016887765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1666284550
Short name T56
Test name
Test status
Simulation time 228332931 ps
CPU time 1.36 seconds
Started Aug 29 10:59:16 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666284550 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.1666284550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1596153382
Short name T4
Test name
Test status
Simulation time 166071883 ps
CPU time 0.79 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596153382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1596153382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.607851346
Short name T9
Test name
Test status
Simulation time 1267996156 ps
CPU time 4.65 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607851346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.607851346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.3652505474
Short name T72
Test name
Test status
Simulation time 190533654 ps
CPU time 2.72 seconds
Started Aug 29 10:59:17 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652505474 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.3652505474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2565459726
Short name T79
Test name
Test status
Simulation time 903705800 ps
CPU time 3.02 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 11:00:00 AM UTC 24
Peak memory 208848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565459726 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.2565459726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3828019828
Short name T101
Test name
Test status
Simulation time 156082051 ps
CPU time 1.84 seconds
Started Aug 29 10:59:14 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828019828 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.3828019828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.600587768
Short name T57
Test name
Test status
Simulation time 804838554 ps
CPU time 4.11 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:24 AM UTC 24
Peak memory 208920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600587768 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.600587768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1643990838
Short name T536
Test name
Test status
Simulation time 136909498 ps
CPU time 0.79 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643990838 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.1643990838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.4099723713
Short name T54
Test name
Test status
Simulation time 72281237 ps
CPU time 0.68 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:21 AM UTC 24
Peak memory 208040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099723713 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.4099723713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2493964454
Short name T75
Test name
Test status
Simulation time 922074238 ps
CPU time 3.25 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493964454 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.2493964454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3521016704
Short name T540
Test name
Test status
Simulation time 159874748 ps
CPU time 1.9 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 207724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521016704 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.3521016704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.2894227984
Short name T574
Test name
Test status
Simulation time 1545423714 ps
CPU time 8.08 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 208844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894227984 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.2894227984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3329747645
Short name T58
Test name
Test status
Simulation time 146249577 ps
CPU time 0.88 seconds
Started Aug 29 10:59:21 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329747645 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3329747645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3938118766
Short name T65
Test name
Test status
Simulation time 131775512 ps
CPU time 1.36 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 217496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3938118766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w
ith_rand_reset.3938118766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.274715590
Short name T538
Test name
Test status
Simulation time 92533428 ps
CPU time 0.94 seconds
Started Aug 29 10:59:22 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274715590 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.274715590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3666300601
Short name T114
Test name
Test status
Simulation time 126483225 ps
CPU time 1.28 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 207768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666300601 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.3666300601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2456345718
Short name T63
Test name
Test status
Simulation time 418067437 ps
CPU time 1.66 seconds
Started Aug 29 10:59:21 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456345718 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.2456345718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.4288409544
Short name T568
Test name
Test status
Simulation time 176818782 ps
CPU time 1.45 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4288409544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_
with_rand_reset.4288409544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.1081660368
Short name T560
Test name
Test status
Simulation time 69151058 ps
CPU time 0.87 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081660368 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1081660368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158172592
Short name T569
Test name
Test status
Simulation time 264617753 ps
CPU time 1.53 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 207788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158172592 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.2158172592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.247154388
Short name T565
Test name
Test status
Simulation time 106898153 ps
CPU time 1.36 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 224912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247154388 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.247154388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3691891755
Short name T130
Test name
Test status
Simulation time 787712763 ps
CPU time 2.62 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691891755 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.3691891755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1701029671
Short name T573
Test name
Test status
Simulation time 189035547 ps
CPU time 1.15 seconds
Started Aug 29 10:59:32 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1701029671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_
with_rand_reset.1701029671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.1414546489
Short name T564
Test name
Test status
Simulation time 62110272 ps
CPU time 0.94 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414546489 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.1414546489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.784845046
Short name T566
Test name
Test status
Simulation time 153618628 ps
CPU time 0.99 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784845046 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.784845046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2861004088
Short name T578
Test name
Test status
Simulation time 547748075 ps
CPU time 3.34 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 217516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861004088 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2861004088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.2729335424
Short name T571
Test name
Test status
Simulation time 459618495 ps
CPU time 1.76 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729335424 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.2729335424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2540413134
Short name T584
Test name
Test status
Simulation time 196784106 ps
CPU time 1.39 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2540413134 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_
with_rand_reset.2540413134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1794203961
Short name T577
Test name
Test status
Simulation time 66949506 ps
CPU time 0.83 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 206896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794203961 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1794203961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2815850948
Short name T576
Test name
Test status
Simulation time 231613136 ps
CPU time 1.34 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815850948 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.2815850948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.2491249296
Short name T594
Test name
Test status
Simulation time 598574542 ps
CPU time 3.66 seconds
Started Aug 29 10:59:32 AM UTC 24
Finished Aug 29 10:59:38 AM UTC 24
Peak memory 217248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491249296 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.2491249296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.4031526376
Short name T131
Test name
Test status
Simulation time 768580200 ps
CPU time 2.62 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031526376 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.4031526376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.2830462632
Short name T581
Test name
Test status
Simulation time 147700894 ps
CPU time 1 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2830462632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_
with_rand_reset.2830462632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2406289668
Short name T579
Test name
Test status
Simulation time 71533750 ps
CPU time 0.82 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406289668 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2406289668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2224052897
Short name T583
Test name
Test status
Simulation time 86916064 ps
CPU time 1 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224052897 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2224052897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3443690193
Short name T589
Test name
Test status
Simulation time 258867231 ps
CPU time 1.87 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:37 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443690193 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.3443690193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.3198418243
Short name T78
Test name
Test status
Simulation time 940922772 ps
CPU time 2.91 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:38 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198418243 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.3198418243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.458262603
Short name T586
Test name
Test status
Simulation time 171870079 ps
CPU time 1.08 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 217552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=458262603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_w
ith_rand_reset.458262603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3346732896
Short name T582
Test name
Test status
Simulation time 73616109 ps
CPU time 0.78 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346732896 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.3346732896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.4275695735
Short name T587
Test name
Test status
Simulation time 156605855 ps
CPU time 1.12 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275695735 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.4275695735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.413214859
Short name T588
Test name
Test status
Simulation time 107786941 ps
CPU time 1.42 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413214859 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.413214859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.578551987
Short name T134
Test name
Test status
Simulation time 802988612 ps
CPU time 2.61 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:38 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578551987 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.578551987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3220667022
Short name T595
Test name
Test status
Simulation time 119320002 ps
CPU time 0.83 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:56 AM UTC 24
Peak memory 207836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3220667022 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_
with_rand_reset.3220667022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.4048752569
Short name T580
Test name
Test status
Simulation time 65572466 ps
CPU time 0.73 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048752569 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.4048752569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3867092386
Short name T585
Test name
Test status
Simulation time 114069818 ps
CPU time 0.91 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 207828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867092386 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.3867092386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.2707173983
Short name T592
Test name
Test status
Simulation time 198833654 ps
CPU time 2.87 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:38 AM UTC 24
Peak memory 217524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707173983 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.2707173983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1380081925
Short name T593
Test name
Test status
Simulation time 953695995 ps
CPU time 2.96 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:38 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380081925 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.1380081925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2222651693
Short name T602
Test name
Test status
Simulation time 163909492 ps
CPU time 1.3 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2222651693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_
with_rand_reset.2222651693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2569368035
Short name T597
Test name
Test status
Simulation time 73027913 ps
CPU time 0.76 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569368035 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.2569368035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.848352425
Short name T596
Test name
Test status
Simulation time 143234896 ps
CPU time 0.99 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848352425 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.848352425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.1424725955
Short name T590
Test name
Test status
Simulation time 114874671 ps
CPU time 1.38 seconds
Started Aug 29 10:59:33 AM UTC 24
Finished Aug 29 10:59:37 AM UTC 24
Peak memory 217624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424725955 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.1424725955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2102354568
Short name T607
Test name
Test status
Simulation time 465369291 ps
CPU time 1.79 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102354568 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.2102354568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.279368584
Short name T603
Test name
Test status
Simulation time 182493807 ps
CPU time 1.33 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=279368584 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_w
ith_rand_reset.279368584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.798311928
Short name T598
Test name
Test status
Simulation time 75660553 ps
CPU time 0.86 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798311928 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.798311928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3360248648
Short name T601
Test name
Test status
Simulation time 149490530 ps
CPU time 1.23 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360248648 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.3360248648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.964006826
Short name T610
Test name
Test status
Simulation time 269666292 ps
CPU time 1.97 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 217648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964006826 -assert nopostproc +UVM_TESTNAME=rstmgr_ba
se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/r
stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.964006826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.3100223576
Short name T608
Test name
Test status
Simulation time 463362567 ps
CPU time 1.92 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 207704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100223576 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.3100223576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2246395609
Short name T604
Test name
Test status
Simulation time 122949894 ps
CPU time 1.11 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 217568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2246395609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_
with_rand_reset.2246395609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1773440407
Short name T599
Test name
Test status
Simulation time 68648366 ps
CPU time 0.86 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773440407 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1773440407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.478227309
Short name T605
Test name
Test status
Simulation time 114663397 ps
CPU time 1.25 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 207488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478227309 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.478227309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.3703844828
Short name T612
Test name
Test status
Simulation time 363774906 ps
CPU time 2.45 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703844828 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.3703844828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3079029451
Short name T613
Test name
Test status
Simulation time 804364920 ps
CPU time 2.89 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:59 AM UTC 24
Peak memory 208852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079029451 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.3079029451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.505660531
Short name T611
Test name
Test status
Simulation time 190405284 ps
CPU time 1.82 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 217712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=505660531 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_w
ith_rand_reset.505660531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1168989475
Short name T600
Test name
Test status
Simulation time 78124319 ps
CPU time 0.72 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:57 AM UTC 24
Peak memory 207712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168989475 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1168989475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.390227756
Short name T606
Test name
Test status
Simulation time 149871293 ps
CPU time 1.23 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 207760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390227756 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.390227756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1071963677
Short name T609
Test name
Test status
Simulation time 215985394 ps
CPU time 1.59 seconds
Started Aug 29 10:59:35 AM UTC 24
Finished Aug 29 10:59:58 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071963677 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1071963677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.618117755
Short name T539
Test name
Test status
Simulation time 471825446 ps
CPU time 2.57 seconds
Started Aug 29 10:59:24 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 208768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618117755 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.618117755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3548811614
Short name T545
Test name
Test status
Simulation time 803455752 ps
CPU time 4.51 seconds
Started Aug 29 10:59:24 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548811614 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.3548811614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1277436496
Short name T537
Test name
Test status
Simulation time 89860024 ps
CPU time 0.72 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277436496 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1277436496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.1181512726
Short name T64
Test name
Test status
Simulation time 176315474 ps
CPU time 1.58 seconds
Started Aug 29 10:59:24 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 217688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1181512726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_w
ith_rand_reset.1181512726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.195619045
Short name T113
Test name
Test status
Simulation time 71153430 ps
CPU time 0.8 seconds
Started Aug 29 10:59:24 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 205700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195619045 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.195619045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.1668843453
Short name T70
Test name
Test status
Simulation time 149485984 ps
CPU time 0.99 seconds
Started Aug 29 10:59:24 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 206260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668843453 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.1668843453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.2121663341
Short name T74
Test name
Test status
Simulation time 306951819 ps
CPU time 2.12 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 217784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121663341 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2121663341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.73065412
Short name T81
Test name
Test status
Simulation time 771406138 ps
CPU time 2.61 seconds
Started Aug 29 10:59:23 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73065412 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.73065412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.4078576035
Short name T544
Test name
Test status
Simulation time 114898074 ps
CPU time 1.51 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078576035 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.4078576035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.34017977
Short name T591
Test name
Test status
Simulation time 1570918515 ps
CPU time 8.35 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:37 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34017977 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.34017977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3376224700
Short name T541
Test name
Test status
Simulation time 117107688 ps
CPU time 0.88 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376224700 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3376224700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.3195782559
Short name T543
Test name
Test status
Simulation time 202330551 ps
CPU time 1.54 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 219612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3195782559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w
ith_rand_reset.3195782559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.2083747395
Short name T115
Test name
Test status
Simulation time 72072883 ps
CPU time 0.97 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083747395 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.2083747395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.829984465
Short name T116
Test name
Test status
Simulation time 197651005 ps
CPU time 1.41 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829984465 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.829984465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2572187277
Short name T80
Test name
Test status
Simulation time 542874367 ps
CPU time 3.67 seconds
Started Aug 29 10:59:25 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 217728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572187277 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.2572187277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.537552884
Short name T69
Test name
Test status
Simulation time 863528736 ps
CPU time 2.48 seconds
Started Aug 29 10:59:25 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537552884 -assert nopostproc +UVM_TESTNA
ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.537552884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2987768957
Short name T551
Test name
Test status
Simulation time 166287743 ps
CPU time 1.75 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987768957 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.2987768957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2933436855
Short name T572
Test name
Test status
Simulation time 1043584437 ps
CPU time 4.64 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933436855 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.2933436855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4280878666
Short name T542
Test name
Test status
Simulation time 149788979 ps
CPU time 1.12 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280878666 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.4280878666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3238653756
Short name T82
Test name
Test status
Simulation time 143613679 ps
CPU time 1.15 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3238653756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w
ith_rand_reset.3238653756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1386640018
Short name T117
Test name
Test status
Simulation time 75790345 ps
CPU time 0.79 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386640018 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1386640018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3927547226
Short name T119
Test name
Test status
Simulation time 81650815 ps
CPU time 1.2 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927547226 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.3927547226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.1978946883
Short name T548
Test name
Test status
Simulation time 442942780 ps
CPU time 2.66 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 217652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978946883 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.1978946883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3229214202
Short name T76
Test name
Test status
Simulation time 417996209 ps
CPU time 1.77 seconds
Started Aug 29 10:59:27 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229214202 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3229214202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.1353269135
Short name T546
Test name
Test status
Simulation time 124818921 ps
CPU time 1.1 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1353269135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w
ith_rand_reset.1353269135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2087591169
Short name T118
Test name
Test status
Simulation time 58151156 ps
CPU time 0.98 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087591169 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2087591169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.260046806
Short name T549
Test name
Test status
Simulation time 125868726 ps
CPU time 1.25 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260046806 -assert nopostproc +U
VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.260046806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1480405316
Short name T554
Test name
Test status
Simulation time 170828546 ps
CPU time 2.17 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 225204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480405316 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1480405316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.47445398
Short name T133
Test name
Test status
Simulation time 875373839 ps
CPU time 3.24 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47445398 -assert nopostproc +UVM_TESTNAM
E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.47445398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.126745800
Short name T552
Test name
Test status
Simulation time 136278186 ps
CPU time 1.65 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 217656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=126745800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_wi
th_rand_reset.126745800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.2346511968
Short name T547
Test name
Test status
Simulation time 66206104 ps
CPU time 0.87 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346511968 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2346511968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3483759375
Short name T550
Test name
Test status
Simulation time 149693191 ps
CPU time 1.27 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483759375 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.3483759375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.4170723744
Short name T555
Test name
Test status
Simulation time 254317490 ps
CPU time 2.16 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 217836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170723744 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.4170723744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3931730044
Short name T132
Test name
Test status
Simulation time 938294140 ps
CPU time 2.88 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 208760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931730044 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.3931730044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2999140574
Short name T567
Test name
Test status
Simulation time 173320826 ps
CPU time 1.67 seconds
Started Aug 29 10:59:30 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 217708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2999140574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w
ith_rand_reset.2999140574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.720544411
Short name T120
Test name
Test status
Simulation time 54567634 ps
CPU time 0.91 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 207708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720544411 -assert nopostproc +UVM_TESTNAME=rstmgr
_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.720544411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.4070564539
Short name T553
Test name
Test status
Simulation time 217914417 ps
CPU time 1.62 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 207768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070564539 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.4070564539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3428317600
Short name T556
Test name
Test status
Simulation time 160582760 ps
CPU time 2.18 seconds
Started Aug 29 10:59:29 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 217772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428317600 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.3428317600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.2399837694
Short name T559
Test name
Test status
Simulation time 113236043 ps
CPU time 1.14 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2399837694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w
ith_rand_reset.2399837694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.2521100812
Short name T557
Test name
Test status
Simulation time 55993196 ps
CPU time 0.73 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521100812 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.2521100812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.2272295722
Short name T563
Test name
Test status
Simulation time 108037257 ps
CPU time 1.3 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272295722 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.2272295722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.2236416485
Short name T575
Test name
Test status
Simulation time 519869463 ps
CPU time 3.24 seconds
Started Aug 29 10:59:30 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 225104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236416485 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2236416485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2038000844
Short name T561
Test name
Test status
Simulation time 113451999 ps
CPU time 1 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2038000844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_w
ith_rand_reset.2038000844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.1188626124
Short name T558
Test name
Test status
Simulation time 83286138 ps
CPU time 1 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188626124 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1188626124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2594079554
Short name T562
Test name
Test status
Simulation time 148122455 ps
CPU time 1.07 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594079554 -assert nopostproc +
UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2594079554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.1059382022
Short name T570
Test name
Test status
Simulation time 265152262 ps
CPU time 1.88 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 219616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059382022 -assert nopostproc +UVM_TESTNAME=rstmgr_b
ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1059382022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.1865209256
Short name T73
Test name
Test status
Simulation time 653086867 ps
CPU time 2.21 seconds
Started Aug 29 10:59:31 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865209256 -assert nopostproc +UVM_TESTN
AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.1865209256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2663329346
Short name T84
Test name
Test status
Simulation time 301456480 ps
CPU time 1.27 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663329346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2663329346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.498474346
Short name T96
Test name
Test status
Simulation time 1748303310 ps
CPU time 6.28 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:32 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498474346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.498474346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.600842630
Short name T139
Test name
Test status
Simulation time 101244620 ps
CPU time 0.91 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600842630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.600842630
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.3568118370
Short name T11
Test name
Test status
Simulation time 253900021 ps
CPU time 1.3 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568118370 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.3568118370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.3823646455
Short name T98
Test name
Test status
Simulation time 7172994870 ps
CPU time 23.44 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:34 AM UTC 24
Peak memory 218236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823646455 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3823646455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.2757027797
Short name T7
Test name
Test status
Simulation time 141416873 ps
CPU time 1.64 seconds
Started Aug 29 10:57:08 AM UTC 24
Finished Aug 29 10:57:18 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757027797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2757027797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.2417746070
Short name T48
Test name
Test status
Simulation time 55200630 ps
CPU time 0.78 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417746070 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2417746070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.4162082344
Short name T140
Test name
Test status
Simulation time 300492801 ps
CPU time 1.05 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 237196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162082344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4162082344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.987254548
Short name T2
Test name
Test status
Simulation time 188785913 ps
CPU time 0.89 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987254548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.987254548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1142996168
Short name T8
Test name
Test status
Simulation time 1401007175 ps
CPU time 4.93 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142996168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1142996168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.160202101
Short name T60
Test name
Test status
Simulation time 16639754845 ps
CPU time 25 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 241948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160202101 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.160202101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.647858853
Short name T12
Test name
Test status
Simulation time 101105454 ps
CPU time 0.88 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647858853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.647858853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.4116268282
Short name T5
Test name
Test status
Simulation time 203440013 ps
CPU time 1.28 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116268282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.4116268282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4176425491
Short name T110
Test name
Test status
Simulation time 2726057808 ps
CPU time 10.48 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:39 AM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176425491 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.4176425491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1480143083
Short name T3
Test name
Test status
Simulation time 149791678 ps
CPU time 0.99 seconds
Started Aug 29 10:57:12 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480143083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1480143083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.1314923127
Short name T210
Test name
Test status
Simulation time 73064226 ps
CPU time 1 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314923127 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.1314923127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1648286830
Short name T265
Test name
Test status
Simulation time 2440374734 ps
CPU time 9.19 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:06 AM UTC 24
Peak memory 242448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648286830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1648286830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.1094049193
Short name T206
Test name
Test status
Simulation time 301698970 ps
CPU time 1.01 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094049193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.1094049193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.3937061413
Short name T202
Test name
Test status
Simulation time 145367611 ps
CPU time 1.23 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937061413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.3937061413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.3294330064
Short name T233
Test name
Test status
Simulation time 1254372963 ps
CPU time 5.06 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 209228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294330064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.3294330064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.1745522132
Short name T215
Test name
Test status
Simulation time 187785735 ps
CPU time 1.44 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745522132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.1745522132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3936962373
Short name T211
Test name
Test status
Simulation time 265788262 ps
CPU time 1.42 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936962373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.3936962373
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.2210826449
Short name T282
Test name
Test status
Simulation time 3676731210 ps
CPU time 12.91 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:09 AM UTC 24
Peak memory 209344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210826449 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.2210826449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.1584021248
Short name T203
Test name
Test status
Simulation time 135857770 ps
CPU time 1.87 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584021248 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.1584021248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.1024942083
Short name T216
Test name
Test status
Simulation time 210776211 ps
CPU time 1.49 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 206204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024942083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.1024942083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.1850502687
Short name T176
Test name
Test status
Simulation time 79192593 ps
CPU time 1.09 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850502687 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1850502687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.845565956
Short name T251
Test name
Test status
Simulation time 1270034853 ps
CPU time 5.67 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845565956 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.845565956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.446498344
Short name T219
Test name
Test status
Simulation time 302278052 ps
CPU time 1.25 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446498344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.446498344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3317433931
Short name T204
Test name
Test status
Simulation time 192997176 ps
CPU time 0.83 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317433931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.3317433931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.2394987717
Short name T249
Test name
Test status
Simulation time 1373300141 ps
CPU time 5.36 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394987717 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.2394987717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1429923456
Short name T218
Test name
Test status
Simulation time 170615091 ps
CPU time 1.14 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429923456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.1429923456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.967136201
Short name T195
Test name
Test status
Simulation time 189693140 ps
CPU time 1.53 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967136201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.967136201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.2380215256
Short name T389
Test name
Test status
Simulation time 11065168384 ps
CPU time 34.33 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:31 AM UTC 24
Peak memory 209340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380215256 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.2380215256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1989560720
Short name T225
Test name
Test status
Simulation time 405317322 ps
CPU time 2.04 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:59 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989560720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.1989560720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.156878000
Short name T199
Test name
Test status
Simulation time 68484358 ps
CPU time 0.69 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 207816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156878000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.156878000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.1102853873
Short name T154
Test name
Test status
Simulation time 75160749 ps
CPU time 0.69 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102853873 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.1102853873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.3834354771
Short name T39
Test name
Test status
Simulation time 1952252866 ps
CPU time 6.31 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 241944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834354771 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3834354771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.1208610186
Short name T157
Test name
Test status
Simulation time 301667442 ps
CPU time 1.04 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 237596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208610186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.1208610186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3189868147
Short name T213
Test name
Test status
Simulation time 103279167 ps
CPU time 0.87 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189868147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3189868147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.2538842861
Short name T104
Test name
Test status
Simulation time 895697189 ps
CPU time 3.97 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:45 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538842861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2538842861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1607965552
Short name T155
Test name
Test status
Simulation time 103358828 ps
CPU time 0.91 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 207960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607965552 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.1607965552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3678408125
Short name T214
Test name
Test status
Simulation time 258459436 ps
CPU time 1.55 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678408125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3678408125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.697246138
Short name T239
Test name
Test status
Simulation time 5340279582 ps
CPU time 20.17 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 217344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697246138 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.697246138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.1317214065
Short name T163
Test name
Test status
Simulation time 133075439 ps
CPU time 1.52 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 216864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317214065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.1317214065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.2510424838
Short name T156
Test name
Test status
Simulation time 150606425 ps
CPU time 1.07 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 206616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510424838 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.2510424838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2796091045
Short name T160
Test name
Test status
Simulation time 96248992 ps
CPU time 0.71 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796091045 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.2796091045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.4213302462
Short name T31
Test name
Test status
Simulation time 2450932373 ps
CPU time 8.34 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:57:50 AM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213302462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.4213302462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.2955829886
Short name T162
Test name
Test status
Simulation time 303403800 ps
CPU time 1.03 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 237264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955829886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.2955829886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2242710665
Short name T159
Test name
Test status
Simulation time 173315127 ps
CPU time 0.87 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 207848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242710665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2242710665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.3720129395
Short name T165
Test name
Test status
Simulation time 899119161 ps
CPU time 3.68 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:45 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720129395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.3720129395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2205517922
Short name T181
Test name
Test status
Simulation time 98275069 ps
CPU time 0.92 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205517922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2205517922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.3978398609
Short name T161
Test name
Test status
Simulation time 119789168 ps
CPU time 1.04 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978398609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.3978398609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.2066902891
Short name T124
Test name
Test status
Simulation time 11246709106 ps
CPU time 34.14 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:58:26 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066902891 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2066902891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.736114577
Short name T164
Test name
Test status
Simulation time 325792196 ps
CPU time 1.88 seconds
Started Aug 29 10:57:39 AM UTC 24
Finished Aug 29 10:57:43 AM UTC 24
Peak memory 207676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736114577 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.736114577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2862822870
Short name T158
Test name
Test status
Simulation time 107738799 ps
CPU time 0.8 seconds
Started Aug 29 10:57:37 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862822870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2862822870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.971609797
Short name T193
Test name
Test status
Simulation time 57446289 ps
CPU time 0.74 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:56 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971609797 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.971609797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.577136065
Short name T32
Test name
Test status
Simulation time 2261794647 ps
CPU time 6.87 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:53 AM UTC 24
Peak memory 241788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577136065 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.577136065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2627346944
Short name T169
Test name
Test status
Simulation time 302068949 ps
CPU time 0.98 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627346944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2627346944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.4101792490
Short name T166
Test name
Test status
Simulation time 190288305 ps
CPU time 0.85 seconds
Started Aug 29 10:57:41 AM UTC 24
Finished Aug 29 10:57:46 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101792490 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.4101792490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1511268473
Short name T174
Test name
Test status
Simulation time 1538842043 ps
CPU time 4.98 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:51 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511268473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1511268473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.3942917046
Short name T167
Test name
Test status
Simulation time 95606137 ps
CPU time 0.9 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:46 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942917046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.3942917046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.4069956124
Short name T168
Test name
Test status
Simulation time 111693125 ps
CPU time 1.07 seconds
Started Aug 29 10:57:41 AM UTC 24
Finished Aug 29 10:57:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069956124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.4069956124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.278421992
Short name T173
Test name
Test status
Simulation time 656280468 ps
CPU time 2.61 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:48 AM UTC 24
Peak memory 209100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278421992 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.278421992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1028295820
Short name T172
Test name
Test status
Simulation time 358541332 ps
CPU time 2.23 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:48 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028295820 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1028295820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.379294020
Short name T170
Test name
Test status
Simulation time 210410459 ps
CPU time 1.24 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379294020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.379294020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.4060607156
Short name T177
Test name
Test status
Simulation time 82405725 ps
CPU time 0.73 seconds
Started Aug 29 10:57:47 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060607156 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.4060607156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.4075773395
Short name T40
Test name
Test status
Simulation time 1272669953 ps
CPU time 5.35 seconds
Started Aug 29 10:57:47 AM UTC 24
Finished Aug 29 10:57:56 AM UTC 24
Peak memory 241232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075773395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4075773395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1247759383
Short name T179
Test name
Test status
Simulation time 302080683 ps
CPU time 1.05 seconds
Started Aug 29 10:57:47 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 237560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247759383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1247759383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3020576095
Short name T189
Test name
Test status
Simulation time 153291516 ps
CPU time 0.72 seconds
Started Aug 29 10:57:44 AM UTC 24
Finished Aug 29 10:57:54 AM UTC 24
Peak memory 207716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020576095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.3020576095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.1767989679
Short name T112
Test name
Test status
Simulation time 739290532 ps
CPU time 3.48 seconds
Started Aug 29 10:57:44 AM UTC 24
Finished Aug 29 10:57:49 AM UTC 24
Peak memory 209320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767989679 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.1767989679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.4212831331
Short name T178
Test name
Test status
Simulation time 112023805 ps
CPU time 0.94 seconds
Started Aug 29 10:57:47 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212831331 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.4212831331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.1020061800
Short name T171
Test name
Test status
Simulation time 253821721 ps
CPU time 1.28 seconds
Started Aug 29 10:57:43 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020061800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.1020061800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.3639496527
Short name T126
Test name
Test status
Simulation time 15654192206 ps
CPU time 50.77 seconds
Started Aug 29 10:57:47 AM UTC 24
Finished Aug 29 10:58:42 AM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639496527 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.3639496527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.15046218
Short name T191
Test name
Test status
Simulation time 155023426 ps
CPU time 1.7 seconds
Started Aug 29 10:57:44 AM UTC 24
Finished Aug 29 10:57:55 AM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15046218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.15046218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.2202638512
Short name T190
Test name
Test status
Simulation time 262282136 ps
CPU time 1.33 seconds
Started Aug 29 10:57:44 AM UTC 24
Finished Aug 29 10:57:54 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202638512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2202638512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.244440968
Short name T175
Test name
Test status
Simulation time 78356473 ps
CPU time 0.68 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:51 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244440968 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.244440968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.300649894
Short name T41
Test name
Test status
Simulation time 1969548567 ps
CPU time 7.26 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:59 AM UTC 24
Peak memory 241752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300649894 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.300649894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.3836828156
Short name T182
Test name
Test status
Simulation time 302358959 ps
CPU time 0.99 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836828156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.3836828156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.1053768205
Short name T180
Test name
Test status
Simulation time 199486289 ps
CPU time 0.94 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053768205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.1053768205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3126563104
Short name T106
Test name
Test status
Simulation time 967822937 ps
CPU time 3.84 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:55 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126563104 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3126563104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.473452051
Short name T183
Test name
Test status
Simulation time 170617983 ps
CPU time 1.05 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473452051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.473452051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.2540771651
Short name T184
Test name
Test status
Simulation time 208242182 ps
CPU time 1.4 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540771651 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.2540771651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.2845185215
Short name T122
Test name
Test status
Simulation time 6307873406 ps
CPU time 19.81 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:58:10 AM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845185215 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.2845185215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.3955761762
Short name T185
Test name
Test status
Simulation time 274357756 ps
CPU time 1.64 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:53 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955761762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3955761762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3698453372
Short name T137
Test name
Test status
Simulation time 260899421 ps
CPU time 1.28 seconds
Started Aug 29 10:57:49 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698453372 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3698453372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.1135004118
Short name T196
Test name
Test status
Simulation time 77036736 ps
CPU time 0.85 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135004118 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.1135004118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.3761439078
Short name T34
Test name
Test status
Simulation time 1263883437 ps
CPU time 5.7 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 242060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761439078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3761439078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3761545609
Short name T205
Test name
Test status
Simulation time 301108868 ps
CPU time 1.45 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761545609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3761545609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.1766087840
Short name T187
Test name
Test status
Simulation time 180150975 ps
CPU time 0.84 seconds
Started Aug 29 10:57:51 AM UTC 24
Finished Aug 29 10:57:53 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766087840 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.1766087840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.135797551
Short name T192
Test name
Test status
Simulation time 1402758410 ps
CPU time 5.36 seconds
Started Aug 29 10:57:51 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 209220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135797551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.135797551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.69030582
Short name T194
Test name
Test status
Simulation time 106736530 ps
CPU time 1.03 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69030582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.69030582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.1899690330
Short name T188
Test name
Test status
Simulation time 116152132 ps
CPU time 1.01 seconds
Started Aug 29 10:57:51 AM UTC 24
Finished Aug 29 10:57:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899690330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.1899690330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.2370902182
Short name T220
Test name
Test status
Simulation time 273029016 ps
CPU time 2.01 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 209184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370902182 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.2370902182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1881941661
Short name T207
Test name
Test status
Simulation time 124153058 ps
CPU time 1.67 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881941661 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.1881941661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.1029963756
Short name T186
Test name
Test status
Simulation time 84871945 ps
CPU time 0.76 seconds
Started Aug 29 10:57:51 AM UTC 24
Finished Aug 29 10:57:53 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029963756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1029963756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.807706362
Short name T221
Test name
Test status
Simulation time 92152528 ps
CPU time 0.81 seconds
Started Aug 29 10:57:56 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807706362 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.807706362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.1302449816
Short name T33
Test name
Test status
Simulation time 1269535537 ps
CPU time 5.36 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 241896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302449816 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.1302449816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3236695542
Short name T212
Test name
Test status
Simulation time 301824051 ps
CPU time 1.12 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236695542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3236695542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.78671198
Short name T198
Test name
Test status
Simulation time 102524682 ps
CPU time 1.02 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78671198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.78671198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.711723846
Short name T252
Test name
Test status
Simulation time 1571412174 ps
CPU time 6.39 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 209280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711723846 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.711723846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.1883660091
Short name T209
Test name
Test status
Simulation time 182574333 ps
CPU time 1.23 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 207936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883660091 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.1883660091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.226400238
Short name T200
Test name
Test status
Simulation time 123161354 ps
CPU time 1.27 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226400238 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.226400238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.2073050201
Short name T354
Test name
Test status
Simulation time 6692663835 ps
CPU time 26.8 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073050201 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.2073050201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.529255888
Short name T223
Test name
Test status
Simulation time 377819204 ps
CPU time 2.17 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529255888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.529255888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.217406740
Short name T201
Test name
Test status
Simulation time 153480949 ps
CPU time 1.21 seconds
Started Aug 29 10:57:54 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217406740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.217406740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3993450724
Short name T227
Test name
Test status
Simulation time 81164854 ps
CPU time 0.81 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:00 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993450724 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3993450724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3630430424
Short name T262
Test name
Test status
Simulation time 1275698996 ps
CPU time 5.37 seconds
Started Aug 29 10:57:58 AM UTC 24
Finished Aug 29 10:58:05 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630430424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3630430424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.1868468647
Short name T236
Test name
Test status
Simulation time 302324284 ps
CPU time 1.44 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868468647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.1868468647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.2155595666
Short name T222
Test name
Test status
Simulation time 158022444 ps
CPU time 0.89 seconds
Started Aug 29 10:57:56 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155595666 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.2155595666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.1936791530
Short name T254
Test name
Test status
Simulation time 1407802049 ps
CPU time 5.44 seconds
Started Aug 29 10:57:56 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936791530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.1936791530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.3435402728
Short name T229
Test name
Test status
Simulation time 175540335 ps
CPU time 1.08 seconds
Started Aug 29 10:57:58 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435402728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.3435402728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.878853227
Short name T224
Test name
Test status
Simulation time 223235759 ps
CPU time 1.36 seconds
Started Aug 29 10:57:56 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878853227 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.878853227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.2564215191
Short name T407
Test name
Test status
Simulation time 16509959166 ps
CPU time 55.95 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564215191 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.2564215191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.3755168366
Short name T248
Test name
Test status
Simulation time 352865630 ps
CPU time 2.15 seconds
Started Aug 29 10:57:58 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755168366 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.3755168366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.284781537
Short name T226
Test name
Test status
Simulation time 134776830 ps
CPU time 0.98 seconds
Started Aug 29 10:57:58 AM UTC 24
Finished Aug 29 10:58:00 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284781537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.284781537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2345946048
Short name T25
Test name
Test status
Simulation time 89105610 ps
CPU time 0.79 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345946048 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2345946048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.2025775106
Short name T14
Test name
Test status
Simulation time 301539984 ps
CPU time 1.01 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 237220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025775106 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.2025775106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3937176144
Short name T17
Test name
Test status
Simulation time 123123759 ps
CPU time 0.74 seconds
Started Aug 29 10:57:18 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937176144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3937176144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1153961947
Short name T94
Test name
Test status
Simulation time 839497484 ps
CPU time 4.06 seconds
Started Aug 29 10:57:18 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153961947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1153961947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.1994659625
Short name T61
Test name
Test status
Simulation time 16515212463 ps
CPU time 25.73 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:47 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994659625 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.1994659625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1050917658
Short name T23
Test name
Test status
Simulation time 246740125 ps
CPU time 1.42 seconds
Started Aug 29 10:57:17 AM UTC 24
Finished Aug 29 10:57:23 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050917658 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1050917658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.2375582693
Short name T87
Test name
Test status
Simulation time 432329767 ps
CPU time 2.35 seconds
Started Aug 29 10:57:18 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375582693 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.2375582693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.2323077
Short name T24
Test name
Test status
Simulation time 85454818 ps
CPU time 0.81 seconds
Started Aug 29 10:57:18 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 208308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r
stmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.2323077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.2991592789
Short name T231
Test name
Test status
Simulation time 67451644 ps
CPU time 0.81 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991592789 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2991592789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.2154538668
Short name T278
Test name
Test status
Simulation time 2245669763 ps
CPU time 7.69 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:08 AM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154538668 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.2154538668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.3385685927
Short name T244
Test name
Test status
Simulation time 301988255 ps
CPU time 1.53 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385685927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.3385685927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.2116319900
Short name T228
Test name
Test status
Simulation time 108563494 ps
CPU time 0.7 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:00 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116319900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.2116319900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.1040098877
Short name T261
Test name
Test status
Simulation time 1016627987 ps
CPU time 4.48 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:04 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040098877 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.1040098877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.1618793670
Short name T232
Test name
Test status
Simulation time 141155436 ps
CPU time 1.06 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618793670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.1618793670
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.1146418169
Short name T241
Test name
Test status
Simulation time 193078094 ps
CPU time 1.55 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146418169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.1146418169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.478214
Short name T318
Test name
Test status
Simulation time 5455995470 ps
CPU time 17.59 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478214 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.478214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.3232413335
Short name T247
Test name
Test status
Simulation time 113150324 ps
CPU time 1.78 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232413335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.3232413335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.2230386208
Short name T234
Test name
Test status
Simulation time 253374877 ps
CPU time 1.27 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230386208 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.2230386208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.636910051
Short name T238
Test name
Test status
Simulation time 60450480 ps
CPU time 0.96 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636910051 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.636910051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.3022371400
Short name T263
Test name
Test status
Simulation time 1281287514 ps
CPU time 5.15 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:05 AM UTC 24
Peak memory 241708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022371400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.3022371400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.2950323438
Short name T245
Test name
Test status
Simulation time 302036320 ps
CPU time 1.29 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950323438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.2950323438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.3835883662
Short name T235
Test name
Test status
Simulation time 176791451 ps
CPU time 1.06 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 207896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835883662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.3835883662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.528337205
Short name T260
Test name
Test status
Simulation time 762213164 ps
CPU time 3.67 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:04 AM UTC 24
Peak memory 209408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528337205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.528337205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3817102390
Short name T243
Test name
Test status
Simulation time 150066669 ps
CPU time 1.23 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817102390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3817102390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.641273598
Short name T242
Test name
Test status
Simulation time 123484766 ps
CPU time 1.24 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641273598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.641273598
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.4226761176
Short name T403
Test name
Test status
Simulation time 16011328621 ps
CPU time 54.75 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226761176 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.4226761176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.3259993901
Short name T256
Test name
Test status
Simulation time 361495208 ps
CPU time 2.64 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259993901 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.3259993901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.4193408686
Short name T240
Test name
Test status
Simulation time 170571658 ps
CPU time 1.14 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193408686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.4193408686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.2163966180
Short name T264
Test name
Test status
Simulation time 70774221 ps
CPU time 0.83 seconds
Started Aug 29 10:58:01 AM UTC 24
Finished Aug 29 10:58:05 AM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163966180 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.2163966180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.3173638804
Short name T279
Test name
Test status
Simulation time 1276907580 ps
CPU time 6.23 seconds
Started Aug 29 10:58:00 AM UTC 24
Finished Aug 29 10:58:08 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173638804 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3173638804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.1435715464
Short name T258
Test name
Test status
Simulation time 301277163 ps
CPU time 1.54 seconds
Started Aug 29 10:58:00 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435715464 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.1435715464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.2504601371
Short name T237
Test name
Test status
Simulation time 153736814 ps
CPU time 0.88 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504601371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.2504601371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.3682383543
Short name T270
Test name
Test status
Simulation time 1641420368 ps
CPU time 6.48 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682383543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.3682383543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.2007147313
Short name T253
Test name
Test status
Simulation time 138073061 ps
CPU time 1.25 seconds
Started Aug 29 10:58:00 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007147313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.2007147313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.2811985653
Short name T250
Test name
Test status
Simulation time 255152176 ps
CPU time 1.59 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811985653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.2811985653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.3684515594
Short name T267
Test name
Test status
Simulation time 1072298285 ps
CPU time 4.76 seconds
Started Aug 29 10:58:00 AM UTC 24
Finished Aug 29 10:58:06 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684515594 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.3684515594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.1967130341
Short name T255
Test name
Test status
Simulation time 380279045 ps
CPU time 2.25 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967130341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1967130341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.2414367868
Short name T246
Test name
Test status
Simulation time 120832933 ps
CPU time 1.12 seconds
Started Aug 29 10:57:59 AM UTC 24
Finished Aug 29 10:58:02 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414367868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.2414367868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.3362119274
Short name T373
Test name
Test status
Simulation time 53581593 ps
CPU time 0.96 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362119274 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.3362119274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.1919829523
Short name T348
Test name
Test status
Simulation time 1275118668 ps
CPU time 5.2 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 241944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919829523 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1919829523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3497050736
Short name T275
Test name
Test status
Simulation time 301574669 ps
CPU time 1.16 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497050736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3497050736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.2298049798
Short name T266
Test name
Test status
Simulation time 163997108 ps
CPU time 0.84 seconds
Started Aug 29 10:58:01 AM UTC 24
Finished Aug 29 10:58:06 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298049798 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2298049798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.1455857502
Short name T285
Test name
Test status
Simulation time 1749628928 ps
CPU time 6.27 seconds
Started Aug 29 10:58:01 AM UTC 24
Finished Aug 29 10:58:11 AM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455857502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.1455857502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.4146372857
Short name T376
Test name
Test status
Simulation time 144694218 ps
CPU time 1.25 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146372857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.4146372857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.3192243785
Short name T257
Test name
Test status
Simulation time 197654262 ps
CPU time 1.38 seconds
Started Aug 29 10:58:01 AM UTC 24
Finished Aug 29 10:58:03 AM UTC 24
Peak memory 208016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192243785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.3192243785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.3952328369
Short name T382
Test name
Test status
Simulation time 6371155187 ps
CPU time 22.21 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:29 AM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952328369 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.3952328369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.1178428467
Short name T325
Test name
Test status
Simulation time 376116019 ps
CPU time 2.07 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178428467 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.1178428467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.365137505
Short name T321
Test name
Test status
Simulation time 112164109 ps
CPU time 1.3 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365137505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.365137505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.2679444972
Short name T395
Test name
Test status
Simulation time 1261956475 ps
CPU time 5.1 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:35 AM UTC 24
Peak memory 241284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679444972 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2679444972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.4100119471
Short name T388
Test name
Test status
Simulation time 303787170 ps
CPU time 1.07 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:31 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100119471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.4100119471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.1623811365
Short name T378
Test name
Test status
Simulation time 190537362 ps
CPU time 1.25 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623811365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1623811365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/24.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3831887771
Short name T269
Test name
Test status
Simulation time 77412372 ps
CPU time 0.84 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831887771 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3831887771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.3724308873
Short name T284
Test name
Test status
Simulation time 1270658427 ps
CPU time 4.9 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:11 AM UTC 24
Peak memory 241576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724308873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3724308873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.650763676
Short name T274
Test name
Test status
Simulation time 301529912 ps
CPU time 1.22 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650763676 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.650763676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2982199647
Short name T286
Test name
Test status
Simulation time 205743733 ps
CPU time 0.89 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:12 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982199647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2982199647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1492773969
Short name T303
Test name
Test status
Simulation time 901250291 ps
CPU time 3.83 seconds
Started Aug 29 10:58:03 AM UTC 24
Finished Aug 29 10:58:15 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492773969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1492773969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.2715418243
Short name T268
Test name
Test status
Simulation time 112773154 ps
CPU time 0.97 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715418243 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.2715418243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.2893753452
Short name T331
Test name
Test status
Simulation time 244617914 ps
CPU time 1.45 seconds
Started Aug 29 10:58:02 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893753452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.2893753452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.2411514048
Short name T384
Test name
Test status
Simulation time 7511165816 ps
CPU time 23.11 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:29 AM UTC 24
Peak memory 209296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411514048 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2411514048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3615091827
Short name T280
Test name
Test status
Simulation time 378781554 ps
CPU time 2.2 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:08 AM UTC 24
Peak memory 217692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615091827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3615091827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.3601387826
Short name T283
Test name
Test status
Simulation time 76457774 ps
CPU time 0.75 seconds
Started Aug 29 10:58:03 AM UTC 24
Finished Aug 29 10:58:11 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601387826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.3601387826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2888536156
Short name T319
Test name
Test status
Simulation time 80361665 ps
CPU time 0.73 seconds
Started Aug 29 10:58:05 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888536156 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2888536156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.3852403346
Short name T294
Test name
Test status
Simulation time 1948422607 ps
CPU time 6.57 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 241724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852403346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.3852403346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.193539291
Short name T277
Test name
Test status
Simulation time 301997112 ps
CPU time 1.19 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193539291 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.193539291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.1645410603
Short name T271
Test name
Test status
Simulation time 143855424 ps
CPU time 0.81 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645410603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.1645410603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.3777661004
Short name T287
Test name
Test status
Simulation time 1490452389 ps
CPU time 5.59 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:12 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777661004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.3777661004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.2390789832
Short name T276
Test name
Test status
Simulation time 161152009 ps
CPU time 1.08 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390789832 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.2390789832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.570056279
Short name T273
Test name
Test status
Simulation time 109527286 ps
CPU time 1.13 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570056279 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.570056279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.1244809506
Short name T345
Test name
Test status
Simulation time 1100078488 ps
CPU time 4.72 seconds
Started Aug 29 10:58:05 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244809506 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1244809506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.578952077
Short name T281
Test name
Test status
Simulation time 300150813 ps
CPU time 1.81 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:08 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578952077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.578952077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3505430989
Short name T272
Test name
Test status
Simulation time 155773234 ps
CPU time 1.02 seconds
Started Aug 29 10:58:04 AM UTC 24
Finished Aug 29 10:58:07 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505430989 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3505430989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.625655207
Short name T295
Test name
Test status
Simulation time 70274379 ps
CPU time 0.7 seconds
Started Aug 29 10:58:07 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625655207 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.625655207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.1413273415
Short name T326
Test name
Test status
Simulation time 1964790996 ps
CPU time 7.17 seconds
Started Aug 29 10:58:07 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413273415 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1413273415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1675212495
Short name T300
Test name
Test status
Simulation time 301582651 ps
CPU time 1.09 seconds
Started Aug 29 10:58:07 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675212495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1675212495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.1353445344
Short name T289
Test name
Test status
Simulation time 128611404 ps
CPU time 0.75 seconds
Started Aug 29 10:58:06 AM UTC 24
Finished Aug 29 10:58:12 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353445344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.1353445344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.1531025973
Short name T305
Test name
Test status
Simulation time 865875657 ps
CPU time 3.83 seconds
Started Aug 29 10:58:06 AM UTC 24
Finished Aug 29 10:58:15 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531025973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.1531025973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.3375830043
Short name T291
Test name
Test status
Simulation time 95814033 ps
CPU time 0.88 seconds
Started Aug 29 10:58:06 AM UTC 24
Finished Aug 29 10:58:12 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375830043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.3375830043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.1304755161
Short name T320
Test name
Test status
Simulation time 128733283 ps
CPU time 1.02 seconds
Started Aug 29 10:58:05 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304755161 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.1304755161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.537907777
Short name T310
Test name
Test status
Simulation time 1032330750 ps
CPU time 5.07 seconds
Started Aug 29 10:58:07 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 218108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537907777 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.537907777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.876624017
Short name T301
Test name
Test status
Simulation time 317118448 ps
CPU time 1.82 seconds
Started Aug 29 10:58:06 AM UTC 24
Finished Aug 29 10:58:14 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876624017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.876624017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.181639955
Short name T288
Test name
Test status
Simulation time 123195097 ps
CPU time 0.88 seconds
Started Aug 29 10:58:06 AM UTC 24
Finished Aug 29 10:58:12 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181639955 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.181639955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.1071950827
Short name T293
Test name
Test status
Simulation time 62407995 ps
CPU time 0.68 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071950827 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.1071950827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.3883765793
Short name T323
Test name
Test status
Simulation time 1974264498 ps
CPU time 6.42 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 241660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883765793 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3883765793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.2881069675
Short name T299
Test name
Test status
Simulation time 303069535 ps
CPU time 1.19 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881069675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.2881069675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.3872349906
Short name T297
Test name
Test status
Simulation time 184444862 ps
CPU time 0.87 seconds
Started Aug 29 10:58:08 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872349906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.3872349906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.2354908129
Short name T307
Test name
Test status
Simulation time 1527175554 ps
CPU time 5.07 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 209136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354908129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.2354908129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.3221090721
Short name T296
Test name
Test status
Simulation time 108363511 ps
CPU time 0.96 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221090721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.3221090721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.3833582268
Short name T230
Test name
Test status
Simulation time 240243714 ps
CPU time 1.3 seconds
Started Aug 29 10:58:08 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833582268 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.3833582268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.3706263037
Short name T391
Test name
Test status
Simulation time 5678243380 ps
CPU time 19.26 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:31 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706263037 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.3706263037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.559075520
Short name T304
Test name
Test status
Simulation time 541794530 ps
CPU time 2.71 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:15 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559075520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.559075520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.1717436459
Short name T298
Test name
Test status
Simulation time 253201857 ps
CPU time 1.22 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717436459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.1717436459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.176829785
Short name T309
Test name
Test status
Simulation time 73450762 ps
CPU time 0.93 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176829785 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.176829785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.2151207647
Short name T328
Test name
Test status
Simulation time 2464018200 ps
CPU time 7.76 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 242448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151207647 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2151207647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3795448457
Short name T336
Test name
Test status
Simulation time 302327679 ps
CPU time 1.07 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795448457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3795448457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.3065260980
Short name T292
Test name
Test status
Simulation time 133875055 ps
CPU time 0.78 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065260980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3065260980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.873414028
Short name T123
Test name
Test status
Simulation time 1722673384 ps
CPU time 6.51 seconds
Started Aug 29 10:58:10 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 209268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873414028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.873414028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.50937495
Short name T337
Test name
Test status
Simulation time 107367473 ps
CPU time 1.12 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50937495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstm
gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.50937495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.616274074
Short name T290
Test name
Test status
Simulation time 120908966 ps
CPU time 1.02 seconds
Started Aug 29 10:58:09 AM UTC 24
Finished Aug 29 10:58:13 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616274074 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.616274074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.403775412
Short name T394
Test name
Test status
Simulation time 4370064139 ps
CPU time 13.95 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:34 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403775412 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.403775412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.1776664403
Short name T347
Test name
Test status
Simulation time 137827722 ps
CPU time 1.59 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776664403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.1776664403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.1147000980
Short name T302
Test name
Test status
Simulation time 192121588 ps
CPU time 1.15 seconds
Started Aug 29 10:58:12 AM UTC 24
Finished Aug 29 10:58:14 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147000980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.1147000980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.3118964732
Short name T66
Test name
Test status
Simulation time 61114262 ps
CPU time 0.62 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118964732 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.3118964732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3036583300
Short name T28
Test name
Test status
Simulation time 2463376143 ps
CPU time 8.57 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:34 AM UTC 24
Peak memory 241780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036583300 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3036583300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2500120608
Short name T59
Test name
Test status
Simulation time 304023720 ps
CPU time 1.12 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500120608 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2500120608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.1208089917
Short name T15
Test name
Test status
Simulation time 82316117 ps
CPU time 0.74 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208089917 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.1208089917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.3669777830
Short name T44
Test name
Test status
Simulation time 860379455 ps
CPU time 3.77 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 209044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669777830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3669777830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.2572763821
Short name T67
Test name
Test status
Simulation time 16542864276 ps
CPU time 24.06 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:49 AM UTC 24
Peak memory 242204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572763821 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.2572763821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3685447493
Short name T136
Test name
Test status
Simulation time 144694223 ps
CPU time 0.98 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685447493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3685447493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2629215579
Short name T13
Test name
Test status
Simulation time 187702272 ps
CPU time 1.21 seconds
Started Aug 29 10:57:19 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629215579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2629215579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2510019726
Short name T105
Test name
Test status
Simulation time 7304966453 ps
CPU time 20.89 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:46 AM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510019726 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.2510019726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.3026867034
Short name T47
Test name
Test status
Simulation time 450485799 ps
CPU time 2.32 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026867034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.3026867034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.450724526
Short name T135
Test name
Test status
Simulation time 65524656 ps
CPU time 0.68 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450724526 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.450724526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.2579324289
Short name T308
Test name
Test status
Simulation time 71331211 ps
CPU time 0.7 seconds
Started Aug 29 10:58:14 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 206392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579324289 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2579324289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.3606623850
Short name T355
Test name
Test status
Simulation time 2262058249 ps
CPU time 7.05 seconds
Started Aug 29 10:58:14 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 242460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606623850 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.3606623850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.3367354504
Short name T315
Test name
Test status
Simulation time 301241436 ps
CPU time 1.2 seconds
Started Aug 29 10:58:14 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367354504 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.3367354504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.2385579233
Short name T312
Test name
Test status
Simulation time 217449458 ps
CPU time 0.92 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385579233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.2385579233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.1055266119
Short name T350
Test name
Test status
Simulation time 1680460095 ps
CPU time 6.3 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055266119 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1055266119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.4027637125
Short name T314
Test name
Test status
Simulation time 104236771 ps
CPU time 1.13 seconds
Started Aug 29 10:58:14 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027637125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.4027637125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.3118742015
Short name T313
Test name
Test status
Simulation time 121106220 ps
CPU time 1.2 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118742015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.3118742015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.2481717779
Short name T125
Test name
Test status
Simulation time 4368889395 ps
CPU time 15.1 seconds
Started Aug 29 10:58:14 AM UTC 24
Finished Aug 29 10:58:32 AM UTC 24
Peak memory 217240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481717779 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.2481717779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.931271714
Short name T324
Test name
Test status
Simulation time 552614938 ps
CPU time 2.52 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931271714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.931271714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3341899926
Short name T316
Test name
Test status
Simulation time 210777378 ps
CPU time 1.24 seconds
Started Aug 29 10:58:13 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341899926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3341899926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.1563397809
Short name T352
Test name
Test status
Simulation time 66481493 ps
CPU time 0.7 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 207540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563397809 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.1563397809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.4199363945
Short name T411
Test name
Test status
Simulation time 1980921843 ps
CPU time 6.3 seconds
Started Aug 29 10:58:16 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 241668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199363945 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.4199363945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1349345177
Short name T402
Test name
Test status
Simulation time 302206785 ps
CPU time 1 seconds
Started Aug 29 10:58:16 AM UTC 24
Finished Aug 29 10:58:51 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349345177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1349345177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.2651059943
Short name T311
Test name
Test status
Simulation time 124900305 ps
CPU time 0.69 seconds
Started Aug 29 10:58:15 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651059943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.2651059943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.801492399
Short name T330
Test name
Test status
Simulation time 838199024 ps
CPU time 4.05 seconds
Started Aug 29 10:58:15 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 209156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801492399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.801492399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.211764567
Short name T401
Test name
Test status
Simulation time 109166185 ps
CPU time 0.85 seconds
Started Aug 29 10:58:16 AM UTC 24
Finished Aug 29 10:58:51 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211764567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.211764567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.2057320398
Short name T322
Test name
Test status
Simulation time 127332879 ps
CPU time 1.34 seconds
Started Aug 29 10:58:15 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057320398 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2057320398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.3864464991
Short name T353
Test name
Test status
Simulation time 365702117 ps
CPU time 1.84 seconds
Started Aug 29 10:58:17 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 208204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864464991 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3864464991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.2360595313
Short name T327
Test name
Test status
Simulation time 380696687 ps
CPU time 2.26 seconds
Started Aug 29 10:58:15 AM UTC 24
Finished Aug 29 10:58:19 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360595313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.2360595313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.2144972672
Short name T317
Test name
Test status
Simulation time 195531431 ps
CPU time 1.26 seconds
Started Aug 29 10:58:15 AM UTC 24
Finished Aug 29 10:58:18 AM UTC 24
Peak memory 208136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144972672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.2144972672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.3307736546
Short name T338
Test name
Test status
Simulation time 64567744 ps
CPU time 0.95 seconds
Started Aug 29 10:58:19 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307736546 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.3307736546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.3128213476
Short name T360
Test name
Test status
Simulation time 1268540931 ps
CPU time 5.73 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:26 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128213476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3128213476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4040599125
Short name T340
Test name
Test status
Simulation time 301951076 ps
CPU time 1.05 seconds
Started Aug 29 10:58:19 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040599125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4040599125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.79156942
Short name T332
Test name
Test status
Simulation time 187901751 ps
CPU time 0.92 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79156942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.79156942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.2299860461
Short name T357
Test name
Test status
Simulation time 1293115465 ps
CPU time 5.24 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:25 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299860461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.2299860461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.1730798648
Short name T333
Test name
Test status
Simulation time 111402268 ps
CPU time 0.92 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730798648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.1730798648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.2633205993
Short name T356
Test name
Test status
Simulation time 189995830 ps
CPU time 1.25 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:24 AM UTC 24
Peak memory 207916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633205993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2633205993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.2442211599
Short name T390
Test name
Test status
Simulation time 3375473930 ps
CPU time 10.85 seconds
Started Aug 29 10:58:19 AM UTC 24
Finished Aug 29 10:58:31 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442211599 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2442211599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.4206097754
Short name T339
Test name
Test status
Simulation time 368450348 ps
CPU time 2.1 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206097754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.4206097754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.4075775151
Short name T335
Test name
Test status
Simulation time 214957178 ps
CPU time 1.27 seconds
Started Aug 29 10:58:18 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075775151 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.4075775151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.2891665322
Short name T349
Test name
Test status
Simulation time 64405338 ps
CPU time 0.7 seconds
Started Aug 29 10:58:21 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891665322 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.2891665322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.3572108230
Short name T359
Test name
Test status
Simulation time 1272508748 ps
CPU time 5.05 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:26 AM UTC 24
Peak memory 242400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572108230 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3572108230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.1905427794
Short name T344
Test name
Test status
Simulation time 301657434 ps
CPU time 1.17 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905427794 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.1905427794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.478967718
Short name T334
Test name
Test status
Simulation time 124189371 ps
CPU time 0.82 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:21 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478967718 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.478967718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.1179067627
Short name T358
Test name
Test status
Simulation time 1678175168 ps
CPU time 6.47 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 209144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179067627 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1179067627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.261626866
Short name T343
Test name
Test status
Simulation time 101496004 ps
CPU time 0.96 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261626866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.261626866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.1540756822
Short name T342
Test name
Test status
Simulation time 126115601 ps
CPU time 1.26 seconds
Started Aug 29 10:58:19 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540756822 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1540756822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.3108246178
Short name T398
Test name
Test status
Simulation time 5506454438 ps
CPU time 17.29 seconds
Started Aug 29 10:58:21 AM UTC 24
Finished Aug 29 10:58:39 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108246178 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.3108246178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.1492273314
Short name T346
Test name
Test status
Simulation time 115779437 ps
CPU time 1.33 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492273314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1492273314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.3225837947
Short name T341
Test name
Test status
Simulation time 66315982 ps
CPU time 1.02 seconds
Started Aug 29 10:58:20 AM UTC 24
Finished Aug 29 10:58:22 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225837947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3225837947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3901150422
Short name T374
Test name
Test status
Simulation time 64984601 ps
CPU time 0.9 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901150422 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3901150422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.777210144
Short name T396
Test name
Test status
Simulation time 2469208976 ps
CPU time 8.41 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:35 AM UTC 24
Peak memory 241796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777210144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.777210144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.4085151775
Short name T379
Test name
Test status
Simulation time 301992247 ps
CPU time 1.44 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 236676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085151775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.4085151775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.1736899260
Short name T329
Test name
Test status
Simulation time 139450591 ps
CPU time 0.93 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736899260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.1736899260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.1183714796
Short name T387
Test name
Test status
Simulation time 820411914 ps
CPU time 4.11 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:30 AM UTC 24
Peak memory 209248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183714796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.1183714796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.2933160309
Short name T375
Test name
Test status
Simulation time 155735812 ps
CPU time 1.12 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933160309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.2933160309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.2452893565
Short name T351
Test name
Test status
Simulation time 123952620 ps
CPU time 1.05 seconds
Started Aug 29 10:58:21 AM UTC 24
Finished Aug 29 10:58:23 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452893565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.2452893565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.801730809
Short name T399
Test name
Test status
Simulation time 5717168692 ps
CPU time 18.56 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:45 AM UTC 24
Peak memory 218112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801730809 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.801730809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.2691203194
Short name T381
Test name
Test status
Simulation time 125230304 ps
CPU time 1.61 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691203194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.2691203194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.2765876997
Short name T368
Test name
Test status
Simulation time 113905871 ps
CPU time 0.82 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765876997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2765876997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.4220024048
Short name T364
Test name
Test status
Simulation time 68570259 ps
CPU time 0.79 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220024048 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.4220024048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.3379638652
Short name T392
Test name
Test status
Simulation time 2256800664 ps
CPU time 7.91 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:34 AM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379638652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.3379638652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1361896187
Short name T365
Test name
Test status
Simulation time 301249011 ps
CPU time 1.1 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 237560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361896187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1361896187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.3051816043
Short name T377
Test name
Test status
Simulation time 190623046 ps
CPU time 1.05 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051816043 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.3051816043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.4092711222
Short name T383
Test name
Test status
Simulation time 776070599 ps
CPU time 3.27 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:29 AM UTC 24
Peak memory 208624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092711222 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.4092711222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2130392259
Short name T362
Test name
Test status
Simulation time 105438595 ps
CPU time 0.95 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130392259 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2130392259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.2750044486
Short name T363
Test name
Test status
Simulation time 111950800 ps
CPU time 1.22 seconds
Started Aug 29 10:58:22 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750044486 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.2750044486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.2158644330
Short name T397
Test name
Test status
Simulation time 2269802509 ps
CPU time 9.88 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:36 AM UTC 24
Peak memory 209316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158644330 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2158644330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.817394764
Short name T371
Test name
Test status
Simulation time 140620735 ps
CPU time 1.71 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817394764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.817394764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.1663601708
Short name T361
Test name
Test status
Simulation time 118323065 ps
CPU time 0.84 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663601708 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.1663601708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.501920274
Short name T400
Test name
Test status
Simulation time 76781264 ps
CPU time 0.71 seconds
Started Aug 29 10:58:26 AM UTC 24
Finished Aug 29 10:58:51 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501920274 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.501920274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.3792193981
Short name T393
Test name
Test status
Simulation time 2434850521 ps
CPU time 7.78 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:58:34 AM UTC 24
Peak memory 242464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792193981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.3792193981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2619099672
Short name T369
Test name
Test status
Simulation time 302288066 ps
CPU time 1.25 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619099672 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2619099672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.1970173501
Short name T366
Test name
Test status
Simulation time 161413220 ps
CPU time 0.87 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970173501 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.1970173501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.3088232394
Short name T385
Test name
Test status
Simulation time 974162711 ps
CPU time 4.34 seconds
Started Aug 29 10:58:24 AM UTC 24
Finished Aug 29 10:58:30 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088232394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.3088232394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.3577532296
Short name T367
Test name
Test status
Simulation time 117243994 ps
CPU time 1.06 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577532296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.3577532296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.3458119815
Short name T370
Test name
Test status
Simulation time 192607186 ps
CPU time 1.4 seconds
Started Aug 29 10:58:23 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458119815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3458119815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.3206288407
Short name T430
Test name
Test status
Simulation time 10933413134 ps
CPU time 33.44 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 218232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206288407 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3206288407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.396594296
Short name T380
Test name
Test status
Simulation time 280114046 ps
CPU time 1.97 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:58:28 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396594296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.396594296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.2497461991
Short name T372
Test name
Test status
Simulation time 275484017 ps
CPU time 1.43 seconds
Started Aug 29 10:58:25 AM UTC 24
Finished Aug 29 10:58:27 AM UTC 24
Peak memory 208324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497461991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.2497461991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.2475414059
Short name T427
Test name
Test status
Simulation time 83364217 ps
CPU time 0.84 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475414059 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2475414059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.3588716874
Short name T464
Test name
Test status
Simulation time 1269665263 ps
CPU time 4.78 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 241412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588716874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.3588716874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3425173748
Short name T431
Test name
Test status
Simulation time 302148488 ps
CPU time 1.16 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425173748 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3425173748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.186383580
Short name T404
Test name
Test status
Simulation time 73871850 ps
CPU time 0.8 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186383580 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.186383580
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.287658574
Short name T438
Test name
Test status
Simulation time 742993390 ps
CPU time 3.95 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287658574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.287658574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.3723963824
Short name T405
Test name
Test status
Simulation time 146164294 ps
CPU time 1.11 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723963824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.3723963824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.1195961054
Short name T412
Test name
Test status
Simulation time 209956548 ps
CPU time 1.42 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195961054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.1195961054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.1263885210
Short name T483
Test name
Test status
Simulation time 4921858493 ps
CPU time 18.01 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:16 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263885210 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.1263885210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.1003579080
Short name T414
Test name
Test status
Simulation time 326584801 ps
CPU time 1.98 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:57 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003579080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.1003579080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.1601808129
Short name T406
Test name
Test status
Simulation time 101483189 ps
CPU time 1.01 seconds
Started Aug 29 10:58:27 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601808129 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1601808129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.969393650
Short name T429
Test name
Test status
Simulation time 67700899 ps
CPU time 0.75 seconds
Started Aug 29 10:58:29 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969393650 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.969393650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.2963152998
Short name T459
Test name
Test status
Simulation time 1258539697 ps
CPU time 5.09 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 241356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963152998 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2963152998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.1986346068
Short name T445
Test name
Test status
Simulation time 301869294 ps
CPU time 1.3 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986346068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.1986346068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.1175670671
Short name T433
Test name
Test status
Simulation time 118246989 ps
CPU time 1 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175670671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1175670671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.746378619
Short name T468
Test name
Test status
Simulation time 1807120697 ps
CPU time 6.11 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:04 AM UTC 24
Peak memory 209188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746378619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.746378619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.2576777540
Short name T436
Test name
Test status
Simulation time 183653565 ps
CPU time 1.26 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576777540 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.2576777540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.1265099359
Short name T440
Test name
Test status
Simulation time 127777726 ps
CPU time 1.27 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265099359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.1265099359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.1689866065
Short name T525
Test name
Test status
Simulation time 10439105102 ps
CPU time 32.79 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689866065 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.1689866065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.2871661674
Short name T439
Test name
Test status
Simulation time 284791044 ps
CPU time 1.9 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871661674 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.2871661674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.534871386
Short name T434
Test name
Test status
Simulation time 112579889 ps
CPU time 1.02 seconds
Started Aug 29 10:58:28 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534871386 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.534871386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.3802022466
Short name T453
Test name
Test status
Simulation time 60614977 ps
CPU time 0.79 seconds
Started Aug 29 10:58:31 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802022466 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3802022466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.62674823
Short name T466
Test name
Test status
Simulation time 1275706815 ps
CPU time 5.29 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:59:04 AM UTC 24
Peak memory 241720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62674823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.62674823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.2257496173
Short name T451
Test name
Test status
Simulation time 304116331 ps
CPU time 1.53 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 237452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257496173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.2257496173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.244030570
Short name T417
Test name
Test status
Simulation time 206316754 ps
CPU time 0.81 seconds
Started Aug 29 10:58:29 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244030570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.244030570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.1568650051
Short name T450
Test name
Test status
Simulation time 1083167595 ps
CPU time 4.66 seconds
Started Aug 29 10:58:29 AM UTC 24
Finished Aug 29 10:59:01 AM UTC 24
Peak memory 209164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568650051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.1568650051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3895340902
Short name T442
Test name
Test status
Simulation time 169536397 ps
CPU time 1.28 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895340902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3895340902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.719610286
Short name T420
Test name
Test status
Simulation time 185320218 ps
CPU time 1.19 seconds
Started Aug 29 10:58:29 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719610286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.719610286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.1751803228
Short name T449
Test name
Test status
Simulation time 233658903 ps
CPU time 1.34 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751803228 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.1751803228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.245690570
Short name T386
Test name
Test status
Simulation time 132329413 ps
CPU time 1.48 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245690570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.245690570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.162182369
Short name T409
Test name
Test status
Simulation time 149199914 ps
CPU time 1.34 seconds
Started Aug 29 10:58:30 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162182369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.162182369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.4275942858
Short name T103
Test name
Test status
Simulation time 84658335 ps
CPU time 0.72 seconds
Started Aug 29 10:57:25 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275942858 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.4275942858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.449832283
Short name T26
Test name
Test status
Simulation time 1266787552 ps
CPU time 5.24 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 241560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449832283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.449832283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1878632950
Short name T51
Test name
Test status
Simulation time 302697523 ps
CPU time 0.98 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878632950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1878632950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.731903719
Short name T16
Test name
Test status
Simulation time 162153025 ps
CPU time 0.9 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:26 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731903719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.731903719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.2191252135
Short name T95
Test name
Test status
Simulation time 1776619236 ps
CPU time 5.94 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191252135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.2191252135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.161815112
Short name T68
Test name
Test status
Simulation time 16520910954 ps
CPU time 25.73 seconds
Started Aug 29 10:57:24 AM UTC 24
Finished Aug 29 10:57:52 AM UTC 24
Peak memory 241876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161815112 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.161815112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.763246177
Short name T83
Test name
Test status
Simulation time 187040462 ps
CPU time 1.2 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763246177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.763246177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2772017941
Short name T52
Test name
Test status
Simulation time 251826537 ps
CPU time 1.51 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772017941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2772017941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.2647405
Short name T108
Test name
Test status
Simulation time 9484350485 ps
CPU time 33.5 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:59 AM UTC 24
Peak memory 218168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647405 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.2647405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.1349199973
Short name T53
Test name
Test status
Simulation time 136455796 ps
CPU time 1.73 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349199973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.1349199973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.2693371895
Short name T85
Test name
Test status
Simulation time 102077049 ps
CPU time 1.3 seconds
Started Aug 29 10:57:23 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693371895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.2693371895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.78720182
Short name T415
Test name
Test status
Simulation time 87525713 ps
CPU time 0.77 seconds
Started Aug 29 10:58:35 AM UTC 24
Finished Aug 29 10:58:57 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78720182 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.78720182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.252241196
Short name T455
Test name
Test status
Simulation time 1276707386 ps
CPU time 4.84 seconds
Started Aug 29 10:58:34 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 242372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252241196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.252241196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.2872643435
Short name T408
Test name
Test status
Simulation time 302565928 ps
CPU time 0.99 seconds
Started Aug 29 10:58:34 AM UTC 24
Finished Aug 29 10:58:56 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872643435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.2872643435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.2206507576
Short name T423
Test name
Test status
Simulation time 158815369 ps
CPU time 0.81 seconds
Started Aug 29 10:58:32 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206507576 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.2206507576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.2620866760
Short name T463
Test name
Test status
Simulation time 1027999728 ps
CPU time 4.83 seconds
Started Aug 29 10:58:32 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620866760 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.2620866760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.3208010093
Short name T426
Test name
Test status
Simulation time 111996721 ps
CPU time 0.87 seconds
Started Aug 29 10:58:32 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208010093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.3208010093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.318986354
Short name T424
Test name
Test status
Simulation time 123533638 ps
CPU time 1.11 seconds
Started Aug 29 10:58:31 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318986354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.318986354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.3087068519
Short name T465
Test name
Test status
Simulation time 1816713326 ps
CPU time 6.19 seconds
Started Aug 29 10:58:35 AM UTC 24
Finished Aug 29 10:59:03 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087068519 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.3087068519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.4137673174
Short name T410
Test name
Test status
Simulation time 479000910 ps
CPU time 2.55 seconds
Started Aug 29 10:58:32 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 217852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137673174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.4137673174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.2771693705
Short name T425
Test name
Test status
Simulation time 146986737 ps
CPU time 0.93 seconds
Started Aug 29 10:58:32 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771693705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.2771693705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.3800191723
Short name T435
Test name
Test status
Simulation time 58789347 ps
CPU time 0.81 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800191723 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.3800191723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.4286598754
Short name T470
Test name
Test status
Simulation time 2447434683 ps
CPU time 7.43 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:59:05 AM UTC 24
Peak memory 242108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286598754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.4286598754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4272161898
Short name T443
Test name
Test status
Simulation time 302113125 ps
CPU time 1.1 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 237564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272161898 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4272161898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.2772587347
Short name T432
Test name
Test status
Simulation time 189201515 ps
CPU time 0.81 seconds
Started Aug 29 10:58:36 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772587347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2772587347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.2078424500
Short name T469
Test name
Test status
Simulation time 1777294485 ps
CPU time 6.05 seconds
Started Aug 29 10:58:40 AM UTC 24
Finished Aug 29 10:59:05 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078424500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.2078424500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.1471243326
Short name T437
Test name
Test status
Simulation time 94034882 ps
CPU time 1.05 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471243326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.1471243326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.2813133333
Short name T418
Test name
Test status
Simulation time 203704697 ps
CPU time 1.3 seconds
Started Aug 29 10:58:35 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813133333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2813133333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.466532597
Short name T447
Test name
Test status
Simulation time 222647828 ps
CPU time 1.46 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466532597 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.466532597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.804137130
Short name T422
Test name
Test status
Simulation time 149951662 ps
CPU time 1.55 seconds
Started Aug 29 10:58:46 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804137130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.804137130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.1584858412
Short name T416
Test name
Test status
Simulation time 80777296 ps
CPU time 0.78 seconds
Started Aug 29 10:58:43 AM UTC 24
Finished Aug 29 10:58:57 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584858412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.1584858412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.2288390881
Short name T446
Test name
Test status
Simulation time 72273954 ps
CPU time 0.76 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288390881 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.2288390881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.1040833975
Short name T473
Test name
Test status
Simulation time 2454582380 ps
CPU time 8.54 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:07 AM UTC 24
Peak memory 241736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040833975 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1040833975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.2645970807
Short name T452
Test name
Test status
Simulation time 303078210 ps
CPU time 1.24 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645970807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.2645970807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.4073656968
Short name T441
Test name
Test status
Simulation time 129117059 ps
CPU time 0.94 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073656968 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.4073656968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.2849174355
Short name T458
Test name
Test status
Simulation time 1705579122 ps
CPU time 5.56 seconds
Started Aug 29 10:58:52 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849174355 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2849174355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.2510308872
Short name T421
Test name
Test status
Simulation time 110698641 ps
CPU time 0.87 seconds
Started Aug 29 10:58:56 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510308872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.2510308872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.3184191136
Short name T448
Test name
Test status
Simulation time 186286965 ps
CPU time 1.36 seconds
Started Aug 29 10:58:47 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184191136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3184191136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2087062946
Short name T530
Test name
Test status
Simulation time 8397347678 ps
CPU time 35.17 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087062946 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2087062946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.81459775
Short name T428
Test name
Test status
Simulation time 372741773 ps
CPU time 2.25 seconds
Started Aug 29 10:58:52 AM UTC 24
Finished Aug 29 10:58:58 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81459775 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.81459775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.1353494085
Short name T413
Test name
Test status
Simulation time 91123298 ps
CPU time 0.75 seconds
Started Aug 29 10:58:52 AM UTC 24
Finished Aug 29 10:58:57 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353494085 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.1353494085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.2409025198
Short name T456
Test name
Test status
Simulation time 68402911 ps
CPU time 0.69 seconds
Started Aug 29 10:58:59 AM UTC 24
Finished Aug 29 10:59:01 AM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409025198 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.2409025198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2829731021
Short name T474
Test name
Test status
Simulation time 2462708543 ps
CPU time 7.75 seconds
Started Aug 29 10:58:58 AM UTC 24
Finished Aug 29 10:59:08 AM UTC 24
Peak memory 241792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829731021 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2829731021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.1327487905
Short name T460
Test name
Test status
Simulation time 302115706 ps
CPU time 1.1 seconds
Started Aug 29 10:58:59 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 237620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327487905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.1327487905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.52913780
Short name T444
Test name
Test status
Simulation time 181035547 ps
CPU time 0.85 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:58:59 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52913780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.52913780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.2297366754
Short name T467
Test name
Test status
Simulation time 1619913330 ps
CPU time 5.12 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:04 AM UTC 24
Peak memory 209152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297366754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.2297366754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.1147256528
Short name T457
Test name
Test status
Simulation time 182779022 ps
CPU time 1.1 seconds
Started Aug 29 10:58:58 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147256528 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.1147256528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.688105477
Short name T419
Test name
Test status
Simulation time 115692250 ps
CPU time 1.12 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688105477 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.688105477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.2175688151
Short name T496
Test name
Test status
Simulation time 904446876 ps
CPU time 3.86 seconds
Started Aug 29 10:58:59 AM UTC 24
Finished Aug 29 10:59:24 AM UTC 24
Peak memory 208540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175688151 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.2175688151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.529587199
Short name T462
Test name
Test status
Simulation time 142690501 ps
CPU time 1.55 seconds
Started Aug 29 10:58:58 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529587199 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.529587199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.2702541507
Short name T454
Test name
Test status
Simulation time 269782535 ps
CPU time 1.51 seconds
Started Aug 29 10:58:57 AM UTC 24
Finished Aug 29 10:59:00 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702541507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.2702541507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.972861433
Short name T461
Test name
Test status
Simulation time 69938302 ps
CPU time 0.74 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:02 AM UTC 24
Peak memory 207664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972861433 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.972861433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.2232875754
Short name T514
Test name
Test status
Simulation time 1974964024 ps
CPU time 6.63 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 241732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232875754 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.2232875754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.199073904
Short name T491
Test name
Test status
Simulation time 301783065 ps
CPU time 1.03 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199073904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.199073904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.4150790357
Short name T486
Test name
Test status
Simulation time 146939538 ps
CPU time 0.8 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150790357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.4150790357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.4176764946
Short name T509
Test name
Test status
Simulation time 1678294789 ps
CPU time 6.07 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176764946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.4176764946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1314052478
Short name T490
Test name
Test status
Simulation time 150452734 ps
CPU time 1.02 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314052478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1314052478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.3950352002
Short name T485
Test name
Test status
Simulation time 258318946 ps
CPU time 1.38 seconds
Started Aug 29 10:58:59 AM UTC 24
Finished Aug 29 10:59:21 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950352002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.3950352002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.294595323
Short name T516
Test name
Test status
Simulation time 2198260270 ps
CPU time 7.82 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 218116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294595323 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.294595323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.1760589195
Short name T494
Test name
Test status
Simulation time 351117289 ps
CPU time 1.87 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:23 AM UTC 24
Peak memory 208332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760589195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1760589195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.2083381784
Short name T492
Test name
Test status
Simulation time 288900430 ps
CPU time 1.42 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083381784 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2083381784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1732880045
Short name T521
Test name
Test status
Simulation time 64075510 ps
CPU time 0.73 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732880045 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1732880045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.2140457579
Short name T534
Test name
Test status
Simulation time 2277707384 ps
CPU time 7.99 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:37 AM UTC 24
Peak memory 242160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140457579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.2140457579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.1081387762
Short name T520
Test name
Test status
Simulation time 301909396 ps
CPU time 1.02 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081387762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.1081387762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.2029552903
Short name T488
Test name
Test status
Simulation time 90024236 ps
CPU time 0.69 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029552903 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2029552903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3872426941
Short name T531
Test name
Test status
Simulation time 1769289462 ps
CPU time 5.77 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872426941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3872426941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.678844087
Short name T519
Test name
Test status
Simulation time 106943266 ps
CPU time 0.97 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 208372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678844087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rst
mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.678844087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.43562413
Short name T493
Test name
Test status
Simulation time 205235635 ps
CPU time 1.18 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43562413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.43562413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.302322152
Short name T522
Test name
Test status
Simulation time 229579955 ps
CPU time 1.33 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302322152 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.302322152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.2275699399
Short name T524
Test name
Test status
Simulation time 377745888 ps
CPU time 2.17 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275699399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.2275699399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.2546224392
Short name T489
Test name
Test status
Simulation time 65414057 ps
CPU time 0.68 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546224392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2546224392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.469542335
Short name T508
Test name
Test status
Simulation time 67830978 ps
CPU time 0.82 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469542335 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.469542335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.1008696537
Short name T527
Test name
Test status
Simulation time 1968043161 ps
CPU time 6.46 seconds
Started Aug 29 10:59:01 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 242368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008696537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1008696537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.669175221
Short name T477
Test name
Test status
Simulation time 302274239 ps
CPU time 1.04 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 237244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669175221 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.669175221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.2451176969
Short name T518
Test name
Test status
Simulation time 88980237 ps
CPU time 0.71 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:29 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451176969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.2451176969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.894800567
Short name T533
Test name
Test status
Simulation time 1860870547 ps
CPU time 7.47 seconds
Started Aug 29 10:59:01 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894800567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.894800567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.3484268931
Short name T497
Test name
Test status
Simulation time 156945443 ps
CPU time 1.01 seconds
Started Aug 29 10:59:01 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484268931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.3484268931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.2714537194
Short name T523
Test name
Test status
Simulation time 119458274 ps
CPU time 1.24 seconds
Started Aug 29 10:59:00 AM UTC 24
Finished Aug 29 10:59:30 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714537194 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2714537194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.3781078217
Short name T517
Test name
Test status
Simulation time 2167706433 ps
CPU time 9.84 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 217136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781078217 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.3781078217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.2255548274
Short name T471
Test name
Test status
Simulation time 141995462 ps
CPU time 1.59 seconds
Started Aug 29 10:59:01 AM UTC 24
Finished Aug 29 10:59:06 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255548274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2255548274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.2687194068
Short name T498
Test name
Test status
Simulation time 270827472 ps
CPU time 1.29 seconds
Started Aug 29 10:59:01 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687194068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.2687194068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.27718092
Short name T478
Test name
Test status
Simulation time 74067767 ps
CPU time 0.7 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27718092 -assert nopostproc +UVM_TESTNAME=rstmg
r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.27718092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.2782982799
Short name T482
Test name
Test status
Simulation time 1272449146 ps
CPU time 4.92 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:15 AM UTC 24
Peak memory 242064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782982799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.2782982799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.143057976
Short name T480
Test name
Test status
Simulation time 301818348 ps
CPU time 1.05 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143057976 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.143057976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.3899703761
Short name T476
Test name
Test status
Simulation time 98372229 ps
CPU time 0.74 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 207832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899703761 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.3899703761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.873012913
Short name T529
Test name
Test status
Simulation time 1655553303 ps
CPU time 6.52 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:33 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873012913 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.873012913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.2966638824
Short name T479
Test name
Test status
Simulation time 145747074 ps
CPU time 1.02 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966638824 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.2966638824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.1058879108
Short name T512
Test name
Test status
Simulation time 122533338 ps
CPU time 1.19 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058879108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.1058879108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.2301519304
Short name T535
Test name
Test status
Simulation time 7247336394 ps
CPU time 31.06 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:42 AM UTC 24
Peak memory 218236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301519304 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.2301519304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.4058508438
Short name T481
Test name
Test status
Simulation time 118498335 ps
CPU time 1.3 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:11 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058508438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.4058508438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.1661498191
Short name T511
Test name
Test status
Simulation time 161610453 ps
CPU time 1.13 seconds
Started Aug 29 10:59:02 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661498191 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.1661498191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.274121704
Short name T502
Test name
Test status
Simulation time 81117527 ps
CPU time 0.76 seconds
Started Aug 29 10:59:05 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274121704 -assert nopostproc +UVM_TESTNAME=rstm
gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.274121704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.1330345204
Short name T500
Test name
Test status
Simulation time 2444059168 ps
CPU time 8.3 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:34 AM UTC 24
Peak memory 242416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330345204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.1330345204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1706076363
Short name T507
Test name
Test status
Simulation time 302440584 ps
CPU time 1.33 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 237628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706076363 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1706076363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.725210742
Short name T499
Test name
Test status
Simulation time 132703279 ps
CPU time 0.71 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725210742 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.725210742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.3598321231
Short name T475
Test name
Test status
Simulation time 964420552 ps
CPU time 3.99 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:09 AM UTC 24
Peak memory 208716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598321231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.3598321231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.3812991819
Short name T504
Test name
Test status
Simulation time 152617404 ps
CPU time 1.06 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812991819 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.3812991819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2681544207
Short name T472
Test name
Test status
Simulation time 243035145 ps
CPU time 1.27 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:07 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681544207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2681544207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.2804325371
Short name T528
Test name
Test status
Simulation time 1889880537 ps
CPU time 6.6 seconds
Started Aug 29 10:59:04 AM UTC 24
Finished Aug 29 10:59:32 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804325371 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.2804325371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.2867373280
Short name T513
Test name
Test status
Simulation time 329610407 ps
CPU time 2.13 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867373280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.2867373280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.3703370978
Short name T505
Test name
Test status
Simulation time 171115188 ps
CPU time 1.09 seconds
Started Aug 29 10:59:03 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703370978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.3703370978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.3592689438
Short name T506
Test name
Test status
Simulation time 69828523 ps
CPU time 0.67 seconds
Started Aug 29 10:59:12 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592689438 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3592689438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.1009511755
Short name T532
Test name
Test status
Simulation time 2449795281 ps
CPU time 8.81 seconds
Started Aug 29 10:59:08 AM UTC 24
Finished Aug 29 10:59:35 AM UTC 24
Peak memory 242528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009511755 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.1009511755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.1075437212
Short name T487
Test name
Test status
Simulation time 302122653 ps
CPU time 0.93 seconds
Started Aug 29 10:59:09 AM UTC 24
Finished Aug 29 10:59:22 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075437212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.1075437212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.4009696611
Short name T503
Test name
Test status
Simulation time 126731743 ps
CPU time 0.7 seconds
Started Aug 29 10:59:05 AM UTC 24
Finished Aug 29 10:59:26 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009696611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.4009696611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.892947902
Short name T526
Test name
Test status
Simulation time 848622687 ps
CPU time 4.26 seconds
Started Aug 29 10:59:06 AM UTC 24
Finished Aug 29 10:59:31 AM UTC 24
Peak memory 209192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892947902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.892947902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3309938219
Short name T510
Test name
Test status
Simulation time 172329696 ps
CPU time 1.11 seconds
Started Aug 29 10:59:08 AM UTC 24
Finished Aug 29 10:59:27 AM UTC 24
Peak memory 206776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309938219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3309938219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.2714359393
Short name T484
Test name
Test status
Simulation time 124408295 ps
CPU time 1.01 seconds
Started Aug 29 10:59:05 AM UTC 24
Finished Aug 29 10:59:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714359393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.2714359393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.1616714561
Short name T501
Test name
Test status
Simulation time 4744739491 ps
CPU time 14.52 seconds
Started Aug 29 10:59:10 AM UTC 24
Finished Aug 29 10:59:36 AM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616714561 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.1616714561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.2006766944
Short name T495
Test name
Test status
Simulation time 511487702 ps
CPU time 2.33 seconds
Started Aug 29 10:59:07 AM UTC 24
Finished Aug 29 10:59:23 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006766944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.2006766944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.3109054686
Short name T515
Test name
Test status
Simulation time 151997764 ps
CPU time 1.11 seconds
Started Aug 29 10:59:06 AM UTC 24
Finished Aug 29 10:59:28 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109054686 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.3109054686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.4283295133
Short name T42
Test name
Test status
Simulation time 64369141 ps
CPU time 0.67 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283295133 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4283295133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4282179978
Short name T27
Test name
Test status
Simulation time 1270458868 ps
CPU time 5.63 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:34 AM UTC 24
Peak memory 240828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282179978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.4282179978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.3595851357
Short name T46
Test name
Test status
Simulation time 302246978 ps
CPU time 1.25 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595851357 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.3595851357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.2444623619
Short name T18
Test name
Test status
Simulation time 152151929 ps
CPU time 1.01 seconds
Started Aug 29 10:57:25 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444623619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.2444623619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2575120705
Short name T43
Test name
Test status
Simulation time 100988104 ps
CPU time 0.84 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575120705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2575120705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.4280263241
Short name T92
Test name
Test status
Simulation time 247914136 ps
CPU time 1.51 seconds
Started Aug 29 10:57:25 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280263241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.4280263241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3463857130
Short name T107
Test name
Test status
Simulation time 9355155745 ps
CPU time 28.68 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463857130 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3463857130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3866112411
Short name T88
Test name
Test status
Simulation time 301249611 ps
CPU time 2.06 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 217916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866112411 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3866112411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.4254454255
Short name T45
Test name
Test status
Simulation time 187162267 ps
CPU time 1.28 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254454255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4254454255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.2460025812
Short name T141
Test name
Test status
Simulation time 73951271 ps
CPU time 0.8 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460025812 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.2460025812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2637140860
Short name T38
Test name
Test status
Simulation time 1267787871 ps
CPU time 5.33 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 241352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637140860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2637140860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.4000513364
Short name T145
Test name
Test status
Simulation time 300832230 ps
CPU time 1.24 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000513364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.4000513364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.2657460198
Short name T19
Test name
Test status
Simulation time 132814125 ps
CPU time 0.72 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657460198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.2657460198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2769343338
Short name T102
Test name
Test status
Simulation time 1544830934 ps
CPU time 5.51 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769343338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.2769343338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.3105986153
Short name T143
Test name
Test status
Simulation time 143614783 ps
CPU time 1.17 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105986153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.3105986153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.847867284
Short name T91
Test name
Test status
Simulation time 249573556 ps
CPU time 1.42 seconds
Started Aug 29 10:57:27 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847867284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.847867284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.3545564628
Short name T111
Test name
Test status
Simulation time 3113395499 ps
CPU time 11.87 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:42 AM UTC 24
Peak memory 209376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545564628 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.3545564628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3139517071
Short name T89
Test name
Test status
Simulation time 111397815 ps
CPU time 1.33 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139517071 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3139517071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2590818252
Short name T142
Test name
Test status
Simulation time 101942582 ps
CPU time 0.95 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590818252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2590818252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.3623782650
Short name T144
Test name
Test status
Simulation time 68818892 ps
CPU time 0.69 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623782650 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.3623782650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.205426860
Short name T29
Test name
Test status
Simulation time 1261083969 ps
CPU time 5.65 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:36 AM UTC 24
Peak memory 241728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205426860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.205426860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1820795780
Short name T146
Test name
Test status
Simulation time 302659042 ps
CPU time 1.22 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 237624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820795780 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.1820795780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.18362677
Short name T20
Test name
Test status
Simulation time 108578253 ps
CPU time 0.7 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18362677 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=
rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.18362677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.351019099
Short name T100
Test name
Test status
Simulation time 1126279962 ps
CPU time 4.93 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 209112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351019099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.351019099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.1871272923
Short name T148
Test name
Test status
Simulation time 159696849 ps
CPU time 1.3 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:32 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871272923 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.1871272923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.3632980454
Short name T147
Test name
Test status
Simulation time 117865776 ps
CPU time 1.31 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632980454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3632980454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.844151555
Short name T121
Test name
Test status
Simulation time 12861708903 ps
CPU time 37.62 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:58:08 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844151555 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.844151555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.3554959440
Short name T93
Test name
Test status
Simulation time 347199592 ps
CPU time 2.03 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:32 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554959440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.3554959440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.782296323
Short name T138
Test name
Test status
Simulation time 133946307 ps
CPU time 1.21 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782296323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.782296323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.4167682102
Short name T150
Test name
Test status
Simulation time 71581688 ps
CPU time 0.72 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:36 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167682102 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.4167682102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1192725932
Short name T151
Test name
Test status
Simulation time 301904763 ps
CPU time 1.1 seconds
Started Aug 29 10:57:34 AM UTC 24
Finished Aug 29 10:57:37 AM UTC 24
Peak memory 237448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192725932 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1192725932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.1242072872
Short name T21
Test name
Test status
Simulation time 94284524 ps
CPU time 0.74 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:31 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242072872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1242072872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2719500340
Short name T99
Test name
Test status
Simulation time 1138249524 ps
CPU time 4.46 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 209252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719500340 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.2719500340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2162994375
Short name T127
Test name
Test status
Simulation time 102287804 ps
CPU time 0.9 seconds
Started Aug 29 10:57:33 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 208368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162994375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2162994375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2365820378
Short name T90
Test name
Test status
Simulation time 199908577 ps
CPU time 1.36 seconds
Started Aug 29 10:57:29 AM UTC 24
Finished Aug 29 10:57:32 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365820378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2365820378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.4045016898
Short name T153
Test name
Test status
Simulation time 781754239 ps
CPU time 3.08 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:39 AM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045016898 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.4045016898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.1094361875
Short name T149
Test name
Test status
Simulation time 299943770 ps
CPU time 1.83 seconds
Started Aug 29 10:57:33 AM UTC 24
Finished Aug 29 10:57:36 AM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094361875 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1094361875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.527953060
Short name T128
Test name
Test status
Simulation time 157027206 ps
CPU time 1.05 seconds
Started Aug 29 10:57:33 AM UTC 24
Finished Aug 29 10:57:35 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527953060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.527953060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3901459273
Short name T197
Test name
Test status
Simulation time 66197372 ps
CPU time 0.76 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901459273 -assert nopostproc +UVM_TESTNAME=rst
mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3901459273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.4087911869
Short name T259
Test name
Test status
Simulation time 2238551704 ps
CPU time 7.48 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:04 AM UTC 24
Peak memory 242456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087911869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.4087911869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1080428862
Short name T217
Test name
Test status
Simulation time 301947535 ps
CPU time 1.66 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:58 AM UTC 24
Peak memory 237444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080428862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmg
r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.1080428862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.2574684634
Short name T22
Test name
Test status
Simulation time 84708101 ps
CPU time 0.67 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:36 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574684634 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2574684634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.313859721
Short name T109
Test name
Test status
Simulation time 891619332 ps
CPU time 4.87 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:01 AM UTC 24
Peak memory 209152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313859721 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ
=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.313859721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2680034551
Short name T208
Test name
Test status
Simulation time 149116688 ps
CPU time 1.23 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:57 AM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680034551 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rs
tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2680034551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1545128768
Short name T306
Test name
Test status
Simulation time 5336065470 ps
CPU time 20.43 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:58:17 AM UTC 24
Peak memory 220176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545128768 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1545128768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2562525931
Short name T129
Test name
Test status
Simulation time 424608901 ps
CPU time 2.15 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:38 AM UTC 24
Peak memory 217788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562525931 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2562525931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.1346820904
Short name T152
Test name
Test status
Simulation time 153078195 ps
CPU time 1.01 seconds
Started Aug 29 10:57:35 AM UTC 24
Finished Aug 29 10:57:37 AM UTC 24
Peak memory 208300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346820904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE
Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.1346820904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest
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