Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	596230	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

357447

1

T1

116

T3

51

T4

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	507039	1			T1	186		T2	1		T3	72
values[0x0]	222541	1			T1	91		T3	36		T4	57
values[0x1]	224097	1			T1	102		T3	38		T4	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	500200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

453477

1

T1

163

T3

63

T4

100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3421	1			T4	1		T9	9		T12	1
valid_sources[0x01]	3532	1			T1	19		T4	2		T5	6
valid_sources[0x02]	3527	1			T5	3		T8	3		T9	12
valid_sources[0x03]	3108	1			T1	5		T5	1		T8	4
valid_sources[0x04]	3500	1			T4	1		T5	4		T8	1
valid_sources[0x05]	3526	1			T4	1		T5	2		T8	3
valid_sources[0x06]	4675	1			T4	2		T5	6		T9	8
valid_sources[0x07]	4069	1			T1	2		T4	1		T5	5
valid_sources[0x08]	4401	1			T4	1		T5	4		T9	13
valid_sources[0x09]	3244	1			T3	1		T5	3		T9	8
valid_sources[0x0a]	3030	1			T4	1		T8	1		T9	10
valid_sources[0x0b]	3360	1			T1	1		T5	5		T9	5
valid_sources[0x0c]	4823	1			T1	7		T4	2		T9	10
valid_sources[0x0d]	6132	1			T3	5		T5	5		T8	1
valid_sources[0x0e]	6156	1			T4	1		T5	7		T9	11
valid_sources[0x0f]	3466	1			T1	31		T5	4		T9	12
valid_sources[0x10]	3174	1			T1	4		T8	2		T9	12
valid_sources[0x11]	3098	1			T4	1		T5	12		T9	10
valid_sources[0x12]	3591	1			T4	2		T5	2		T8	1
valid_sources[0x13]	3309	1			T5	3		T8	1		T9	9
valid_sources[0x14]	3555	1			T4	1		T5	6		T8	1
valid_sources[0x15]	3160	1			T3	1		T4	1		T5	2
valid_sources[0x16]	4833	1			T5	3		T9	16		T12	1
valid_sources[0x17]	3191	1			T5	8		T8	1		T9	11
valid_sources[0x18]	4864	1			T4	1		T8	1		T9	12
valid_sources[0x19]	5585	1			T5	5		T9	5		T12	1
valid_sources[0x1a]	3212	1			T4	2		T5	3		T8	7
valid_sources[0x1b]	3360	1			T1	9		T5	4		T9	12
valid_sources[0x1c]	3827	1			T4	2		T5	8		T8	2
valid_sources[0x1d]	3734	1			T5	3		T9	11		T12	1
valid_sources[0x1e]	4237	1			T4	1		T5	5		T9	18
valid_sources[0x1f]	6324	1			T4	2		T5	6		T8	2
valid_sources[0x20]	4377	1			T5	4		T8	5		T9	15
valid_sources[0x21]	3872	1			T1	3		T5	8		T7	1
valid_sources[0x22]	3406	1			T4	1		T5	1		T9	11
valid_sources[0x23]	2729	1			T5	4		T9	11		T12	2
valid_sources[0x24]	4175	1			T4	1		T5	4		T8	1
valid_sources[0x25]	4059	1			T4	3		T9	16		T23	8
valid_sources[0x26]	3319	1			T1	6		T4	2		T5	1
valid_sources[0x27]	3885	1			T5	7		T9	11		T22	3
valid_sources[0x28]	3322	1			T4	2		T5	3		T9	9
valid_sources[0x29]	2702	1			T5	5		T8	2		T9	16
valid_sources[0x2a]	3337	1			T4	1		T5	3		T9	20
valid_sources[0x2b]	4350	1			T3	7		T4	2		T5	3
valid_sources[0x2c]	3479	1			T4	1		T5	5		T8	4
valid_sources[0x2d]	3234	1			T4	1		T5	2		T8	4
valid_sources[0x2e]	3995	1			T4	1		T5	2		T9	11
valid_sources[0x2f]	2853	1			T4	1		T5	5		T9	11
valid_sources[0x30]	3683	1			T5	8		T9	16		T58	4
valid_sources[0x31]	3347	1			T1	8		T4	1		T8	2
valid_sources[0x32]	2630	1			T4	1		T5	2		T8	3
valid_sources[0x33]	3803	1			T4	2		T5	1		T9	15
valid_sources[0x34]	2779	1			T1	8		T5	10		T8	10
valid_sources[0x35]	3721	1			T4	1		T5	2		T8	3
valid_sources[0x36]	3501	1			T1	3		T5	1		T8	4
valid_sources[0x37]	2980	1			T4	1		T5	2		T8	2
valid_sources[0x38]	3159	1			T3	3		T4	2		T5	8
valid_sources[0x39]	2551	1			T4	1		T5	7		T9	15
valid_sources[0x3a]	4269	1			T4	2		T5	1		T8	1
valid_sources[0x3b]	3610	1			T4	2		T5	4		T9	6
valid_sources[0x3c]	3500	1			T5	4		T9	7		T22	1
valid_sources[0x3d]	4384	1			T4	4		T9	14		T23	9
valid_sources[0x3e]	3367	1			T5	6		T9	15		T12	2
valid_sources[0x3f]	4023	1			T5	3		T8	2		T9	9
valid_sources[0x40]	3204	1			T4	3		T9	13		T12	3
valid_sources[0x41]	4014	1			T4	2		T5	1		T9	7
valid_sources[0x42]	2925	1			T4	1		T5	2		T8	1
valid_sources[0x43]	3017	1			T4	1		T5	1		T9	10
valid_sources[0x44]	3059	1			T1	6		T5	3		T8	2
valid_sources[0x45]	2975	1			T4	1		T5	4		T8	3
valid_sources[0x46]	3666	1			T5	7		T9	12		T12	1
valid_sources[0x47]	3629	1			T5	10		T8	2		T9	17
valid_sources[0x48]	4131	1			T3	9		T5	5		T9	13
valid_sources[0x49]	3087	1			T1	9		T3	7		T5	2
valid_sources[0x4a]	4441	1			T5	2		T9	14		T23	5
valid_sources[0x4b]	3320	1			T5	4		T9	10		T12	2
valid_sources[0x4c]	3677	1			T1	17		T4	1		T5	3
valid_sources[0x4d]	3405	1			T1	8		T5	4		T8	10
valid_sources[0x4e]	3468	1			T1	7		T5	6		T8	3
valid_sources[0x4f]	2563	1			T3	3		T4	1		T5	5
valid_sources[0x50]	3438	1			T3	7		T4	1		T5	3
valid_sources[0x51]	3328	1			T4	1		T5	1		T8	4
valid_sources[0x52]	3447	1			T5	2		T8	8		T9	8
valid_sources[0x53]	3086	1			T5	4		T8	5		T9	15
valid_sources[0x54]	4233	1			T4	2		T9	17		T12	2
valid_sources[0x55]	4134	1			T5	8		T8	1		T9	17
valid_sources[0x56]	3809	1			T5	4		T9	4		T23	2
valid_sources[0x57]	4961	1			T4	1		T5	5		T9	15
valid_sources[0x58]	3812	1			T4	1		T5	8		T9	14
valid_sources[0x59]	3280	1			T4	1		T5	6		T9	5
valid_sources[0x5a]	3631	1			T3	5		T4	1		T9	12
valid_sources[0x5b]	4384	1			T4	1		T5	2		T9	11
valid_sources[0x5c]	3441	1			T4	1		T5	2		T9	6
valid_sources[0x5d]	5633	1			T4	1		T5	3		T8	2
valid_sources[0x5e]	3793	1			T3	2		T4	1		T8	4
valid_sources[0x5f]	3298	1			T4	1		T5	2		T8	4
valid_sources[0x60]	4383	1			T4	3		T8	9		T9	12
valid_sources[0x61]	4152	1			T5	3		T9	14		T58	3
valid_sources[0x62]	2417	1			T5	6		T9	7		T23	20
valid_sources[0x63]	5541	1			T5	4		T9	10		T23	10
valid_sources[0x64]	3218	1			T3	1		T5	3		T8	1
valid_sources[0x65]	3249	1			T5	6		T9	16		T22	3
valid_sources[0x66]	3071	1			T3	13		T5	1		T8	3
valid_sources[0x67]	3710	1			T5	3		T9	17		T12	1
valid_sources[0x68]	3344	1			T1	1		T4	1		T5	4
valid_sources[0x69]	3030	1			T1	12		T5	3		T8	1
valid_sources[0x6a]	4084	1			T1	20		T4	1		T5	3
valid_sources[0x6b]	3107	1			T4	1		T5	2		T9	4
valid_sources[0x6c]	4388	1			T3	4		T5	3		T8	7
valid_sources[0x6d]	4206	1			T1	6		T4	1		T5	4
valid_sources[0x6e]	3389	1			T9	17		T70	2		T22	2
valid_sources[0x6f]	2595	1			T4	3		T5	5		T8	6
valid_sources[0x70]	5776	1			T5	5		T9	17		T12	2
valid_sources[0x71]	3702	1			T4	1		T5	7		T9	11
valid_sources[0x72]	2726	1			T4	2		T5	2		T9	10
valid_sources[0x73]	4111	1			T4	1		T8	3		T9	13
valid_sources[0x74]	3315	1			T3	1		T5	2		T9	11
valid_sources[0x75]	3655	1			T3	1		T4	1		T5	9
valid_sources[0x76]	2473	1			T4	1		T5	2		T8	1
valid_sources[0x77]	3265	1			T1	5		T3	2		T5	3
valid_sources[0x78]	6045	1			T4	1		T5	1		T9	3
valid_sources[0x79]	3465	1			T5	7		T9	11		T12	2
valid_sources[0x7a]	3028	1			T1	7		T4	2		T5	4
valid_sources[0x7b]	3283	1			T4	1		T5	1		T8	1
valid_sources[0x7c]	2521	1			T1	4		T5	6		T9	10
valid_sources[0x7d]	4657	1			T5	2		T9	19		T11	52
valid_sources[0x7e]	2935	1			T5	2		T9	15		T11	3
valid_sources[0x7f]	2930	1			T3	7		T4	1		T5	2
valid_sources[0x80]	5253	1			T5	3		T8	2		T9	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237596

1

T1

75

T3

35

T4

42

values[0x0]

all_enables

biggest_size

78029

1

T1

28

T3

12

T4

23

values[0x1]

all_enables

biggest_size

41822

1

T1

13

T3

4

T4

16