Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T58,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T58,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T58
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T58
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T58,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T58,T21
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T58
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12950076	13657	0	0
gen_assertions[0].RstEnOn_A	12950076	1122	0	0
gen_assertions[0].RstNOff_A	12950076	13657	0	0
gen_assertions[0].RstNOn_A	12950076	1122	0	0
gen_assertions[1].RstEnOff_A	51799992	12412	0	0
gen_assertions[1].RstEnOn_A	51799992	1053	0	0
gen_assertions[1].RstNOff_A	51799992	12412	0	0
gen_assertions[1].RstNOn_A	51799992	1053	0	0
gen_assertions[2].RstEnOff_A	25900741	12481	0	0
gen_assertions[2].RstEnOn_A	25900741	1063	0	0
gen_assertions[2].RstNOff_A	25900741	12481	0	0
gen_assertions[2].RstNOn_A	25900741	1063	0	0
gen_assertions[3].RstEnOff_A	25900854	12555	0	0
gen_assertions[3].RstEnOn_A	25900854	1126	0	0
gen_assertions[3].RstNOff_A	25900854	12555	0	0
gen_assertions[3].RstNOn_A	25900854	1126	0	0
gen_assertions[4].RstEnOff_A	1634584	21432	0	0
gen_assertions[4].RstEnOn_A	1634584	1154	0	0
gen_assertions[4].RstNOff_A	1634584	21432	0	0
gen_assertions[4].RstNOn_A	1634584	1154	0	0
gen_assertions[5].RstEnOff_A	12950076	13878	0	0
gen_assertions[5].RstEnOn_A	12950076	1183	0	0
gen_assertions[5].RstNOff_A	12950076	13878	0	0
gen_assertions[5].RstNOn_A	12950076	1183	0	0
gen_assertions[6].RstEnOff_A	12950076	13931	0	0
gen_assertions[6].RstEnOn_A	12950076	1248	0	0
gen_assertions[6].RstNOff_A	12950076	13931	0	0
gen_assertions[6].RstNOn_A	12950076	1248	0	0
gen_assertions[7].RstEnOff_A	12950076	13993	0	0
gen_assertions[7].RstEnOn_A	12950076	1309	0	0
gen_assertions[7].RstNOff_A	12950076	13993	0	0
gen_assertions[7].RstNOn_A	12950076	1309	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13657	0	0
T1	5965	5	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	4	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	5	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	5	0	0
T58	0	6	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1122	0	0
T1	5965	1	0	0
T2	4376	0	0	0
T3	3350	1	0	0
T4	2467	0	0	0
T5	10861	4	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	1	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T12	0	3	0	0
T21	0	1	0	0
T22	0	4	0	0
T54	0	1	0	0
T55	0	5	0	0
T58	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13657	0	0
T1	5965	5	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	4	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	5	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	5	0	0
T58	0	6	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1122	0	0
T1	5965	1	0	0
T2	4376	0	0	0
T3	3350	1	0	0
T4	2467	0	0	0
T5	10861	4	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	1	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T12	0	3	0	0
T21	0	1	0	0
T22	0	4	0	0
T54	0	1	0	0
T55	0	5	0	0
T58	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51799992	12412	0	0
T1	23867	4	0	0
T2	17510	0	0	0
T3	13404	5	0	0
T4	9872	3	0	0
T5	43448	6	0	0
T6	28789	0	0	0
T7	5589	0	0	0
T8	23688	3	0	0
T9	95102	35	0	0
T10	20952	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51799992	1053	0	0
T5	43448	6	0	0
T6	28789	0	0	0
T7	5589	0	0	0
T8	23688	0	0	0
T9	95102	0	0	0
T10	20952	0	0	0
T11	10525	0	0	0
T12	15368	0	0	0
T22	0	3	0	0
T24	28695	0	0	0
T37	0	3	0	0
T55	0	8	0	0
T58	0	4	0	0
T70	7198	0	0	0
T95	0	5	0	0
T96	0	2	0	0
T97	0	7	0	0
T98	0	3	0	0
T99	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51799992	12412	0	0
T1	23867	4	0	0
T2	17510	0	0	0
T3	13404	5	0	0
T4	9872	3	0	0
T5	43448	6	0	0
T6	28789	0	0	0
T7	5589	0	0	0
T8	23688	3	0	0
T9	95102	35	0	0
T10	20952	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51799992	1053	0	0
T5	43448	6	0	0
T6	28789	0	0	0
T7	5589	0	0	0
T8	23688	0	0	0
T9	95102	0	0	0
T10	20952	0	0	0
T11	10525	0	0	0
T12	15368	0	0	0
T22	0	3	0	0
T24	28695	0	0	0
T37	0	3	0	0
T55	0	8	0	0
T58	0	4	0	0
T70	7198	0	0	0
T95	0	5	0	0
T96	0	2	0	0
T97	0	7	0	0
T98	0	3	0	0
T99	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900741	12481	0	0
T1	11935	4	0	0
T2	8754	0	0	0
T3	6702	5	0	0
T4	4932	3	0	0
T5	21724	5	0	0
T6	14393	0	0	0
T7	2795	0	0	0
T8	11848	3	0	0
T9	47556	35	0	0
T10	10476	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	7	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900741	1063	0	0
T5	21724	5	0	0
T6	14393	0	0	0
T7	2795	0	0	0
T8	11848	0	0	0
T9	47556	0	0	0
T10	10476	0	0	0
T11	5261	0	0	0
T12	7684	0	0	0
T22	0	1	0	0
T24	14355	0	0	0
T37	0	5	0	0
T54	0	1	0	0
T55	0	7	0	0
T58	0	7	0	0
T70	3598	0	0	0
T95	0	7	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900741	12481	0	0
T1	11935	4	0	0
T2	8754	0	0	0
T3	6702	5	0	0
T4	4932	3	0	0
T5	21724	5	0	0
T6	14393	0	0	0
T7	2795	0	0	0
T8	11848	3	0	0
T9	47556	35	0	0
T10	10476	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	7	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900741	1063	0	0
T5	21724	5	0	0
T6	14393	0	0	0
T7	2795	0	0	0
T8	11848	0	0	0
T9	47556	0	0	0
T10	10476	0	0	0
T11	5261	0	0	0
T12	7684	0	0	0
T22	0	1	0	0
T24	14355	0	0	0
T37	0	5	0	0
T54	0	1	0	0
T55	0	7	0	0
T58	0	7	0	0
T70	3598	0	0	0
T95	0	7	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900854	12555	0	0
T1	11932	4	0	0
T2	8754	0	0	0
T3	6702	5	0	0
T4	4935	3	0	0
T5	21724	8	0	0
T6	14391	0	0	0
T7	2794	0	0	0
T8	11847	4	0	0
T9	47552	35	0	0
T10	10476	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	7	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900854	1126	0	0
T5	21724	8	0	0
T6	14391	0	0	0
T7	2794	0	0	0
T8	11847	1	0	0
T9	47552	0	0	0
T10	10476	0	0	0
T11	5262	0	0	0
T12	7684	0	0	0
T24	14353	0	0	0
T37	0	5	0	0
T54	0	1	0	0
T55	0	8	0	0
T58	0	7	0	0
T70	3598	0	0	0
T95	0	7	0	0
T96	0	3	0	0
T98	0	6	0	0
T100	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900854	12555	0	0
T1	11932	4	0	0
T2	8754	0	0	0
T3	6702	5	0	0
T4	4935	3	0	0
T5	21724	8	0	0
T6	14391	0	0	0
T7	2794	0	0	0
T8	11847	4	0	0
T9	47552	35	0	0
T10	10476	0	0	0
T11	0	4	0	0
T12	0	9	0	0
T21	0	4	0	0
T58	0	7	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25900854	1126	0	0
T5	21724	8	0	0
T6	14391	0	0	0
T7	2794	0	0	0
T8	11847	1	0	0
T9	47552	0	0	0
T10	10476	0	0	0
T11	5262	0	0	0
T12	7684	0	0	0
T24	14353	0	0	0
T37	0	5	0	0
T54	0	1	0	0
T55	0	8	0	0
T58	0	7	0	0
T70	3598	0	0	0
T95	0	7	0	0
T96	0	3	0	0
T98	0	6	0	0
T100	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1634584	21432	0	0
T1	745	6	0	0
T2	547	2	0	0
T3	417	9	0	0
T4	308	4	0	0
T5	1356	9	0	0
T6	902	2	0	0
T7	173	1	0	0
T8	740	6	0	0
T9	3072	59	0	0
T10	654	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1634584	1154	0	0
T5	1356	8	0	0
T6	902	0	0	0
T7	173	0	0	0
T8	740	1	0	0
T9	3072	0	0	0
T10	654	0	0	0
T11	327	0	0	0
T12	478	0	0	0
T21	0	1	0	0
T24	900	0	0	0
T37	0	5	0	0
T55	0	6	0	0
T58	0	11	0	0
T70	223	0	0	0
T95	0	9	0	0
T96	0	4	0	0
T98	0	7	0	0
T101	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1634584	21432	0	0
T1	745	6	0	0
T2	547	2	0	0
T3	417	9	0	0
T4	308	4	0	0
T5	1356	9	0	0
T6	902	2	0	0
T7	173	1	0	0
T8	740	6	0	0
T9	3072	59	0	0
T10	654	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1634584	1154	0	0
T5	1356	8	0	0
T6	902	0	0	0
T7	173	0	0	0
T8	740	1	0	0
T9	3072	0	0	0
T10	654	0	0	0
T11	327	0	0	0
T12	478	0	0	0
T21	0	1	0	0
T24	900	0	0	0
T37	0	5	0	0
T55	0	6	0	0
T58	0	11	0	0
T70	223	0	0	0
T95	0	9	0	0
T96	0	4	0	0
T98	0	7	0	0
T101	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13878	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	11	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	4	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	4	0	0
T58	0	11	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1183	0	0
T5	10861	11	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	0	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T24	7173	0	0	0
T36	0	1	0	0
T37	0	6	0	0
T55	0	11	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	11	0	0
T96	0	5	0	0
T98	0	7	0	0
T100	0	5	0	0
T102	0	27	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13878	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	11	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	4	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	4	0	0
T58	0	11	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1183	0	0
T5	10861	11	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	0	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T24	7173	0	0	0
T36	0	1	0	0
T37	0	6	0	0
T55	0	11	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	11	0	0
T96	0	5	0	0
T98	0	7	0	0
T100	0	5	0	0
T102	0	27	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13931	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	9	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	4	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	5	0	0
T58	0	11	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1248	0	0
T5	10861	9	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	0	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T21	0	1	0	0
T24	7173	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T55	0	10	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	9	0	0
T96	0	6	0	0
T98	0	9	0	0
T101	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13931	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	9	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	4	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	5	0	0
T58	0	11	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1248	0	0
T5	10861	9	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	0	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T21	0	1	0	0
T24	7173	0	0	0
T36	0	1	0	0
T37	0	9	0	0
T55	0	10	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	9	0	0
T96	0	6	0	0
T98	0	9	0	0
T101	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13993	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	12	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	5	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	4	0	0
T58	0	11	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1309	0	0
T5	10861	12	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	1	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T24	7173	0	0	0
T37	0	9	0	0
T54	0	1	0	0
T55	0	13	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	12	0	0
T96	0	8	0	0
T98	0	8	0	0
T103	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	13993	0	0
T1	5965	4	0	0
T2	4376	0	0	0
T3	3350	8	0	0
T4	2467	4	0	0
T5	10861	12	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	5	0	0
T9	23780	37	0	0
T10	5237	0	0	0
T11	0	4	0	0
T12	0	11	0	0
T21	0	4	0	0
T58	0	11	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12950076	1309	0	0
T5	10861	12	0	0
T6	7199	0	0	0
T7	1396	0	0	0
T8	5923	1	0	0
T9	23780	0	0	0
T10	5237	0	0	0
T11	2630	0	0	0
T12	3840	0	0	0
T24	7173	0	0	0
T37	0	9	0	0
T54	0	1	0	0
T55	0	13	0	0
T58	0	11	0	0
T70	1798	0	0	0
T95	0	12	0	0
T96	0	8	0	0
T98	0	8	0	0
T103	0	1	0	0