Unified Coverage Report :: Module

Module : rstmgr_por

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	91.67	91.67			88.89

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon	90.74	91.67	91.67			88.89

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	91.67	91.67			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.65	95.83	97.44			93.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_rst_clean_mux	100.00	100.00	100.00				100.00
u_rst_flop	100.00	100.00				100.00
u_rst_out_mux	100.00	100.00	100.00				100.00
u_rst_root_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_por

	Line No.	Total	Covered	Percent
TOTAL		12	11	91.67
ALWAYS	49	3	3	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	78	6	5	83.33



48                        always_ff @(posedge clk_i or negedge rst_root_n) begin
49         1/1              if (!rst_root_n) begin
           Tests:       T1 T2 T3 
50         1/1                rst_filter_n <= '0;
           Tests:       T1 T2 T3 
51                          end else begin
52         1/1                rst_filter_n <= {rst_filter_n[0 +: FilterStages-1], 1'b1};
           Tests:       T1 T2 T3 
53                          end
54                        end
55                      
56                        // The stable is a vote of all filter stages.
57                        // Only when all the stages agree is the reset considered stable and count allowed.
58                      
59                        prim_clock_mux2 #(
60                          .NoFpgaBufG(1'b1)
61                        ) u_rst_clean_mux (
62                          .clk0_i(rst_filter_n[FilterStages-1]),
63                          .clk1_i(scan_rst_ni),
64                          .sel_i(scanmode_i),
65                          .clk_o(rst_clean_n)
66                        );
67                      
68         1/1            assign rst_stable = &rst_filter_n;
           Tests:       T1 T2 T3 
69         1/1            assign cnt_en = rst_stable & !rst_no;
           Tests:       T1 T2 T3 
70                      
71                        // stretch the POR
72                        logic rst_nd, rst_nq;
73                      
74         1/1            assign rst_nd = ~rst_stable ? 1'b0 :
           Tests:       T1 T2 T3 
75                                        cnt_en & (cnt == StretchCount[CtrWidth-1:0]) ? 1'b1 : rst_nq;
76                      
77                        always_ff @(posedge clk_i or negedge rst_clean_n) begin
78         1/1              if (!rst_clean_n) begin
           Tests:       T1 T2 T3 
79         1/1                cnt <= '0;
           Tests:       T1 T2 T3 
80         1/1              end else if (!rst_stable) begin
           Tests:       T1 T2 T3 
81         0/1     ==>        cnt <= '0;
82         1/1              end else if (cnt_en) begin
           Tests:       T1 T2 T3 
83         1/1                cnt <= cnt + 1'b1;
           Tests:       T1 T2 T3 
84                          end
                        MISSING_ELSE

Cond Coverage for Module : rstmgr_por

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       69
 EXPRESSION (rst_stable & ((!rst_no)))
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (((~rst_stable)) ? 1'b0 : ((cnt_en & (cnt == StretchCount[(CtrWidth - 1):0])) ? 1'b1 : rst_nq))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION ((cnt_en & (cnt == StretchCount[(CtrWidth - 1):0])) ? 1'b1 : rst_nq)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION (cnt_en & (cnt == StretchCount[(CtrWidth - 1):0]))
                 ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION (cnt == StretchCount[(CtrWidth - 1):0])
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

Branch Coverage for Module : rstmgr_por

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	74	3	3	100.00
IF	49	2	2	100.00
IF	78	4	3	75.00



74           assign rst_nd = ~rst_stable ? 1'b0 :
                                         -1-  
                                         ==>  
75                           cnt_en & (cnt == StretchCount[CtrWidth-1:0]) ? 1'b1 : rst_nq;
                                                                          -2-  
                                                                          ==>  
                                                                          ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3



49             if (!rst_root_n) begin
               -1-  
50               rst_filter_n <= '0;
                 ==>
51             end else begin
52               rst_filter_n <= {rst_filter_n[0 +: FilterStages-1], 1'b1};
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



78             if (!rst_clean_n) begin
               -1-  
79               cnt <= '0;
                 ==>
80             end else if (!rst_stable) begin
                        -2-  
81               cnt <= '0;
                 ==>
82             end else if (cnt_en) begin
                        -3-  
83               cnt <= cnt + 1'b1;
                 ==>
84             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3