Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12346720	6872	0	0
alert_regwen_rd_A	12346720	4933	0	0
cpu_regwen_rd_A	12346720	5161	0	0
sw_rst_ctrl_n_0_rd_A	12346720	9694	0	0
sw_rst_ctrl_n_1_rd_A	12346720	9513	0	0
sw_rst_ctrl_n_2_rd_A	12346720	9398	0	0
sw_rst_ctrl_n_3_rd_A	12346720	9340	0	0
sw_rst_ctrl_n_4_rd_A	12346720	9540	0	0
sw_rst_ctrl_n_5_rd_A	12346720	9725	0	0
sw_rst_ctrl_n_6_rd_A	12346720	9414	0	0
sw_rst_ctrl_n_7_rd_A	12346720	9671	0	0
sw_rst_regwen_0_rd_A	12346720	5598	0	0
sw_rst_regwen_1_rd_A	12346720	5500	0	0
sw_rst_regwen_2_rd_A	12346720	5590	0	0
sw_rst_regwen_3_rd_A	12346720	5422	0	0
sw_rst_regwen_4_rd_A	12346720	5676	0	0
sw_rst_regwen_5_rd_A	12346720	5712	0	0
sw_rst_regwen_6_rd_A	12346720	5505	0	0
sw_rst_regwen_7_rd_A	12346720	5645	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	6872	0	0
T60	3391	20	0	0
T61	4750	505	0	0
T68	10958	873	0	0
T69	7373	342	0	0
T71	2846	9	0	0
T72	2993	5	0	0
T83	16935	3	0	0
T85	16740	2	0	0
T88	6220	313	0	0
T91	2845	168	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	4933	0	0
T17	2917	0	0	0
T26	27066	0	0	0
T50	26895	0	0	0
T96	2656	0	0	0
T101	2441	0	0	0
T107	37013	83	0	0
T109	0	55	0	0
T110	0	24	0	0
T113	0	65	0	0
T114	0	150	0	0
T115	0	40	0	0
T129	0	32	0	0
T130	0	39	0	0
T131	0	34	0	0
T132	0	306	0	0
T133	2615	0	0	0
T134	3383	0	0	0
T135	2465	0	0	0
T136	6523	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5161	0	0
T17	2917	0	0	0
T26	27066	0	0	0
T50	26895	0	0	0
T96	2656	0	0	0
T101	2441	0	0	0
T107	37013	59	0	0
T109	0	56	0	0
T110	0	29	0	0
T113	0	88	0	0
T114	0	146	0	0
T115	0	33	0	0
T129	0	51	0	0
T130	0	50	0	0
T131	0	30	0	0
T132	0	287	0	0
T133	2615	0	0	0
T134	3383	0	0	0
T135	2465	0	0	0
T136	6523	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9694	0	0
T1	5824	19	0	0
T2	4238	0	0	0
T3	2901	27	0	0
T4	2175	0	0	0
T5	10794	161	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	18	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	160	0	0
T40	0	29	0	0
T57	0	18	0	0
T95	0	132	0	0
T107	0	71	0	0
T137	0	19	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9513	0	0
T1	5824	17	0	0
T2	4238	0	0	0
T3	2901	29	0	0
T4	2175	0	0	0
T5	10794	174	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	11	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	166	0	0
T40	0	51	0	0
T57	0	20	0	0
T95	0	127	0	0
T107	0	92	0	0
T137	0	34	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9398	0	0
T1	5824	14	0	0
T2	4238	0	0	0
T3	2901	24	0	0
T4	2175	0	0	0
T5	10794	169	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	12	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	122	0	0
T40	0	48	0	0
T57	0	19	0	0
T95	0	102	0	0
T107	0	67	0	0
T137	0	38	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9340	0	0
T1	5824	25	0	0
T2	4238	0	0	0
T3	2901	22	0	0
T4	2175	0	0	0
T5	10794	141	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	7	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	143	0	0
T40	0	37	0	0
T57	0	19	0	0
T95	0	83	0	0
T107	0	86	0	0
T137	0	37	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9540	0	0
T1	5824	16	0	0
T2	4238	0	0	0
T3	2901	24	0	0
T4	2175	0	0	0
T5	10794	149	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	11	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	147	0	0
T40	0	50	0	0
T57	0	22	0	0
T95	0	115	0	0
T107	0	64	0	0
T137	0	31	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9725	0	0
T1	5824	21	0	0
T2	4238	0	0	0
T3	2901	20	0	0
T4	2175	0	0	0
T5	10794	152	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	17	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	129	0	0
T40	0	16	0	0
T57	0	16	0	0
T95	0	90	0	0
T107	0	55	0	0
T137	0	31	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9414	0	0
T1	5824	9	0	0
T2	4238	0	0	0
T3	2901	34	0	0
T4	2175	0	0	0
T5	10794	180	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	6	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	130	0	0
T40	0	20	0	0
T57	0	11	0	0
T95	0	93	0	0
T107	0	52	0	0
T137	0	41	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	9671	0	0
T1	5824	11	0	0
T2	4238	0	0	0
T3	2901	28	0	0
T4	2175	0	0	0
T5	10794	188	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	21	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	154	0	0
T40	0	35	0	0
T57	0	24	0	0
T95	0	135	0	0
T107	0	51	0	0
T137	0	30	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5598	0	0
T1	5824	3	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	28	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	1	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	33	0	0
T76	0	15	0	0
T95	0	16	0	0
T107	0	64	0	0
T109	0	59	0	0
T110	0	18	0	0
T138	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5500	0	0
T1	5824	6	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	23	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	5	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	42	0	0
T76	0	34	0	0
T95	0	22	0	0
T107	0	64	0	0
T109	0	48	0	0
T110	0	47	0	0
T139	0	10	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5590	0	0
T1	5824	6	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	27	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	1	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	19	0	0
T76	0	31	0	0
T95	0	16	0	0
T107	0	82	0	0
T109	0	61	0	0
T110	0	34	0	0
T138	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5422	0	0
T1	5824	7	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	37	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	6	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	40	0	0
T76	0	41	0	0
T95	0	40	0	0
T107	0	80	0	0
T109	0	40	0	0
T110	0	19	0	0
T138	0	6	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5676	0	0
T1	5824	4	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	21	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	14	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	30	0	0
T76	0	39	0	0
T95	0	21	0	0
T107	0	60	0	0
T109	0	68	0	0
T110	0	35	0	0
T138	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5712	0	0
T1	5824	2	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	18	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	8	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	35	0	0
T76	0	26	0	0
T95	0	27	0	0
T107	0	56	0	0
T109	0	67	0	0
T110	0	25	0	0
T138	0	17	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5505	0	0
T1	5824	1	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	28	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	10	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	33	0	0
T76	0	32	0	0
T95	0	35	0	0
T107	0	79	0	0
T109	0	54	0	0
T110	0	49	0	0
T138	0	3	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12346720	5645	0	0
T1	5824	10	0	0
T2	4238	0	0	0
T3	2901	0	0	0
T4	2175	0	0	0
T5	10794	50	0	0
T6	6275	0	0	0
T7	1378	0	0	0
T8	5824	6	0	0
T9	18813	0	0	0
T10	5099	0	0	0
T37	0	36	0	0
T76	0	32	0	0
T95	0	37	0	0
T107	0	56	0	0
T109	0	47	0	0
T110	0	38	0	0
T138	0	8	0	0