Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	595082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

355074

1

T1

129

T3

73

T4

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	504558	1			T1	186		T2	1		T3	91
values[0x0]	223004	1			T1	96		T3	39		T4	60
values[0x1]	222594	1			T1	97		T3	60		T4	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	499621	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

450535

1

T1

163

T2

1

T3

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3512	1			T5	9		T6	1		T11	12
valid_sources[0x01]	3290	1			T3	2		T5	8		T6	2
valid_sources[0x02]	3110	1			T1	1		T3	1		T4	1
valid_sources[0x03]	3315	1			T4	1		T5	19		T6	4
valid_sources[0x04]	6902	1			T3	2		T4	1		T5	16
valid_sources[0x05]	3253	1			T4	1		T5	9		T6	2
valid_sources[0x06]	3296	1			T1	6		T3	1		T5	17
valid_sources[0x07]	2819	1			T1	9		T5	17		T6	1
valid_sources[0x08]	3745	1			T5	10		T6	5		T11	14
valid_sources[0x09]	3325	1			T4	4		T5	14		T6	4
valid_sources[0x0a]	4582	1			T3	1		T4	1		T5	8
valid_sources[0x0b]	3334	1			T3	1		T5	9		T6	7
valid_sources[0x0c]	3514	1			T1	15		T4	2		T5	11
valid_sources[0x0d]	3457	1			T3	1		T5	11		T6	1
valid_sources[0x0e]	3100	1			T4	1		T5	12		T6	4
valid_sources[0x0f]	3151	1			T3	2		T4	1		T5	12
valid_sources[0x10]	3138	1			T1	3		T4	1		T5	10
valid_sources[0x11]	3455	1			T5	10		T6	2		T11	16
valid_sources[0x12]	3351	1			T4	2		T5	11		T6	3
valid_sources[0x13]	6432	1			T1	5		T3	1		T5	17
valid_sources[0x14]	3303	1			T3	1		T5	11		T6	2
valid_sources[0x15]	5225	1			T4	1		T5	16		T6	1
valid_sources[0x16]	3100	1			T1	2		T4	3		T5	9
valid_sources[0x17]	3364	1			T3	1		T5	14		T6	4
valid_sources[0x18]	6410	1			T3	1		T5	15		T6	2
valid_sources[0x19]	4199	1			T3	1		T5	16		T6	3
valid_sources[0x1a]	3079	1			T3	4		T5	5		T6	8
valid_sources[0x1b]	2894	1			T3	1		T4	1		T5	8
valid_sources[0x1c]	3184	1			T3	2		T4	2		T5	5
valid_sources[0x1d]	3490	1			T5	10		T6	1		T11	18
valid_sources[0x1e]	3190	1			T3	1		T5	22		T6	9
valid_sources[0x1f]	3784	1			T1	1		T5	8		T6	3
valid_sources[0x20]	2931	1			T1	1		T4	1		T5	16
valid_sources[0x21]	4858	1			T3	1		T4	1		T5	11
valid_sources[0x22]	3637	1			T4	1		T5	14		T6	11
valid_sources[0x23]	3355	1			T3	1		T4	1		T5	10
valid_sources[0x24]	3296	1			T3	2		T4	3		T5	16
valid_sources[0x25]	3223	1			T1	6		T3	1		T4	3
valid_sources[0x26]	2763	1			T1	6		T5	13		T6	3
valid_sources[0x27]	3052	1			T4	2		T5	6		T6	6
valid_sources[0x28]	3111	1			T1	1		T4	1		T5	8
valid_sources[0x29]	6139	1			T4	1		T5	12		T6	4
valid_sources[0x2a]	3324	1			T3	4		T4	1		T5	21
valid_sources[0x2b]	5388	1			T1	4		T4	1		T5	8
valid_sources[0x2c]	3733	1			T5	7		T11	12		T12	1
valid_sources[0x2d]	4630	1			T3	1		T5	13		T6	9
valid_sources[0x2e]	3950	1			T1	7		T5	8		T6	3
valid_sources[0x2f]	3418	1			T4	1		T5	7		T11	10
valid_sources[0x30]	2930	1			T4	1		T5	10		T6	5
valid_sources[0x31]	3585	1			T4	3		T5	20		T6	3
valid_sources[0x32]	2766	1			T3	1		T4	2		T5	12
valid_sources[0x33]	3674	1			T1	2		T3	4		T4	1
valid_sources[0x34]	3334	1			T1	13		T5	12		T6	12
valid_sources[0x35]	3366	1			T1	1		T3	2		T4	1
valid_sources[0x36]	3437	1			T4	1		T5	10		T6	6
valid_sources[0x37]	3364	1			T1	2		T3	1		T4	1
valid_sources[0x38]	3294	1			T3	2		T5	15		T6	3
valid_sources[0x39]	4027	1			T3	2		T5	16		T6	4
valid_sources[0x3a]	3540	1			T3	1		T5	9		T6	2
valid_sources[0x3b]	3606	1			T3	1		T4	3		T5	6
valid_sources[0x3c]	2868	1			T5	14		T6	2		T11	14
valid_sources[0x3d]	3670	1			T5	8		T6	3		T11	18
valid_sources[0x3e]	4601	1			T3	1		T4	1		T5	7
valid_sources[0x3f]	3724	1			T3	2		T4	3		T5	11
valid_sources[0x40]	3390	1			T5	11		T11	10		T13	1
valid_sources[0x41]	3772	1			T3	1		T4	3		T5	18
valid_sources[0x42]	4238	1			T3	1		T4	1		T5	11
valid_sources[0x43]	2865	1			T5	11		T6	6		T11	10
valid_sources[0x44]	3300	1			T3	1		T4	1		T5	7
valid_sources[0x45]	6971	1			T3	2		T5	10		T6	1
valid_sources[0x46]	3677	1			T4	1		T5	11		T6	4
valid_sources[0x47]	3294	1			T3	1		T5	7		T6	8
valid_sources[0x48]	3975	1			T5	9		T6	4		T11	14
valid_sources[0x49]	3820	1			T5	9		T6	6		T11	10
valid_sources[0x4a]	3259	1			T3	3		T4	1		T5	10
valid_sources[0x4b]	3288	1			T3	1		T4	2		T5	15
valid_sources[0x4c]	3146	1			T4	1		T5	20		T6	5
valid_sources[0x4d]	3409	1			T3	3		T4	1		T5	12
valid_sources[0x4e]	3453	1			T5	9		T6	3		T11	10
valid_sources[0x4f]	3877	1			T5	15		T6	4		T11	13
valid_sources[0x50]	3870	1			T5	5		T6	5		T11	9
valid_sources[0x51]	2956	1			T1	5		T3	2		T5	19
valid_sources[0x52]	2808	1			T3	2		T4	1		T5	16
valid_sources[0x53]	3259	1			T4	2		T5	18		T11	10
valid_sources[0x54]	3875	1			T3	2		T4	1		T5	10
valid_sources[0x55]	4226	1			T3	2		T4	1		T5	16
valid_sources[0x56]	3010	1			T5	14		T6	1		T11	13
valid_sources[0x57]	2943	1			T5	21		T6	4		T11	12
valid_sources[0x58]	3623	1			T4	1		T5	21		T6	3
valid_sources[0x59]	3917	1			T3	3		T4	1		T5	14
valid_sources[0x5a]	3329	1			T1	4		T5	10		T6	10
valid_sources[0x5b]	4355	1			T5	10		T6	2		T11	12
valid_sources[0x5c]	3009	1			T1	18		T3	2		T5	10
valid_sources[0x5d]	2831	1			T5	5		T6	5		T11	6
valid_sources[0x5e]	3003	1			T3	3		T5	15		T6	3
valid_sources[0x5f]	3359	1			T1	1		T3	1		T5	23
valid_sources[0x60]	4084	1			T1	3		T3	2		T4	1
valid_sources[0x61]	2782	1			T5	12		T6	6		T11	9
valid_sources[0x62]	3772	1			T3	2		T5	13		T6	8
valid_sources[0x63]	7182	1			T3	1		T5	11		T6	7
valid_sources[0x64]	2998	1			T3	2		T5	12		T6	8
valid_sources[0x65]	3483	1			T5	8		T6	15		T11	16
valid_sources[0x66]	3558	1			T1	6		T3	1		T5	11
valid_sources[0x67]	3213	1			T4	1		T5	9		T6	5
valid_sources[0x68]	3138	1			T3	1		T5	12		T6	3
valid_sources[0x69]	4315	1			T4	2		T5	5		T6	5
valid_sources[0x6a]	4379	1			T3	2		T4	2		T5	17
valid_sources[0x6b]	3780	1			T4	1		T5	9		T6	1
valid_sources[0x6c]	3773	1			T3	2		T5	21		T6	10
valid_sources[0x6d]	3555	1			T1	28		T5	10		T6	12
valid_sources[0x6e]	4572	1			T3	3		T5	10		T6	4
valid_sources[0x6f]	3366	1			T4	3		T5	3		T6	3
valid_sources[0x70]	4059	1			T4	1		T5	9		T6	6
valid_sources[0x71]	2854	1			T3	1		T5	14		T6	2
valid_sources[0x72]	4392	1			T4	2		T5	10		T6	3
valid_sources[0x73]	3158	1			T4	2		T5	14		T6	7
valid_sources[0x74]	3927	1			T1	2		T3	1		T4	3
valid_sources[0x75]	6857	1			T5	15		T6	4		T11	7
valid_sources[0x76]	3093	1			T1	2		T3	2		T4	2
valid_sources[0x77]	3088	1			T3	1		T4	1		T5	13
valid_sources[0x78]	4702	1			T5	8		T6	1		T11	17
valid_sources[0x79]	3500	1			T1	10		T4	1		T5	15
valid_sources[0x7a]	3239	1			T1	4		T3	1		T5	20
valid_sources[0x7b]	3554	1			T3	1		T4	2		T5	12
valid_sources[0x7c]	4461	1			T1	9		T3	3		T5	10
valid_sources[0x7d]	3538	1			T3	1		T5	14		T6	8
valid_sources[0x7e]	3182	1			T1	7		T4	1		T5	14
valid_sources[0x7f]	4012	1			T3	1		T4	1		T5	11
valid_sources[0x80]	4651	1			T4	1		T5	13		T6	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235894

1

T1

81

T3

42

T4

51

values[0x0]

all_enables

biggest_size

77849

1

T1

31

T3

20

T4

14

values[0x1]

all_enables

biggest_size

41331

1

T1

17

T3

11

T4

9