Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T58
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T58
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T58,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T58,T23
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T58,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T58
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12818302	13729	0	0
gen_assertions[0].RstEnOn_A	12818302	1012	0	0
gen_assertions[0].RstNOff_A	12818302	13729	0	0
gen_assertions[0].RstNOn_A	12818302	1012	0	0
gen_assertions[1].RstEnOff_A	51272828	12488	0	0
gen_assertions[1].RstEnOn_A	51272828	993	0	0
gen_assertions[1].RstNOff_A	51272828	12488	0	0
gen_assertions[1].RstNOn_A	51272828	993	0	0
gen_assertions[2].RstEnOff_A	25637237	12508	0	0
gen_assertions[2].RstEnOn_A	25637237	950	0	0
gen_assertions[2].RstNOff_A	25637237	12508	0	0
gen_assertions[2].RstNOn_A	25637237	950	0	0
gen_assertions[3].RstEnOff_A	25637203	12574	0	0
gen_assertions[3].RstEnOn_A	25637203	1012	0	0
gen_assertions[3].RstNOff_A	25637203	12574	0	0
gen_assertions[3].RstNOn_A	25637203	1012	0	0
gen_assertions[4].RstEnOff_A	1618250	21174	0	0
gen_assertions[4].RstEnOn_A	1618250	1053	0	0
gen_assertions[4].RstNOff_A	1618250	21174	0	0
gen_assertions[4].RstNOn_A	1618250	1053	0	0
gen_assertions[5].RstEnOff_A	12818302	13969	0	0
gen_assertions[5].RstEnOn_A	12818302	1107	0	0
gen_assertions[5].RstNOff_A	12818302	13969	0	0
gen_assertions[5].RstNOn_A	12818302	1107	0	0
gen_assertions[6].RstEnOff_A	12818302	14009	0	0
gen_assertions[6].RstEnOn_A	12818302	1145	0	0
gen_assertions[6].RstNOff_A	12818302	14009	0	0
gen_assertions[6].RstNOn_A	12818302	1145	0	0
gen_assertions[7].RstEnOff_A	12818302	14082	0	0
gen_assertions[7].RstEnOn_A	12818302	1209	0	0
gen_assertions[7].RstNOff_A	12818302	14082	0	0
gen_assertions[7].RstNOn_A	12818302	1209	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	13729	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	8	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	7	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1012	0	0
T3	2425	2	0	0
T4	2312	0	0	0
T5	23957	0	0	0
T6	12888	8	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	5	0	0
T23	0	1	0	0
T36	0	1	0	0
T38	0	28	0	0
T41	0	3	0	0
T58	0	7	0	0
T81	0	1	0	0
T82	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	13729	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	8	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	7	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1012	0	0
T3	2425	2	0	0
T4	2312	0	0	0
T5	23957	0	0	0
T6	12888	8	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	5	0	0
T23	0	1	0	0
T36	0	1	0	0
T38	0	28	0	0
T41	0	3	0	0
T58	0	7	0	0
T81	0	1	0	0
T82	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51272828	12488	0	0
T1	18523	5	0	0
T2	7818	0	0	0
T3	9706	9	0	0
T4	9244	4	0	0
T5	95809	33	0	0
T6	51553	8	0	0
T7	28752	0	0	0
T8	7190	0	0	0
T9	21483	5	0	0
T10	22018	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	9	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51272828	993	0	0
T1	18523	1	0	0
T2	7818	0	0	0
T3	9706	5	0	0
T4	9244	0	0	0
T5	95809	0	0	0
T6	51553	8	0	0
T7	28752	0	0	0
T8	7190	0	0	0
T9	21483	1	0	0
T10	22018	0	0	0
T36	0	2	0	0
T38	0	32	0	0
T41	0	3	0	0
T58	0	9	0	0
T81	0	1	0	0
T83	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51272828	12488	0	0
T1	18523	5	0	0
T2	7818	0	0	0
T3	9706	9	0	0
T4	9244	4	0	0
T5	95809	33	0	0
T6	51553	8	0	0
T7	28752	0	0	0
T8	7190	0	0	0
T9	21483	5	0	0
T10	22018	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	9	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51272828	993	0	0
T1	18523	1	0	0
T2	7818	0	0	0
T3	9706	5	0	0
T4	9244	0	0	0
T5	95809	0	0	0
T6	51553	8	0	0
T7	28752	0	0	0
T8	7190	0	0	0
T9	21483	1	0	0
T10	22018	0	0	0
T36	0	2	0	0
T38	0	32	0	0
T41	0	3	0	0
T58	0	9	0	0
T81	0	1	0	0
T83	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637237	12508	0	0
T1	9261	4	0	0
T2	3907	0	0	0
T3	4852	9	0	0
T4	4622	4	0	0
T5	47915	33	0	0
T6	25778	6	0	0
T7	14379	0	0	0
T8	3594	0	0	0
T9	10741	5	0	0
T10	11008	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	8	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637237	950	0	0
T6	25778	6	0	0
T7	14379	0	0	0
T8	3594	0	0	0
T9	10741	1	0	0
T10	11008	0	0	0
T11	93680	0	0	0
T12	10362	0	0	0
T13	6984	0	0	0
T24	14415	0	0	0
T36	0	3	0	0
T38	0	28	0	0
T41	0	6	0	0
T48	0	4	0	0
T52	0	3	0	0
T55	0	1	0	0
T58	24621	8	0	0
T83	0	5	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637237	12508	0	0
T1	9261	4	0	0
T2	3907	0	0	0
T3	4852	9	0	0
T4	4622	4	0	0
T5	47915	33	0	0
T6	25778	6	0	0
T7	14379	0	0	0
T8	3594	0	0	0
T9	10741	5	0	0
T10	11008	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	8	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637237	950	0	0
T6	25778	6	0	0
T7	14379	0	0	0
T8	3594	0	0	0
T9	10741	1	0	0
T10	11008	0	0	0
T11	93680	0	0	0
T12	10362	0	0	0
T13	6984	0	0	0
T24	14415	0	0	0
T36	0	3	0	0
T38	0	28	0	0
T41	0	6	0	0
T48	0	4	0	0
T52	0	3	0	0
T55	0	1	0	0
T58	24621	8	0	0
T83	0	5	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637203	12574	0	0
T1	9262	4	0	0
T2	3907	0	0	0
T3	4852	9	0	0
T4	4624	4	0	0
T5	47906	33	0	0
T6	25777	11	0	0
T7	14371	0	0	0
T8	3595	0	0	0
T9	10740	5	0	0
T10	11008	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	9	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637203	1012	0	0
T6	25777	11	0	0
T7	14371	0	0	0
T8	3595	0	0	0
T9	10740	1	0	0
T10	11008	0	0	0
T11	93683	0	0	0
T12	10362	0	0	0
T13	6985	0	0	0
T23	0	1	0	0
T24	14412	0	0	0
T36	0	4	0	0
T38	0	30	0	0
T41	0	6	0	0
T48	0	4	0	0
T58	24621	9	0	0
T79	0	1	0	0
T83	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637203	12574	0	0
T1	9262	4	0	0
T2	3907	0	0	0
T3	4852	9	0	0
T4	4624	4	0	0
T5	47906	33	0	0
T6	25777	11	0	0
T7	14371	0	0	0
T8	3595	0	0	0
T9	10740	5	0	0
T10	11008	0	0	0
T11	0	67	0	0
T12	0	12	0	0
T13	0	4	0	0
T58	0	9	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25637203	1012	0	0
T6	25777	11	0	0
T7	14371	0	0	0
T8	3595	0	0	0
T9	10740	1	0	0
T10	11008	0	0	0
T11	93683	0	0	0
T12	10362	0	0	0
T13	6985	0	0	0
T23	0	1	0	0
T24	14412	0	0	0
T36	0	4	0	0
T38	0	30	0	0
T41	0	6	0	0
T48	0	4	0	0
T58	24621	9	0	0
T79	0	1	0	0
T83	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1618250	21174	0	0
T1	578	6	0	0
T2	244	2	0	0
T3	302	9	0	0
T4	287	5	0	0
T5	3053	61	0	0
T6	1609	12	0	0
T7	902	2	0	0
T8	224	1	0	0
T9	671	6	0	0
T10	687	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1618250	1053	0	0
T6	1609	11	0	0
T7	902	0	0	0
T8	224	0	0	0
T9	671	0	0	0
T10	687	0	0	0
T11	5869	0	0	0
T12	646	0	0	0
T13	436	0	0	0
T24	903	0	0	0
T36	0	5	0	0
T38	0	27	0	0
T41	0	4	0	0
T48	0	6	0	0
T52	0	3	0	0
T58	1537	9	0	0
T83	0	6	0	0
T84	0	10	0	0
T85	0	11	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1618250	21174	0	0
T1	578	6	0	0
T2	244	2	0	0
T3	302	9	0	0
T4	287	5	0	0
T5	3053	61	0	0
T6	1609	12	0	0
T7	902	2	0	0
T8	224	1	0	0
T9	671	6	0	0
T10	687	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1618250	1053	0	0
T6	1609	11	0	0
T7	902	0	0	0
T8	224	0	0	0
T9	671	0	0	0
T10	687	0	0	0
T11	5869	0	0	0
T12	646	0	0	0
T13	436	0	0	0
T24	903	0	0	0
T36	0	5	0	0
T38	0	27	0	0
T41	0	4	0	0
T48	0	6	0	0
T52	0	3	0	0
T58	1537	9	0	0
T83	0	6	0	0
T84	0	10	0	0
T85	0	11	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	13969	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	12	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	11	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1107	0	0
T6	12888	12	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	0	0	0
T13	3493	0	0	0
T23	0	1	0	0
T24	7204	0	0	0
T36	0	6	0	0
T38	0	20	0	0
T41	0	5	0	0
T48	0	6	0	0
T52	0	4	0	0
T58	12309	11	0	0
T83	0	8	0	0
T84	0	8	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	13969	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	12	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	11	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1107	0	0
T6	12888	12	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	0	0	0
T13	3493	0	0	0
T23	0	1	0	0
T24	7204	0	0	0
T36	0	6	0	0
T38	0	20	0	0
T41	0	5	0	0
T48	0	6	0	0
T52	0	4	0	0
T58	12309	11	0	0
T83	0	8	0	0
T84	0	8	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	14009	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	13	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	10	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1145	0	0
T6	12888	13	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	0	0	0
T13	3493	0	0	0
T24	7204	0	0	0
T36	0	6	0	0
T38	0	20	0	0
T41	0	5	0	0
T48	0	8	0	0
T52	0	3	0	0
T58	12309	10	0	0
T83	0	9	0	0
T84	0	10	0	0
T85	0	13	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	14009	0	0
T1	4629	4	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	13	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	10	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1145	0	0
T6	12888	13	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T11	46844	0	0	0
T12	5180	0	0	0
T13	3493	0	0	0
T24	7204	0	0	0
T36	0	6	0	0
T38	0	20	0	0
T41	0	5	0	0
T48	0	8	0	0
T52	0	3	0	0
T58	12309	10	0	0
T83	0	9	0	0
T84	0	10	0	0
T85	0	13	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	14082	0	0
T1	4629	5	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	15	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	14	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1209	0	0
T1	4629	1	0	0
T2	1953	0	0	0
T3	2425	0	0	0
T4	2312	0	0	0
T5	23957	0	0	0
T6	12888	15	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T36	0	7	0	0
T38	0	27	0	0
T41	0	6	0	0
T48	0	9	0	0
T52	0	5	0	0
T58	0	14	0	0
T83	0	12	0	0
T84	0	11	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	14082	0	0
T1	4629	5	0	0
T2	1953	0	0	0
T3	2425	9	0	0
T4	2312	4	0	0
T5	23957	40	0	0
T6	12888	15	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	4	0	0
T10	5504	0	0	0
T11	0	78	0	0
T12	0	15	0	0
T13	0	4	0	0
T58	0	14	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12818302	1209	0	0
T1	4629	1	0	0
T2	1953	0	0	0
T3	2425	0	0	0
T4	2312	0	0	0
T5	23957	0	0	0
T6	12888	15	0	0
T7	7189	0	0	0
T8	1797	0	0	0
T9	5369	0	0	0
T10	5504	0	0	0
T36	0	7	0	0
T38	0	27	0	0
T41	0	6	0	0
T48	0	9	0	0
T52	0	5	0	0
T58	0	14	0	0
T83	0	12	0	0
T84	0	11	0	0