Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12064559	9145	0	0
alert_regwen_rd_A	12064559	5067	0	0
cpu_regwen_rd_A	12064559	4980	0	0
sw_rst_ctrl_n_0_rd_A	12064559	11339	0	0
sw_rst_ctrl_n_1_rd_A	12064559	11269	0	0
sw_rst_ctrl_n_2_rd_A	12064559	11281	0	0
sw_rst_ctrl_n_3_rd_A	12064559	11287	0	0
sw_rst_ctrl_n_4_rd_A	12064559	11325	0	0
sw_rst_ctrl_n_5_rd_A	12064559	11353	0	0
sw_rst_ctrl_n_6_rd_A	12064559	11207	0	0
sw_rst_ctrl_n_7_rd_A	12064559	11298	0	0
sw_rst_regwen_0_rd_A	12064559	5859	0	0
sw_rst_regwen_1_rd_A	12064559	5841	0	0
sw_rst_regwen_2_rd_A	12064559	5674	0	0
sw_rst_regwen_3_rd_A	12064559	5925	0	0
sw_rst_regwen_4_rd_A	12064559	5434	0	0
sw_rst_regwen_5_rd_A	12064559	5501	0	0
sw_rst_regwen_6_rd_A	12064559	5698	0	0
sw_rst_regwen_7_rd_A	12064559	5841	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	9145	0	0
T70	12196	576	0	0
T71	9386	2	0	0
T72	4573	201	0	0
T73	5541	307	0	0
T74	11166	2	0	0
T88	5112	172	0	0
T89	4843	375	0	0
T90	4682	15	0	0
T94	17105	4	0	0
T115	10097	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5067	0	0
T14	2800	0	0	0
T22	45529	84	0	0
T23	2646	0	0	0
T25	43886	0	0	0
T35	2424	0	0	0
T36	2497	0	0	0
T37	3516	0	0	0
T38	155053	228	0	0
T39	6515	0	0	0
T40	28317	0	0	0
T77	0	60	0	0
T99	0	41	0	0
T101	0	27	0	0
T121	0	12	0	0
T122	0	100	0	0
T123	0	45	0	0
T124	0	175	0	0
T125	0	59	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	4980	0	0
T14	2800	0	0	0
T22	45529	71	0	0
T23	2646	0	0	0
T25	43886	0	0	0
T35	2424	0	0	0
T36	2497	0	0	0
T37	3516	0	0	0
T38	155053	197	0	0
T39	6515	0	0	0
T40	28317	0	0	0
T77	0	78	0	0
T99	0	34	0	0
T101	0	53	0	0
T121	0	36	0	0
T122	0	115	0	0
T123	0	34	0	0
T124	0	146	0	0
T125	0	68	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11339	0	0
T6	12868	184	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	13	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	23	0	0
T13	3202	0	0	0
T22	0	79	0	0
T24	6284	0	0	0
T38	0	593	0	0
T58	12243	176	0	0
T77	0	67	0	0
T83	0	181	0	0
T85	0	227	0	0
T126	0	48	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11269	0	0
T6	12868	221	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	10	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	40	0	0
T13	3202	0	0	0
T22	0	98	0	0
T24	6284	0	0	0
T38	0	501	0	0
T58	12243	165	0	0
T77	0	62	0	0
T83	0	123	0	0
T85	0	191	0	0
T126	0	48	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11281	0	0
T6	12868	207	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	13	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	27	0	0
T13	3202	0	0	0
T22	0	91	0	0
T24	6284	0	0	0
T38	0	537	0	0
T58	12243	207	0	0
T77	0	69	0	0
T83	0	155	0	0
T85	0	227	0	0
T126	0	65	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11287	0	0
T6	12868	208	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	6	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	23	0	0
T13	3202	0	0	0
T22	0	68	0	0
T24	6284	0	0	0
T38	0	482	0	0
T58	12243	233	0	0
T77	0	40	0	0
T83	0	167	0	0
T85	0	209	0	0
T126	0	74	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11325	0	0
T6	12868	227	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	10	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	40	0	0
T13	3202	0	0	0
T22	0	62	0	0
T24	6284	0	0	0
T38	0	473	0	0
T58	12243	194	0	0
T77	0	68	0	0
T83	0	202	0	0
T85	0	266	0	0
T126	0	47	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11353	0	0
T6	12868	222	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	5	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	33	0	0
T13	3202	0	0	0
T22	0	82	0	0
T24	6284	0	0	0
T38	0	524	0	0
T58	12243	171	0	0
T77	0	48	0	0
T83	0	143	0	0
T85	0	229	0	0
T126	0	49	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11207	0	0
T6	12868	195	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	4	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	25	0	0
T13	3202	0	0	0
T22	0	92	0	0
T24	6284	0	0	0
T38	0	513	0	0
T58	12243	213	0	0
T77	0	75	0	0
T83	0	170	0	0
T85	0	192	0	0
T126	0	48	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	11298	0	0
T6	12868	247	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	8	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	35	0	0
T13	3202	0	0	0
T22	0	89	0	0
T24	6284	0	0	0
T38	0	514	0	0
T58	12243	214	0	0
T77	0	68	0	0
T83	0	142	0	0
T85	0	230	0	0
T126	0	53	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5859	0	0
T6	12868	24	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	0	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	104	0	0
T24	6284	0	0	0
T38	0	173	0	0
T58	12243	30	0	0
T77	0	83	0	0
T83	0	25	0	0
T85	0	29	0	0
T99	0	39	0	0
T127	0	2	0	0
T128	0	9	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5841	0	0
T6	12868	35	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	0	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	83	0	0
T24	6284	0	0	0
T38	0	220	0	0
T58	12243	28	0	0
T77	0	66	0	0
T83	0	27	0	0
T85	0	23	0	0
T99	0	44	0	0
T127	0	4	0	0
T128	0	8	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5674	0	0
T6	12868	26	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	0	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	71	0	0
T24	6284	0	0	0
T38	0	211	0	0
T58	12243	55	0	0
T77	0	50	0	0
T83	0	36	0	0
T85	0	27	0	0
T99	0	25	0	0
T127	0	1	0	0
T128	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5925	0	0
T6	12868	21	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	0	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	90	0	0
T24	6284	0	0	0
T38	0	184	0	0
T58	12243	30	0	0
T77	0	70	0	0
T83	0	44	0	0
T85	0	30	0	0
T99	0	46	0	0
T127	0	9	0	0
T128	0	7	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5434	0	0
T6	12868	36	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	7	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	77	0	0
T24	6284	0	0	0
T38	0	188	0	0
T58	12243	27	0	0
T77	0	45	0	0
T83	0	27	0	0
T85	0	29	0	0
T99	0	31	0	0
T127	0	6	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5501	0	0
T6	12868	29	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	1	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	53	0	0
T24	6284	0	0	0
T38	0	207	0	0
T58	12243	38	0	0
T77	0	67	0	0
T83	0	41	0	0
T85	0	53	0	0
T99	0	28	0	0
T128	0	3	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5698	0	0
T6	12868	34	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	2	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	80	0	0
T24	6284	0	0	0
T38	0	185	0	0
T58	12243	44	0	0
T77	0	55	0	0
T83	0	35	0	0
T85	0	29	0	0
T99	0	22	0	0
T127	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12064559	5841	0	0
T6	12868	33	0	0
T7	6746	0	0	0
T8	1706	0	0	0
T9	5228	12	0	0
T10	5389	0	0	0
T11	43568	0	0	0
T12	4304	0	0	0
T13	3202	0	0	0
T22	0	73	0	0
T24	6284	0	0	0
T38	0	233	0	0
T58	12243	17	0	0
T77	0	43	0	0
T83	0	30	0	0
T85	0	38	0	0
T99	0	32	0	0
T127	0	11	0	0