Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	649565	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

388316

1

T1

130

T3

68

T4

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	553870	1			T1	186		T2	1		T3	99
values[0x0]	242102	1			T1	104		T3	56		T4	33
values[0x1]	241909	1			T1	89		T3	57		T4	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	545051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

492830

1

T1

164

T2

1

T3

89

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3525	1			T1	1		T3	212		T8	6
valid_sources[0x01]	4198	1			T1	2		T8	1		T10	8
valid_sources[0x02]	4094	1			T1	3		T4	2		T10	12
valid_sources[0x03]	3927	1			T1	2		T8	2		T10	6
valid_sources[0x04]	3761	1			T1	1		T8	3		T10	13
valid_sources[0x05]	3990	1			T1	2		T4	1		T8	2
valid_sources[0x06]	3652	1			T1	2		T8	1		T10	7
valid_sources[0x07]	5161	1			T1	1		T4	1		T8	1
valid_sources[0x08]	3194	1			T1	2		T4	1		T8	1
valid_sources[0x09]	3535	1			T1	4		T8	3		T10	18
valid_sources[0x0a]	3644	1			T1	1		T8	1		T10	14
valid_sources[0x0b]	3522	1			T1	2		T8	3		T10	7
valid_sources[0x0c]	3946	1			T1	2		T8	4		T10	7
valid_sources[0x0d]	3046	1			T1	5		T10	16		T11	3
valid_sources[0x0e]	5524	1			T1	3		T10	3		T13	3
valid_sources[0x0f]	3302	1			T1	2		T8	1		T10	10
valid_sources[0x10]	3752	1			T8	3		T10	5		T11	1
valid_sources[0x11]	3942	1			T8	2		T10	4		T13	9
valid_sources[0x12]	3726	1			T1	2		T8	1		T10	11
valid_sources[0x13]	4506	1			T1	1		T10	3		T13	15
valid_sources[0x14]	4684	1			T8	2		T10	11		T13	15
valid_sources[0x15]	3425	1			T8	5		T10	9		T11	1
valid_sources[0x16]	4432	1			T1	1		T8	1		T10	9
valid_sources[0x17]	2977	1			T10	7		T13	2		T22	6
valid_sources[0x18]	3742	1			T1	1		T4	1		T10	6
valid_sources[0x19]	3877	1			T1	2		T8	3		T10	5
valid_sources[0x1a]	3607	1			T1	4		T8	1		T10	7
valid_sources[0x1b]	6795	1			T1	2		T8	1		T10	8
valid_sources[0x1c]	7491	1			T1	2		T10	6		T11	1
valid_sources[0x1d]	3297	1			T1	2		T8	1		T10	6
valid_sources[0x1e]	4075	1			T1	3		T4	1		T8	1
valid_sources[0x1f]	3345	1			T1	1		T10	12		T11	1
valid_sources[0x20]	3699	1			T1	2		T8	3		T10	7
valid_sources[0x21]	3946	1			T1	5		T10	9		T11	3
valid_sources[0x22]	4090	1			T1	3		T8	1		T10	9
valid_sources[0x23]	3368	1			T1	1		T8	4		T10	7
valid_sources[0x24]	3583	1			T1	3		T8	3		T10	11
valid_sources[0x25]	2918	1			T8	3		T10	8		T11	1
valid_sources[0x26]	3417	1			T1	4		T4	2		T8	4
valid_sources[0x27]	4005	1			T1	1		T8	1		T10	5
valid_sources[0x28]	3944	1			T1	2		T6	1		T8	4
valid_sources[0x29]	6056	1			T10	8		T11	1		T13	12
valid_sources[0x2a]	4035	1			T1	1		T8	1		T10	10
valid_sources[0x2b]	4237	1			T1	3		T10	13		T13	12
valid_sources[0x2c]	3425	1			T1	1		T8	1		T10	8
valid_sources[0x2d]	3106	1			T1	2		T4	2		T8	2
valid_sources[0x2e]	3350	1			T1	5		T4	2		T8	3
valid_sources[0x2f]	3597	1			T1	2		T8	1		T10	7
valid_sources[0x30]	4788	1			T8	2		T10	14		T11	1
valid_sources[0x31]	3604	1			T1	1		T10	4		T11	2
valid_sources[0x32]	3440	1			T4	1		T8	3		T10	6
valid_sources[0x33]	7392	1			T8	3		T10	10		T13	3
valid_sources[0x34]	3183	1			T1	2		T8	1		T10	12
valid_sources[0x35]	4189	1			T1	2		T4	1		T8	7
valid_sources[0x36]	3495	1			T1	3		T8	2		T10	16
valid_sources[0x37]	3440	1			T8	1		T10	12		T11	1
valid_sources[0x38]	3379	1			T10	10		T22	5		T25	9
valid_sources[0x39]	3146	1			T8	3		T10	16		T22	5
valid_sources[0x3a]	3443	1			T1	5		T8	3		T10	10
valid_sources[0x3b]	4127	1			T1	1		T8	4		T10	12
valid_sources[0x3c]	3349	1			T1	2		T8	2		T10	5
valid_sources[0x3d]	5447	1			T1	2		T10	8		T11	2
valid_sources[0x3e]	3387	1			T4	1		T9	1		T10	9
valid_sources[0x3f]	3406	1			T8	1		T10	1		T13	41
valid_sources[0x40]	3444	1			T1	1		T10	6		T13	3
valid_sources[0x41]	3490	1			T1	1		T8	2		T10	6
valid_sources[0x42]	5260	1			T1	1		T10	3		T13	11
valid_sources[0x43]	4217	1			T1	3		T8	2		T10	12
valid_sources[0x44]	3682	1			T8	2		T10	20		T13	20
valid_sources[0x45]	4298	1			T1	2		T8	1		T10	6
valid_sources[0x46]	3840	1			T1	1		T8	2		T10	3
valid_sources[0x47]	6886	1			T1	4		T10	17		T13	22
valid_sources[0x48]	4142	1			T1	1		T10	4		T13	73
valid_sources[0x49]	3867	1			T1	3		T8	1		T10	2
valid_sources[0x4a]	4188	1			T1	1		T8	1		T10	11
valid_sources[0x4b]	3009	1			T1	1		T8	2		T10	2
valid_sources[0x4c]	3969	1			T8	1		T10	6		T12	10
valid_sources[0x4d]	3492	1			T8	1		T10	5		T12	6
valid_sources[0x4e]	3107	1			T1	1		T8	5		T10	17
valid_sources[0x4f]	4800	1			T1	1		T8	2		T10	9
valid_sources[0x50]	4151	1			T1	1		T4	1		T10	7
valid_sources[0x51]	3532	1			T10	13		T22	10		T25	12
valid_sources[0x52]	3403	1			T8	1		T10	4		T13	19
valid_sources[0x53]	4431	1			T1	1		T4	1		T10	8
valid_sources[0x54]	3549	1			T8	1		T10	8		T11	1
valid_sources[0x55]	3906	1			T1	2		T4	8		T10	3
valid_sources[0x56]	4014	1			T10	7		T13	4		T22	10
valid_sources[0x57]	3950	1			T1	2		T8	1		T10	13
valid_sources[0x58]	3666	1			T1	5		T8	2		T10	7
valid_sources[0x59]	4368	1			T1	1		T4	2		T10	2
valid_sources[0x5a]	3836	1			T10	16		T11	1		T22	10
valid_sources[0x5b]	3988	1			T1	1		T4	1		T6	4
valid_sources[0x5c]	3284	1			T1	2		T8	3		T10	11
valid_sources[0x5d]	4058	1			T8	1		T10	9		T13	26
valid_sources[0x5e]	4110	1			T8	1		T10	5		T11	1
valid_sources[0x5f]	4201	1			T1	2		T8	1		T10	6
valid_sources[0x60]	3307	1			T1	1		T10	10		T22	12
valid_sources[0x61]	4420	1			T1	2		T8	3		T10	10
valid_sources[0x62]	3230	1			T10	8		T12	2		T13	7
valid_sources[0x63]	3986	1			T1	3		T8	1		T10	7
valid_sources[0x64]	3081	1			T1	2		T4	1		T10	5
valid_sources[0x65]	3624	1			T8	1		T10	7		T11	2
valid_sources[0x66]	3250	1			T1	1		T8	1		T10	17
valid_sources[0x67]	3880	1			T4	4		T8	4		T10	3
valid_sources[0x68]	3447	1			T1	1		T4	2		T8	1
valid_sources[0x69]	3344	1			T10	3		T22	15		T25	6
valid_sources[0x6a]	4749	1			T1	2		T4	1		T8	1
valid_sources[0x6b]	3489	1			T1	1		T8	2		T10	9
valid_sources[0x6c]	4734	1			T1	1		T10	16		T12	2
valid_sources[0x6d]	4029	1			T1	1		T8	1		T10	7
valid_sources[0x6e]	4452	1			T1	2		T8	2		T10	8
valid_sources[0x6f]	7120	1			T1	1		T10	9		T11	1
valid_sources[0x70]	4384	1			T8	2		T10	12		T11	1
valid_sources[0x71]	4687	1			T1	1		T8	2		T10	9
valid_sources[0x72]	3429	1			T4	1		T8	4		T10	9
valid_sources[0x73]	9032	1			T1	1		T10	2		T22	15
valid_sources[0x74]	4413	1			T1	1		T8	1		T10	10
valid_sources[0x75]	4078	1			T1	2		T10	7		T11	2
valid_sources[0x76]	3761	1			T1	3		T10	8		T11	1
valid_sources[0x77]	3590	1			T8	2		T10	6		T11	1
valid_sources[0x78]	4669	1			T1	3		T4	1		T8	2
valid_sources[0x79]	4316	1			T4	3		T8	2		T10	12
valid_sources[0x7a]	3401	1			T1	3		T4	2		T8	1
valid_sources[0x7b]	4359	1			T1	2		T10	9		T11	1
valid_sources[0x7c]	4028	1			T4	1		T8	1		T10	6
valid_sources[0x7d]	4163	1			T1	1		T8	1		T10	4
valid_sources[0x7e]	3169	1			T1	3		T8	3		T10	8
valid_sources[0x7f]	3340	1			T1	2		T8	2		T10	10
valid_sources[0x80]	3462	1			T10	7		T13	62		T22	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

259384

1

T1

81

T3

38

T4

24

values[0x0]

all_enables

biggest_size

84270

1

T1

34

T3

17

T4

13

values[0x1]

all_enables

biggest_size

44662

1

T1

15

T3

13

T4

3