Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

99                        logic scanmode;
100        1/1            always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i);
           Tests:       T1 T3 T8 
101                     
102                       logic scan_reset_n;
103        1/1            always_comb scan_reset_n = !scanmode || scan_rst_ni;
           Tests:       T1 T3 T8 
104                     
105                       // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored.
106                       logic aon_por_n_i;
107        1/1            always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode;
           Tests:       T1 T2 T3 
108                     
109                       sequence PorStable_S;
110                         $rose(
111                             aon_por_n_i
112                         ) ##1 aon_por_n_i [* PorCycles.rise.min];
113                       endsequence
114                     
115                       // The reset stretching assertion.
116                       `ASSERT(StablePorToAonRise_A,
117                               PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)]
118                               !aon_por_n_i || resets_o.rst_por_aon_n[0],
119                               clk_aon_i, disable_sva)
120                     
121                       // The scan reset to Por.
122                       `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i,
123                               disable_sva)
124                     
125                       logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n;
126                       always_comb
127        1/1              effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}};
           Tests:       T1 T2 T3 
128                     
129                       // The AON reset triggers the various POR reset for the different clock domains through
130                       // synchronizers.
131                       // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0
132                       // cascading is checked here.
133                       `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
134                                         resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i)
135                     
136                       // The internal reset is triggered by one of synchronized por.
137                       logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
138        1/1            always_comb por_rst_n = resets_o.rst_por_aon_n;
           Tests:       T1 T2 T3 
139                     
140                       logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n;
141        1/1            always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req;
           Tests:       T1 T2 T3 
142                     
143                       logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n;
144        1/1            always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T8,T10,T22
1	0	Covered	T1,T10,T22

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56974467	8785	0	0
CascadeEffAonToRstPorAboveRise_A	56974467	8785	0	0
CascadeEffAonToRstPorIoAboveFall_A	54693817	8785	0	0
CascadeEffAonToRstPorIoAboveRise_A	54693817	8785	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27347731	8785	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27347731	8785	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13673739	8785	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13673739	8785	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27347883	8785	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27347883	8785	0	0
CascadeLcToLcAboveFall_A	56974467	22725	0	0
CascadeLcToLcAboveRise_A	56974467	22725	0	0
CascadeLcToLcAonAboveFall_A	1727857	22725	0	0
CascadeLcToLcAonAboveRise_A	1727857	22725	0	0
CascadeLcToLcShadowedAboveFall_A	56974467	22725	0	0
CascadeLcToLcShadowedAboveRise_A	56974467	22725	0	0
CascadePorToAonAboveFall_A	1727857	6926	0	0
CascadeSysToSysAboveFall_A	56974467	22725	0	0
CascadeSysToSysAboveRise_A	56974467	22725	0	0
ScanRstToAonRise_A	1727857	218	0	0
StablePorToAonRise_A	1727857	8785	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12144661	22725	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12144661	22725	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12144661	22725	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12144661	22725	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13673739	22725	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13673739	22725	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12144661	22725	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12144661	22725	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12144661	22725	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12144661	22725	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	8785	0	0
T1	11666	2	0	0
T2	20204	2	0	0
T3	10908	2	0	0
T4	13784	1	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	2	0	0
T9	17514	2	0	0
T10	134647	17	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	8785	0	0
T1	11666	2	0	0
T2	20204	2	0	0
T3	10908	2	0	0
T4	13784	1	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	2	0	0
T9	17514	2	0	0
T10	134647	17	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	8785	0	0
T1	11199	2	0	0
T2	19395	2	0	0
T3	10475	2	0	0
T4	13232	1	0	0
T5	28850	10	0	0
T6	6482	1	0	0
T7	49221	1	0	0
T8	12301	2	0	0
T9	16813	2	0	0
T10	129249	17	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	8785	0	0
T1	11199	2	0	0
T2	19395	2	0	0
T3	10475	2	0	0
T4	13232	1	0	0
T5	28850	10	0	0
T6	6482	1	0	0
T7	49221	1	0	0
T8	12301	2	0	0
T9	16813	2	0	0
T10	129249	17	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	8785	0	0
T1	5602	2	0	0
T2	9697	2	0	0
T3	5235	2	0	0
T4	6615	1	0	0
T5	14424	10	0	0
T6	3241	1	0	0
T7	24610	1	0	0
T8	6153	2	0	0
T9	8406	2	0	0
T10	64632	17	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	8785	0	0
T1	5602	2	0	0
T2	9697	2	0	0
T3	5235	2	0	0
T4	6615	1	0	0
T5	14424	10	0	0
T6	3241	1	0	0
T7	24610	1	0	0
T8	6153	2	0	0
T9	8406	2	0	0
T10	64632	17	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	8785	0	0
T1	2798	2	0	0
T2	4848	2	0	0
T3	2618	2	0	0
T4	3306	1	0	0
T5	7214	10	0	0
T6	1620	1	0	0
T7	12304	1	0	0
T8	3074	2	0	0
T9	4203	2	0	0
T10	32319	17	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	8785	0	0
T1	2798	2	0	0
T2	4848	2	0	0
T3	2618	2	0	0
T4	3306	1	0	0
T5	7214	10	0	0
T6	1620	1	0	0
T7	12304	1	0	0
T8	3074	2	0	0
T9	4203	2	0	0
T10	32319	17	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	8785	0	0
T1	5598	2	0	0
T2	9697	2	0	0
T3	5234	2	0	0
T4	6616	1	0	0
T5	14422	10	0	0
T6	3241	1	0	0
T7	24611	1	0	0
T8	6150	2	0	0
T9	8406	2	0	0
T10	64632	17	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	8785	0	0
T1	5598	2	0	0
T2	9697	2	0	0
T3	5234	2	0	0
T4	6616	1	0	0
T5	14422	10	0	0
T6	3241	1	0	0
T7	24611	1	0	0
T8	6150	2	0	0
T9	8406	2	0	0
T10	64632	17	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	22725	0	0
T1	348	6	0	0
T2	604	2	0	0
T3	326	6	0	0
T4	412	7	0	0
T5	904	10	0	0
T6	202	1	0	0
T7	1537	1	0	0
T8	383	6	0	0
T9	524	2	0	0
T10	4101	45	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	22725	0	0
T1	348	6	0	0
T2	604	2	0	0
T3	326	6	0	0
T4	412	7	0	0
T5	904	10	0	0
T6	202	1	0	0
T7	1537	1	0	0
T8	383	6	0	0
T9	524	2	0	0
T10	4101	45	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	6926	0	0
T1	348	1	0	0
T2	604	17	0	0
T3	326	1	0	0
T4	412	1	0	0
T5	904	10	0	0
T6	202	1	0	0
T7	1537	1	0	0
T8	383	1	0	0
T9	524	17	0	0
T10	4101	5	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	22725	0	0
T1	11666	6	0	0
T2	20204	2	0	0
T3	10908	6	0	0
T4	13784	7	0	0
T5	30060	10	0	0
T6	6752	1	0	0
T7	51273	1	0	0
T8	12817	6	0	0
T9	17514	2	0	0
T10	134647	45	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	218	0	0
T10	4101	1	0	0
T11	262	0	0	0
T12	505	0	0	0
T13	5870	0	0	0
T14	488	0	0	0
T22	4736	1	0	0
T23	349	0	0	0
T24	908	0	0	0
T34	214	0	0	0
T54	0	1	0	0
T56	838	0	0	0
T70	0	1	0	0
T74	0	1	0	0
T76	0	7	0	0
T89	0	1	0	0
T91	0	5	0	0
T112	0	1	0	0
T132	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	8785	0	0
T1	348	2	0	0
T2	604	2	0	0
T3	326	2	0	0
T4	412	1	0	0
T5	904	10	0	0
T6	202	1	0	0
T7	1537	1	0	0
T8	383	2	0	0
T9	524	2	0	0
T10	4101	17	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	22725	0	0
T1	2798	6	0	0
T2	4848	2	0	0
T3	2618	6	0	0
T4	3306	7	0	0
T5	7214	10	0	0
T6	1620	1	0	0
T7	12304	1	0	0
T8	3074	6	0	0
T9	4203	2	0	0
T10	32319	45	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	22725	0	0
T1	2798	6	0	0
T2	4848	2	0	0
T3	2618	6	0	0
T4	3306	7	0	0
T5	7214	10	0	0
T6	1620	1	0	0
T7	12304	1	0	0
T8	3074	6	0	0
T9	4203	2	0	0
T10	32319	45	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12144661	22725	0	0
T1	2462	6	0	0
T2	4757	2	0	0
T3	2280	6	0	0
T4	2852	7	0	0
T5	7012	10	0	0
T6	1577	1	0	0
T7	12261	1	0	0
T8	2737	6	0	0
T9	4040	2	0	0
T10	28770	45	0	0