Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T56,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T56,T36
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T56
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T56
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13673739	14877	0	0
gen_assertions[0].RstEnOn_A	13673739	1118	0	0
gen_assertions[0].RstNOff_A	13673739	14877	0	0
gen_assertions[0].RstNOn_A	13673739	1118	0	0
gen_assertions[1].RstEnOff_A	54693817	13522	0	0
gen_assertions[1].RstEnOn_A	54693817	1072	0	0
gen_assertions[1].RstNOff_A	54693817	13522	0	0
gen_assertions[1].RstNOn_A	54693817	1072	0	0
gen_assertions[2].RstEnOff_A	27347731	13548	0	0
gen_assertions[2].RstEnOn_A	27347731	1045	0	0
gen_assertions[2].RstNOff_A	27347731	13548	0	0
gen_assertions[2].RstNOn_A	27347731	1045	0	0
gen_assertions[3].RstEnOff_A	27347883	13606	0	0
gen_assertions[3].RstEnOn_A	27347883	1101	0	0
gen_assertions[3].RstNOff_A	27347883	13606	0	0
gen_assertions[3].RstNOn_A	27347883	1101	0	0
gen_assertions[4].RstEnOff_A	1727857	22426	0	0
gen_assertions[4].RstEnOn_A	1727857	1132	0	0
gen_assertions[4].RstNOff_A	1727857	22426	0	0
gen_assertions[4].RstNOn_A	1727857	1132	0	0
gen_assertions[5].RstEnOff_A	13673739	15136	0	0
gen_assertions[5].RstEnOn_A	13673739	1243	0	0
gen_assertions[5].RstNOff_A	13673739	15136	0	0
gen_assertions[5].RstNOn_A	13673739	1243	0	0
gen_assertions[6].RstEnOff_A	13673739	15148	0	0
gen_assertions[6].RstEnOn_A	13673739	1252	0	0
gen_assertions[6].RstNOff_A	13673739	15148	0	0
gen_assertions[6].RstNOn_A	13673739	1252	0	0
gen_assertions[7].RstEnOff_A	13673739	15166	0	0
gen_assertions[7].RstEnOn_A	13673739	1269	0	0
gen_assertions[7].RstNOff_A	13673739	15166	0	0
gen_assertions[7].RstNOn_A	13673739	1269	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	14877	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	6	0	0
T8	3074	5	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	1	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1118	0	0
T7	12304	6	0	0
T8	3074	1	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	5	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T53	0	7	0	0
T56	6718	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	14877	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	6	0	0
T8	3074	5	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	1	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1118	0	0
T7	12304	6	0	0
T8	3074	1	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	5	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T53	0	7	0	0
T56	6718	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	13522	0	0
T1	11199	4	0	0
T2	19395	0	0	0
T3	10475	3	0	0
T4	13232	6	0	0
T5	28850	0	0	0
T6	6482	0	0	0
T7	49221	8	0	0
T8	12301	3	0	0
T9	16813	0	0	0
T10	129249	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	1072	0	0
T7	49221	8	0	0
T8	12301	1	0	0
T9	16813	0	0	0
T10	129249	0	0	0
T11	8449	3	0	0
T12	16222	0	0	0
T13	187401	0	0	0
T22	149564	0	0	0
T24	28978	0	0	0
T35	0	4	0	0
T36	0	3	0	0
T53	0	8	0	0
T56	26876	3	0	0
T70	0	9	0	0
T71	0	1	0	0
T72	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	13522	0	0
T1	11199	4	0	0
T2	19395	0	0	0
T3	10475	3	0	0
T4	13232	6	0	0
T5	28850	0	0	0
T6	6482	0	0	0
T7	49221	8	0	0
T8	12301	3	0	0
T9	16813	0	0	0
T10	129249	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	1072	0	0
T7	49221	8	0	0
T8	12301	1	0	0
T9	16813	0	0	0
T10	129249	0	0	0
T11	8449	3	0	0
T12	16222	0	0	0
T13	187401	0	0	0
T22	149564	0	0	0
T24	28978	0	0	0
T35	0	4	0	0
T36	0	3	0	0
T53	0	8	0	0
T56	26876	3	0	0
T70	0	9	0	0
T71	0	1	0	0
T72	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	13548	0	0
T1	5602	4	0	0
T2	9697	0	0	0
T3	5235	3	0	0
T4	6615	6	0	0
T5	14424	0	0	0
T6	3241	0	0	0
T7	24610	7	0	0
T8	6153	2	0	0
T9	8406	0	0	0
T10	64632	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	1045	0	0
T7	24610	7	0	0
T8	6153	0	0	0
T9	8406	0	0	0
T10	64632	0	0	0
T11	4224	1	0	0
T12	8112	0	0	0
T13	93674	0	0	0
T22	74772	0	0	0
T24	14486	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T53	0	12	0	0
T56	13438	4	0	0
T70	0	10	0	0
T71	0	4	0	0
T72	0	3	0	0
T73	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	13548	0	0
T1	5602	4	0	0
T2	9697	0	0	0
T3	5235	3	0	0
T4	6615	6	0	0
T5	14424	0	0	0
T6	3241	0	0	0
T7	24610	7	0	0
T8	6153	2	0	0
T9	8406	0	0	0
T10	64632	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	1045	0	0
T7	24610	7	0	0
T8	6153	0	0	0
T9	8406	0	0	0
T10	64632	0	0	0
T11	4224	1	0	0
T12	8112	0	0	0
T13	93674	0	0	0
T22	74772	0	0	0
T24	14486	0	0	0
T35	0	1	0	0
T36	0	4	0	0
T53	0	12	0	0
T56	13438	4	0	0
T70	0	10	0	0
T71	0	4	0	0
T72	0	3	0	0
T73	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	13606	0	0
T1	5598	4	0	0
T2	9697	0	0	0
T3	5234	3	0	0
T4	6616	6	0	0
T5	14422	0	0	0
T6	3241	0	0	0
T7	24611	10	0	0
T8	6150	2	0	0
T9	8406	0	0	0
T10	64632	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	6	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	1101	0	0
T7	24611	10	0	0
T8	6150	0	0	0
T9	8406	0	0	0
T10	64632	0	0	0
T11	4224	0	0	0
T12	8111	0	0	0
T13	93688	0	0	0
T22	74773	0	0	0
T24	14483	0	0	0
T36	0	7	0	0
T53	0	11	0	0
T56	13438	6	0	0
T70	0	8	0	0
T71	0	5	0	0
T72	0	3	0	0
T74	0	15	0	0
T75	0	5	0	0
T76	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	13606	0	0
T1	5598	4	0	0
T2	9697	0	0	0
T3	5234	3	0	0
T4	6616	6	0	0
T5	14422	0	0	0
T6	3241	0	0	0
T7	24611	10	0	0
T8	6150	2	0	0
T9	8406	0	0	0
T10	64632	26	0	0
T11	0	6	0	0
T12	0	4	0	0
T13	0	74	0	0
T56	0	6	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	1101	0	0
T7	24611	10	0	0
T8	6150	0	0	0
T9	8406	0	0	0
T10	64632	0	0	0
T11	4224	0	0	0
T12	8111	0	0	0
T13	93688	0	0	0
T22	74773	0	0	0
T24	14483	0	0	0
T36	0	7	0	0
T53	0	11	0	0
T56	13438	6	0	0
T70	0	8	0	0
T71	0	5	0	0
T72	0	3	0	0
T74	0	15	0	0
T75	0	5	0	0
T76	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	22426	0	0
T1	348	6	0	0
T2	604	2	0	0
T3	326	5	0	0
T4	412	7	0	0
T5	904	3	0	0
T6	202	1	0	0
T7	1537	9	0	0
T8	383	6	0	0
T9	524	2	0	0
T10	4101	45	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	1132	0	0
T7	1537	8	0	0
T8	383	1	0	0
T9	524	0	0	0
T10	4101	0	0	0
T11	262	0	0	0
T12	505	0	0	0
T13	5870	0	0	0
T22	4736	0	0	0
T24	908	0	0	0
T36	0	7	0	0
T53	0	11	0	0
T56	838	5	0	0
T70	0	10	0	0
T71	0	6	0	0
T72	0	5	0	0
T73	0	1	0	0
T74	0	16	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	22426	0	0
T1	348	6	0	0
T2	604	2	0	0
T3	326	5	0	0
T4	412	7	0	0
T5	904	3	0	0
T6	202	1	0	0
T7	1537	9	0	0
T8	383	6	0	0
T9	524	2	0	0
T10	4101	45	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	1132	0	0
T7	1537	8	0	0
T8	383	1	0	0
T9	524	0	0	0
T10	4101	0	0	0
T11	262	0	0	0
T12	505	0	0	0
T13	5870	0	0	0
T22	4736	0	0	0
T24	908	0	0	0
T36	0	7	0	0
T53	0	11	0	0
T56	838	5	0	0
T70	0	10	0	0
T71	0	6	0	0
T72	0	5	0	0
T73	0	1	0	0
T74	0	16	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15136	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	4	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1243	0	0
T7	12304	12	0	0
T8	3074	0	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	0	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T36	0	6	0	0
T53	0	10	0	0
T56	6718	7	0	0
T70	0	10	0	0
T71	0	5	0	0
T72	0	6	0	0
T74	0	15	0	0
T75	0	9	0	0
T76	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15136	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	4	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1243	0	0
T7	12304	12	0	0
T8	3074	0	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	0	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T36	0	6	0	0
T53	0	10	0	0
T56	6718	7	0	0
T70	0	10	0	0
T71	0	5	0	0
T72	0	6	0	0
T74	0	15	0	0
T75	0	9	0	0
T76	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15148	0	0
T1	2798	5	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	4	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1252	0	0
T1	2798	1	0	0
T2	4848	0	0	0
T3	2618	0	0	0
T4	3306	0	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	0	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T36	0	9	0	0
T53	0	13	0	0
T56	0	7	0	0
T70	0	11	0	0
T71	0	8	0	0
T72	0	7	0	0
T74	0	18	0	0
T75	0	9	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15148	0	0
T1	2798	5	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	4	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1252	0	0
T1	2798	1	0	0
T2	4848	0	0	0
T3	2618	0	0	0
T4	3306	0	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	0	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T36	0	9	0	0
T53	0	13	0	0
T56	0	7	0	0
T70	0	11	0	0
T71	0	8	0	0
T72	0	7	0	0
T74	0	18	0	0
T75	0	9	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15166	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	5	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	9	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1269	0	0
T7	12304	12	0	0
T8	3074	1	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	0	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T36	0	10	0	0
T53	0	10	0	0
T56	6718	9	0	0
T68	0	1	0	0
T70	0	10	0	0
T71	0	8	0	0
T72	0	7	0	0
T74	0	17	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	15166	0	0
T1	2798	4	0	0
T2	4848	0	0	0
T3	2618	4	0	0
T4	3306	6	0	0
T5	7214	0	0	0
T6	1620	0	0	0
T7	12304	12	0	0
T8	3074	5	0	0
T9	4203	0	0	0
T10	32319	28	0	0
T11	0	7	0	0
T12	0	4	0	0
T13	0	78	0	0
T56	0	9	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	1269	0	0
T7	12304	12	0	0
T8	3074	1	0	0
T9	4203	0	0	0
T10	32319	0	0	0
T11	2111	0	0	0
T12	4056	0	0	0
T13	46853	0	0	0
T22	37395	0	0	0
T24	7246	0	0	0
T36	0	10	0	0
T53	0	10	0	0
T56	6718	9	0	0
T68	0	1	0	0
T70	0	10	0	0
T71	0	8	0	0
T72	0	7	0	0
T74	0	17	0	0