Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	923053344	516982873	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	923053344	516982873	0	0
T1	188964	106925	0	0
T2	327276	62318	0	0
T3	176708	94333	0	0
T4	223264	154112	0	0
T5	486900	46051	0	0
T6	109376	65370	0	0
T7	830594	768000	0	0
T8	207590	124627	0	0
T9	283710	60195	0	0
T10	2181528	1521139	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	35569849	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	35569849	0	0
T1	11666	7337	0	0
T2	20204	4457	0	0
T3	10908	6567	0	0
T4	13784	11080	0	0
T5	30060	3262	0	0
T6	6752	4076	0	0
T7	51273	48589	0	0
T8	12817	8612	0	0
T9	17514	3831	0	0
T10	134647	101532	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54693817	34146034	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	34146034	0	0
T1	11199	7045	0	0
T2	19395	4279	0	0
T3	10475	6307	0	0
T4	13232	10636	0	0
T5	28850	3132	0	0
T6	6482	3912	0	0
T7	49221	46644	0	0
T8	12301	8264	0	0
T9	16813	3677	0	0
T10	129249	97451	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347731	17069275	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	17069275	0	0
T1	5602	3524	0	0
T2	9697	2138	0	0
T3	5235	3151	0	0
T4	6615	5318	0	0
T5	14424	1561	0	0
T6	3241	1956	0	0
T7	24610	23323	0	0
T8	6153	4134	0	0
T9	8406	1838	0	0
T10	64632	48720	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	8531971	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	8531971	0	0
T1	2798	1760	0	0
T2	4848	1069	0	0
T3	2618	1576	0	0
T4	3306	2658	0	0
T5	7214	776	0	0
T6	1620	977	0	0
T7	12304	11661	0	0
T8	3074	2064	0	0
T9	4203	918	0	0
T10	32319	24367	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347883	17069306	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	17069306	0	0
T1	5598	3520	0	0
T2	9697	2138	0	0
T3	5234	3151	0	0
T4	6616	5318	0	0
T5	14422	1561	0	0
T6	3241	1956	0	0
T7	24611	23323	0	0
T8	6150	4132	0	0
T9	8406	1838	0	0
T10	64632	48728	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	31673045	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	31673045	0	0
T1	11666	6541	0	0
T2	20204	4448	0	0
T3	10908	5762	0	0
T4	13784	9225	0	0
T5	30060	3152	0	0
T6	6752	4069	0	0
T7	51273	48583	0	0
T8	12817	7600	0	0
T9	17514	3819	0	0
T10	134647	92993	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	30944044	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	30944044	0	0
T1	11666	6372	0	0
T2	20204	3281	0	0
T3	10908	5597	0	0
T4	13784	9109	0	0
T5	30060	2485	0	0
T6	6752	4003	0	0
T7	51273	48517	0	0
T8	12817	7434	0	0
T9	17514	3618	0	0
T10	134647	91625	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	31673188	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	31673188	0	0
T1	11666	6541	0	0
T2	20204	4448	0	0
T3	10908	5762	0	0
T4	13784	9225	0	0
T5	30060	3153	0	0
T6	6752	4069	0	0
T7	51273	48583	0	0
T8	12817	7600	0	0
T9	17514	3819	0	0
T10	134647	92993	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	30944022	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	30944022	0	0
T1	11666	6372	0	0
T2	20204	3281	0	0
T3	10908	5597	0	0
T4	13784	9109	0	0
T5	30060	2486	0	0
T6	6752	4003	0	0
T7	51273	48517	0	0
T8	12817	7434	0	0
T9	17514	3618	0	0
T10	134647	91625	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1727857	942057	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	942057	0	0
T1	348	191	0	0
T2	604	131	0	0
T3	326	166	0	0
T4	412	271	0	0
T5	904	82	0	0
T6	202	121	0	0
T7	1537	1456	0	0
T8	383	223	0	0
T9	524	112	0	0
T10	4101	2799	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54693817	30406141	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	30406141	0	0
T1	11199	6279	0	0
T2	19395	4269	0	0
T3	10475	5533	0	0
T4	13232	8856	0	0
T5	28850	3066	0	0
T6	6482	3907	0	0
T7	49221	46639	0	0
T8	12301	7294	0	0
T9	16813	3665	0	0
T10	129249	89256	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54693817	29706157	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	29706157	0	0
T1	11199	6119	0	0
T2	19395	3149	0	0
T3	10475	5373	0	0
T4	13232	8744	0	0
T5	28850	2426	0	0
T6	6482	3843	0	0
T7	49221	46575	0	0
T8	12301	7134	0	0
T9	16813	3473	0	0
T10	129249	87944	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347731	15193018	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	15193018	0	0
T1	5602	3140	0	0
T2	9697	2134	0	0
T3	5235	2761	0	0
T4	6615	4425	0	0
T5	14424	1531	0	0
T6	3241	1953	0	0
T7	24610	23320	0	0
T8	6153	3646	0	0
T9	8406	1832	0	0
T10	64632	44607	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347731	14842714	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	14842714	0	0
T1	5602	3060	0	0
T2	9697	1574	0	0
T3	5235	2681	0	0
T4	6615	4369	0	0
T5	14424	1211	0	0
T6	3241	1921	0	0
T7	24610	23288	0	0
T8	6153	3566	0	0
T9	8406	1736	0	0
T10	64632	43951	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7568075	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7568075	0	0
T1	2798	1560	0	0
T2	4848	1065	0	0
T3	2618	1375	0	0
T4	3306	2202	0	0
T5	7214	746	0	0
T6	1620	975	0	0
T7	12304	11659	0	0
T8	3074	1814	0	0
T9	4203	914	0	0
T10	32319	22257	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7393027	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7393027	0	0
T1	2798	1520	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2174	0	0
T5	7214	586	0	0
T6	1620	959	0	0
T7	12304	11643	0	0
T8	3074	1774	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7568075	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7568075	0	0
T1	2798	1560	0	0
T2	4848	1065	0	0
T3	2618	1375	0	0
T4	3306	2202	0	0
T5	7214	746	0	0
T6	1620	975	0	0
T7	12304	11659	0	0
T8	3074	1814	0	0
T9	4203	914	0	0
T10	32319	22257	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7393027	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7393027	0	0
T1	2798	1520	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2174	0	0
T5	7214	586	0	0
T6	1620	959	0	0
T7	12304	11643	0	0
T8	3074	1774	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347883	15192796	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	15192796	0	0
T1	5598	3136	0	0
T2	9697	2134	0	0
T3	5234	2761	0	0
T4	6616	4425	0	0
T5	14422	1531	0	0
T6	3241	1953	0	0
T7	24611	23320	0	0
T8	6150	3644	0	0
T9	8406	1832	0	0
T10	64632	44616	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347883	14842502	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	14842502	0	0
T1	5598	3056	0	0
T2	9697	1574	0	0
T3	5234	2681	0	0
T4	6616	4369	0	0
T5	14422	1211	0	0
T6	3241	1921	0	0
T7	24611	23288	0	0
T8	6150	3564	0	0
T9	8406	1736	0	0
T10	64632	43960	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	56974467	30628450	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56974467	30628450	0	0
T1	11666	6306	0	0
T2	20204	3281	0	0
T3	10908	5505	0	0
T4	13784	8951	0	0
T5	30060	2527	0	0
T6	6752	4003	0	0
T7	51273	48517	0	0
T8	12817	7383	0	0
T9	17514	3618	0	0
T10	134647	90973	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7491897	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7491897	0	0
T1	2798	1544	0	0
T2	4848	1065	0	0
T3	2618	1353	0	0
T4	3306	2164	0	0
T5	7214	756	0	0
T6	1620	975	0	0
T7	12304	11659	0	0
T8	3074	1802	0	0
T9	4203	914	0	0
T10	32319	22101	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7236808	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7236808	0	0
T1	2798	1520	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2172	0	0
T5	7214	596	0	0
T6	1620	959	0	0
T7	12304	10466	0	0
T8	3074	1742	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54693817	29098571	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54693817	29098571	0	0
T1	11199	6119	0	0
T2	19395	3149	0	0
T3	10475	5373	0	0
T4	13232	8744	0	0
T5	28850	2426	0	0
T6	6482	3843	0	0
T7	49221	40774	0	0
T8	12301	7014	0	0
T9	16813	3473	0	0
T10	129249	87944	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347731	14537081	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347731	14537081	0	0
T1	5602	3060	0	0
T2	9697	1574	0	0
T3	5235	2681	0	0
T4	6615	4369	0	0
T5	14424	1211	0	0
T6	3241	1921	0	0
T7	24610	20828	0	0
T8	6153	3566	0	0
T9	8406	1736	0	0
T10	64632	43951	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	27347883	14529439	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27347883	14529439	0	0
T1	5598	3056	0	0
T2	9697	1574	0	0
T3	5234	2681	0	0
T4	6616	4369	0	0
T5	14422	1211	0	0
T6	3241	1921	0	0
T7	24611	19886	0	0
T8	6150	3564	0	0
T9	8406	1736	0	0
T10	64632	43960	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1727857	902284	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	902284	0	0
T1	348	187	0	0
T2	604	96	0	0
T3	326	162	0	0
T4	412	268	0	0
T5	904	62	0	0
T6	202	119	0	0
T7	1537	1305	0	0
T8	383	215	0	0
T9	524	106	0	0
T10	4101	2757	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7235362	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7235362	0	0
T1	2798	1520	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2174	0	0
T5	7214	596	0	0
T6	1620	959	0	0
T7	12304	9697	0	0
T8	3074	1774	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7241190	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7241190	0	0
T1	2798	1500	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2174	0	0
T5	7214	596	0	0
T6	1620	959	0	0
T7	12304	9806	0	0
T8	3074	1774	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13673739	7255048	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13673739	7255048	0	0
T1	2798	1520	0	0
T2	4848	785	0	0
T3	2618	1335	0	0
T4	3306	2174	0	0
T5	7214	596	0	0
T6	1620	959	0	0
T7	12304	9918	0	0
T8	3074	1756	0	0
T9	4203	866	0	0
T10	32319	21929	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1727857	1088408	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	1088408	0	0
T1	348	222	0	0
T2	604	135	0	0
T3	326	198	0	0
T4	412	333	0	0
T5	904	102	0	0
T6	202	123	0	0
T7	1537	1458	0	0
T8	383	260	0	0
T9	524	116	0	0
T10	4101	3116	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

33                        logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34         unreachable    assign mubi = MuBi4Width'(mubi_i);
35                      
36                        // first generation block decides whether a flop should be present
37                        if (AsyncOn) begin : gen_flops
38                          prim_flop #(
39                            .Width(MuBi4Width),
40                            .ResetValue(MuBi4Width'(ResetValue))
41                          ) u_prim_flop (
42                            .clk_i,
43                            .rst_ni,
44                            .d_i   ( mubi     ),
45                            .q_o   ( mubi_int )
46                          );
47                        end else begin : gen_no_flops
48                          assign mubi_int = mubi;
49                      
50                          // This unused companion logic helps remove lint errors
51                          // for modules where clock and reset are used for assertions only
52                          // This logic will be removed for sythesis since it is unloaded.
53                          mubi4_t unused_logic;
54                          always_ff @(posedge clk_i or negedge rst_ni) begin
55                            if (!rst_ni) begin
56                               unused_logic <= MuBi4False;
57                            end else begin
58                               unused_logic <= mubi_i;
59                            end
60                          end
61                        end
62                      
63                        // second generation block determines output buffer type
64                        // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65                        // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66                        // 3. If not EnSecBuf and AsyncOn -> feed through
67                        if (EnSecBuf) begin : gen_sec_buf
68                          prim_sec_anchor_buf #(
69                            .Width(4)
70                          ) u_prim_sec_buf (
71                            .in_i(mubi_int),
72                            .out_o(mubi_out)
73                          );
74                        end else if (!AsyncOn) begin : gen_prim_buf
75                          prim_buf #(
76                            .Width(4)
77                          ) u_prim_buf (
78                            .in_i(mubi_int),
79                            .out_o(mubi_out)
80                          );
81                        end else begin : gen_feedthru
82         1/1              assign mubi_out = mubi_int;
           Tests:       T1 T2 T3 
83                        end
84                      
85         1/1            assign mubi_o = mubi4_t'(mubi_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1727857	1070012	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1727857	1070012	0	0
T1	348	218	0	0
T2	604	100	0	0
T3	326	194	0	0
T4	412	331	0	0
T5	904	82	0	0
T6	202	121	0	0
T7	1537	1456	0	0
T8	383	256	0	0
T9	524	110	0	0
T10	4101	3082	0	0