Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data

Module Instance : tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_err_code_reg_intg_err

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_err_code_reset_consistency_err

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
50.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_err_code_fsm_err

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

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Module Instances:
tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb

Line Coverage for Instance : tb.dut.u_reg.u_err_code_reg_intg_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0



42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T1 T3 T4 
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg.u_err_code_reset_consistency_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0



42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T5 T13 T24 
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;

Line Coverage for Instance : tb.dut.u_reg.u_err_code_fsm_err.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	1	50.00
CONT_ASSIGN	43	1	1	100.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0



42                        end else if (SwAccess == SwAccessRO) begin : gen_ro
43         1/1              assign wr_en   = de;
           Tests:       T43 T45 T62 
44         0/1     ==>      assign wr_data = d;
45                          // Unused we, wd, q - Prevent lint errors.
46                          logic          unused_we;
47                          logic [DW-1:0] unused_wd;
48                          logic [DW-1:0] unused_q;
49                          //VCS coverage off
50                          // pragma coverage off
51         unreachable      assign unused_we = we;
52         unreachable      assign unused_wd = wd;
53         unreachable      assign unused_q  = q;