Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12889235	6863	0	0
alert_regwen_rd_A	12889235	5295	0	0
cpu_regwen_rd_A	12889235	5465	0	0
sw_rst_ctrl_n_0_rd_A	12889235	11082	0	0
sw_rst_ctrl_n_1_rd_A	12889235	11269	0	0
sw_rst_ctrl_n_2_rd_A	12889235	10652	0	0
sw_rst_ctrl_n_3_rd_A	12889235	11249	0	0
sw_rst_ctrl_n_4_rd_A	12889235	10879	0	0
sw_rst_ctrl_n_5_rd_A	12889235	11101	0	0
sw_rst_ctrl_n_6_rd_A	12889235	11167	0	0
sw_rst_ctrl_n_7_rd_A	12889235	11348	0	0
sw_rst_regwen_0_rd_A	12889235	5835	0	0
sw_rst_regwen_1_rd_A	12889235	5984	0	0
sw_rst_regwen_2_rd_A	12889235	6172	0	0
sw_rst_regwen_3_rd_A	12889235	5958	0	0
sw_rst_regwen_4_rd_A	12889235	5854	0	0
sw_rst_regwen_5_rd_A	12889235	5949	0	0
sw_rst_regwen_6_rd_A	12889235	6129	0	0
sw_rst_regwen_7_rd_A	12889235	6012	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	6863	0	0
T57	7433	237	0	0
T58	17021	2	0	0
T63	3810	114	0	0
T64	8375	242	0	0
T65	10960	1	0	0
T80	4641	18	0	0
T81	11956	436	0	0
T82	2631	6	0	0
T83	7228	231	0	0
T87	10217	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5295	0	0
T10	28770	47	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T14	3815	0	0	0
T22	32504	0	0	0
T23	2510	0	0	0
T24	7040	0	0	0
T34	1632	0	0	0
T54	0	56	0	0
T56	6627	0	0	0
T90	0	68	0	0
T91	0	160	0	0
T100	0	122	0	0
T101	0	45	0	0
T123	0	24	0	0
T124	0	38	0	0
T125	0	71	0	0
T126	0	404	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5465	0	0
T10	28770	30	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T14	3815	0	0	0
T22	32504	0	0	0
T23	2510	0	0	0
T24	7040	0	0	0
T34	1632	0	0	0
T54	0	81	0	0
T56	6627	0	0	0
T90	0	49	0	0
T91	0	193	0	0
T100	0	128	0	0
T101	0	17	0	0
T123	0	26	0	0
T124	0	16	0	0
T125	0	72	0	0
T126	0	426	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11082	0	0
T4	2852	31	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	190	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	36	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	94	0	0
T54	0	75	0	0
T56	6627	0	0	0
T71	0	145	0	0
T72	0	107	0	0
T127	0	19	0	0
T128	0	28	0	0
T129	0	50	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11269	0	0
T4	2852	23	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	215	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	18	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	144	0	0
T54	0	68	0	0
T56	6627	0	0	0
T71	0	148	0	0
T72	0	110	0	0
T127	0	55	0	0
T128	0	29	0	0
T129	0	46	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	10652	0	0
T4	2852	18	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	209	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	37	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	120	0	0
T54	0	63	0	0
T56	6627	0	0	0
T71	0	153	0	0
T72	0	148	0	0
T127	0	46	0	0
T128	0	28	0	0
T129	0	47	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11249	0	0
T4	2852	17	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	198	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	32	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	118	0	0
T54	0	72	0	0
T56	6627	0	0	0
T71	0	135	0	0
T72	0	134	0	0
T127	0	47	0	0
T128	0	28	0	0
T129	0	29	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	10879	0	0
T4	2852	21	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	196	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	42	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	140	0	0
T54	0	105	0	0
T56	6627	0	0	0
T71	0	147	0	0
T72	0	93	0	0
T127	0	38	0	0
T128	0	46	0	0
T129	0	45	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11101	0	0
T4	2852	17	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	204	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	32	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	154	0	0
T54	0	40	0	0
T56	6627	0	0	0
T71	0	117	0	0
T72	0	134	0	0
T127	0	29	0	0
T128	0	18	0	0
T129	0	48	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11167	0	0
T4	2852	13	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	187	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	27	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	145	0	0
T54	0	78	0	0
T56	6627	0	0	0
T71	0	152	0	0
T72	0	130	0	0
T127	0	20	0	0
T128	0	32	0	0
T129	0	50	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	11348	0	0
T4	2852	30	0	0
T5	7012	0	0	0
T6	1577	0	0	0
T7	12261	182	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	51	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T36	0	114	0	0
T54	0	61	0	0
T56	6627	0	0	0
T71	0	157	0	0
T72	0	118	0	0
T127	0	21	0	0
T128	0	35	0	0
T129	0	26	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5835	0	0
T7	12261	38	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	32	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	37	0	0
T54	0	60	0	0
T56	6627	0	0	0
T71	0	27	0	0
T72	0	27	0	0
T90	0	70	0	0
T91	0	162	0	0
T130	0	40	0	0
T131	0	6	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5984	0	0
T7	12261	25	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	26	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	41	0	0
T54	0	70	0	0
T56	6627	0	0	0
T71	0	50	0	0
T72	0	50	0	0
T90	0	36	0	0
T91	0	137	0	0
T130	0	31	0	0
T131	0	7	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	6172	0	0
T7	12261	45	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	24	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	21	0	0
T54	0	59	0	0
T56	6627	0	0	0
T71	0	27	0	0
T72	0	42	0	0
T90	0	56	0	0
T91	0	174	0	0
T130	0	44	0	0
T131	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5958	0	0
T7	12261	34	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	29	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	22	0	0
T54	0	49	0	0
T56	6627	0	0	0
T71	0	36	0	0
T72	0	46	0	0
T90	0	61	0	0
T91	0	220	0	0
T130	0	42	0	0
T131	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5854	0	0
T7	12261	30	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	26	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	34	0	0
T54	0	85	0	0
T56	6627	0	0	0
T71	0	32	0	0
T72	0	27	0	0
T90	0	65	0	0
T91	0	163	0	0
T130	0	25	0	0
T131	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	5949	0	0
T7	12261	15	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	55	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	34	0	0
T54	0	62	0	0
T56	6627	0	0	0
T71	0	28	0	0
T72	0	31	0	0
T90	0	33	0	0
T91	0	184	0	0
T130	0	31	0	0
T131	0	4	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	6129	0	0
T7	12261	29	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	14	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	38	0	0
T54	0	70	0	0
T56	6627	0	0	0
T71	0	38	0	0
T72	0	28	0	0
T90	0	52	0	0
T91	0	179	0	0
T130	0	38	0	0
T131	0	4	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12889235	6012	0	0
T7	12261	39	0	0
T8	2737	0	0	0
T9	4040	0	0	0
T10	28770	39	0	0
T11	1699	0	0	0
T12	3812	0	0	0
T13	43629	0	0	0
T22	32504	0	0	0
T24	7040	0	0	0
T36	0	35	0	0
T54	0	62	0	0
T56	6627	0	0	0
T71	0	22	0	0
T72	0	23	0	0
T90	0	70	0	0
T91	0	164	0	0
T130	0	30	0	0
T131	0	10	0	0