Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
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Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 631991 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 381015 1 T2 26 T4 80 T5 144



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 542266 1 T1 1 T2 29 T3 1
values[0x0] 235265 1 T2 16 T4 66 T5 102
values[0x1] 235475 1 T2 17 T4 47 T5 91



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 530787 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 482219 1 T2 34 T3 1 T4 100



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3069 1 T4 6 T10 1 T22 1
valid_sources[0x01] 3430 1 T2 1 T12 8 T22 1
valid_sources[0x02] 4018 1 T2 1 T4 2 T5 14
valid_sources[0x03] 3684 1 T4 2 T8 1 T12 5
valid_sources[0x04] 3259 1 T10 1 T64 12 T22 1
valid_sources[0x05] 3582 1 T10 9 T22 1 T49 1
valid_sources[0x06] 3612 1 T10 1 T11 1 T12 2
valid_sources[0x07] 3626 1 T10 1 T64 4 T22 1
valid_sources[0x08] 5446 1 T4 9 T10 5 T11 2
valid_sources[0x09] 3073 1 T64 11 T22 2 T89 12
valid_sources[0x0a] 3847 1 T12 6 T22 1 T43 3
valid_sources[0x0b] 5043 1 T2 2 T4 3 T5 26
valid_sources[0x0c] 4304 1 T9 1 T11 5 T22 2
valid_sources[0x0d] 3460 1 T6 24 T9 3 T10 3
valid_sources[0x0e] 3399 1 T8 1 T10 6 T12 4
valid_sources[0x0f] 2668 1 T4 3 T9 2 T10 5
valid_sources[0x10] 3699 1 T12 3 T64 2 T22 2
valid_sources[0x11] 3326 1 T10 4 T103 4 T43 23
valid_sources[0x12] 3989 1 T22 2 T48 1 T49 4
valid_sources[0x13] 3585 1 T2 1 T4 4 T9 7
valid_sources[0x14] 3826 1 T2 1 T10 1 T22 1
valid_sources[0x15] 3584 1 T4 2 T10 1 T12 4
valid_sources[0x16] 3697 1 T2 2 T9 1 T10 1
valid_sources[0x17] 3755 1 T4 4 T9 10 T12 5
valid_sources[0x18] 4210 1 T9 1 T22 4 T23 168
valid_sources[0x19] 3302 1 T2 1 T11 2 T64 21
valid_sources[0x1a] 4319 1 T4 1 T9 3 T10 7
valid_sources[0x1b] 3391 1 T4 1 T64 4 T22 1
valid_sources[0x1c] 4228 1 T4 1 T10 1 T64 7
valid_sources[0x1d] 3877 1 T10 2 T64 1 T23 423
valid_sources[0x1e] 6370 1 T4 1 T10 2 T64 1
valid_sources[0x1f] 3817 1 T2 6 T10 2 T64 8
valid_sources[0x20] 3925 1 T4 3 T9 4 T64 2
valid_sources[0x21] 3686 1 T4 1 T10 1 T22 1
valid_sources[0x22] 4039 1 T4 1 T9 8 T10 2
valid_sources[0x23] 3481 1 T4 1 T10 1 T64 3
valid_sources[0x24] 4120 1 T5 3 T10 2 T22 3
valid_sources[0x25] 3877 1 T2 1 T8 2 T9 1
valid_sources[0x26] 3484 1 T4 1 T5 40 T12 5
valid_sources[0x27] 3761 1 T4 4 T10 2 T64 2
valid_sources[0x28] 3720 1 T4 1 T10 5 T11 2
valid_sources[0x29] 3937 1 T2 2 T10 3 T64 22
valid_sources[0x2a] 2888 1 T2 1 T9 25 T10 5
valid_sources[0x2b] 5270 1 T4 2 T10 5 T64 8
valid_sources[0x2c] 3270 1 T2 1 T4 2 T11 8
valid_sources[0x2d] 3860 1 T4 2 T10 1 T79 2
valid_sources[0x2e] 3364 1 T4 1 T10 1 T22 1
valid_sources[0x2f] 3137 1 T10 3 T22 1 T43 6
valid_sources[0x30] 3804 1 T4 3 T9 2 T22 1
valid_sources[0x31] 3310 1 T4 2 T22 4 T43 25
valid_sources[0x32] 3872 1 T10 3 T22 3 T103 2
valid_sources[0x33] 6241 1 T10 3 T11 6 T64 3
valid_sources[0x34] 3673 1 T9 4 T10 2 T12 1
valid_sources[0x35] 4404 1 T4 1 T10 2 T22 2
valid_sources[0x36] 3060 1 T4 1 T9 3 T10 1
valid_sources[0x37] 3808 1 T4 4 T9 1 T12 6
valid_sources[0x38] 3516 1 T10 3 T22 1 T23 70
valid_sources[0x39] 2857 1 T4 1 T10 1 T12 11
valid_sources[0x3a] 4410 1 T10 1 T11 5 T22 1
valid_sources[0x3b] 3732 1 T11 1 T12 2 T22 2
valid_sources[0x3c] 4628 1 T2 2 T22 1 T103 6
valid_sources[0x3d] 4067 1 T4 1 T11 4 T64 6
valid_sources[0x3e] 4298 1 T12 5 T64 3 T22 5
valid_sources[0x3f] 3810 1 T22 3 T43 28 T48 1
valid_sources[0x40] 4255 1 T4 2 T10 1 T12 4
valid_sources[0x41] 3741 1 T4 3 T10 2 T64 2
valid_sources[0x42] 3309 1 T10 2 T12 6 T22 1
valid_sources[0x43] 3328 1 T4 1 T9 5 T11 8
valid_sources[0x44] 3768 1 T4 1 T5 3 T9 8
valid_sources[0x45] 3406 1 T9 1 T64 3 T22 1
valid_sources[0x46] 4017 1 T9 2 T10 6 T64 3
valid_sources[0x47] 3414 1 T22 1 T79 10 T43 4
valid_sources[0x48] 4305 1 T2 1 T10 3 T12 1
valid_sources[0x49] 3656 1 T2 4 T9 11 T10 2
valid_sources[0x4a] 3435 1 T4 4 T9 1 T11 7
valid_sources[0x4b] 3563 1 T12 2 T64 12 T14 1
valid_sources[0x4c] 4914 1 T2 1 T4 4 T10 1
valid_sources[0x4d] 2873 1 T4 3 T64 3 T22 1
valid_sources[0x4e] 3886 1 T9 8 T10 2 T11 3
valid_sources[0x4f] 3799 1 T12 10 T22 2 T103 3
valid_sources[0x50] 3160 1 T9 1 T10 4 T22 2
valid_sources[0x51] 3166 1 T12 3 T64 6 T22 1
valid_sources[0x52] 3223 1 T64 1 T22 3 T89 70
valid_sources[0x53] 5260 1 T12 1 T64 3 T22 1
valid_sources[0x54] 4656 1 T4 1 T10 2 T22 1
valid_sources[0x55] 4076 1 T2 1 T4 1 T22 2
valid_sources[0x56] 4106 1 T10 4 T11 6 T22 1
valid_sources[0x57] 4128 1 T10 1 T22 1 T43 38
valid_sources[0x58] 3072 1 T4 3 T22 1 T43 9
valid_sources[0x59] 2805 1 T22 1 T79 3 T59 5
valid_sources[0x5a] 3170 1 T2 1 T64 2 T22 1
valid_sources[0x5b] 4222 1 T10 1 T22 4 T48 1
valid_sources[0x5c] 3871 1 T4 5 T8 1 T10 3
valid_sources[0x5d] 3635 1 T4 2 T64 3 T89 7
valid_sources[0x5e] 3394 1 T2 3 T4 2 T5 6
valid_sources[0x5f] 4831 1 T64 2 T22 1 T43 7
valid_sources[0x60] 4704 1 T4 2 T9 1 T10 3
valid_sources[0x61] 3241 1 T5 32 T65 9 T103 1
valid_sources[0x62] 2964 1 T9 2 T10 5 T12 11
valid_sources[0x63] 4155 1 T12 1 T22 1 T103 4
valid_sources[0x64] 7229 1 T10 3 T22 1 T43 7
valid_sources[0x65] 3038 1 T10 1 T12 4 T64 13
valid_sources[0x66] 5224 1 T12 10 T64 9 T79 2
valid_sources[0x67] 3401 1 T4 1 T64 2 T23 70
valid_sources[0x68] 4029 1 T4 1 T5 14 T10 1
valid_sources[0x69] 3674 1 T4 1 T10 4 T64 10
valid_sources[0x6a] 3571 1 T9 1 T10 3 T22 1
valid_sources[0x6b] 4550 1 T2 1 T10 2 T11 3
valid_sources[0x6c] 3444 1 T9 5 T10 1 T22 1
valid_sources[0x6d] 4178 1 T10 2 T12 2 T22 1
valid_sources[0x6e] 3545 1 T4 1 T9 7 T64 3
valid_sources[0x6f] 3359 1 T9 12 T22 4 T59 7
valid_sources[0x70] 3757 1 T9 2 T11 8 T22 1
valid_sources[0x71] 3974 1 T4 2 T9 19 T11 10
valid_sources[0x72] 3985 1 T4 1 T10 2 T64 3
valid_sources[0x73] 3388 1 T4 2 T22 3 T103 3
valid_sources[0x74] 3505 1 T4 1 T12 5 T64 4
valid_sources[0x75] 3658 1 T4 1 T10 5 T64 5
valid_sources[0x76] 4532 1 T22 4 T43 9 T48 2
valid_sources[0x77] 4244 1 T4 1 T10 2 T64 2
valid_sources[0x78] 3480 1 T9 2 T10 2 T64 5
valid_sources[0x79] 3086 1 T4 1 T9 9 T64 5
valid_sources[0x7a] 3103 1 T10 2 T12 8 T43 17
valid_sources[0x7b] 4205 1 T2 1 T10 1 T12 1
valid_sources[0x7c] 4521 1 T64 6 T22 4 T23 9
valid_sources[0x7d] 3803 1 T10 5 T64 6 T22 2
valid_sources[0x7e] 4138 1 T5 32 T10 2 T12 2
valid_sources[0x7f] 3495 1 T8 1 T10 4 T11 1
valid_sources[0x80] 3779 1 T4 2 T8 1 T10 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 254480 1 T2 15 T4 45 T5 95
values[0x0] all_enables biggest_size 82422 1 T2 7 T4 24 T5 35
values[0x1] all_enables biggest_size 44113 1 T2 4 T4 11 T5 14

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%