Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

20                          logic rst_cause;
21         8/8              always_comb rst_cause = !parent_rst_n || !ctrl_ns[i];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T64,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T64,T57,T65
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T64,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T64,T57,T65
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T64,T57,T65
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T64,T22,T57
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T9
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13518665	14182	0	0
gen_assertions[0].RstEnOn_A	13518665	1101	0	0
gen_assertions[0].RstNOff_A	13518665	14182	0	0
gen_assertions[0].RstNOn_A	13518665	1101	0	0
gen_assertions[1].RstEnOff_A	54074054	12880	0	0
gen_assertions[1].RstEnOn_A	54074054	1023	0	0
gen_assertions[1].RstNOff_A	54074054	12880	0	0
gen_assertions[1].RstNOn_A	54074054	1023	0	0
gen_assertions[2].RstEnOff_A	27037914	12950	0	0
gen_assertions[2].RstEnOn_A	27037914	1042	0	0
gen_assertions[2].RstNOff_A	27037914	12950	0	0
gen_assertions[2].RstNOn_A	27037914	1042	0	0
gen_assertions[3].RstEnOff_A	27037678	13002	0	0
gen_assertions[3].RstEnOn_A	27037678	1085	0	0
gen_assertions[3].RstNOff_A	27037678	13002	0	0
gen_assertions[3].RstNOn_A	27037678	1085	0	0
gen_assertions[4].RstEnOff_A	1705966	21913	0	0
gen_assertions[4].RstEnOn_A	1705966	1118	0	0
gen_assertions[4].RstNOff_A	1705966	21913	0	0
gen_assertions[4].RstNOn_A	1705966	1118	0	0
gen_assertions[5].RstEnOff_A	13518665	14408	0	0
gen_assertions[5].RstEnOn_A	13518665	1187	0	0
gen_assertions[5].RstNOff_A	13518665	14408	0	0
gen_assertions[5].RstNOn_A	13518665	1187	0	0
gen_assertions[6].RstEnOff_A	13518665	14450	0	0
gen_assertions[6].RstEnOn_A	13518665	1217	0	0
gen_assertions[6].RstNOff_A	13518665	14450	0	0
gen_assertions[6].RstNOn_A	13518665	1217	0	0
gen_assertions[7].RstEnOff_A	13518665	14522	0	0
gen_assertions[7].RstEnOn_A	13518665	1292	0	0
gen_assertions[7].RstNOff_A	13518665	14522	0	0
gen_assertions[7].RstNOn_A	13518665	1292	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14182	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	5	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1101	0	0
T2	1955	1	0	0
T3	2587	0	0	0
T4	3510	0	0	0
T5	4750	0	0	0
T6	1656	0	0	0
T7	3095	0	0	0
T8	1494	0	0	0
T9	4878	1	0	0
T10	3518	6	0	0
T11	4293	0	0	0
T12	0	3	0	0
T49	0	4	0	0
T51	0	6	0	0
T57	0	6	0	0
T59	0	1	0	0
T64	0	2	0	0
T65	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14182	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	5	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1101	0	0
T2	1955	1	0	0
T3	2587	0	0	0
T4	3510	0	0	0
T5	4750	0	0	0
T6	1656	0	0	0
T7	3095	0	0	0
T8	1494	0	0	0
T9	4878	1	0	0
T10	3518	6	0	0
T11	4293	0	0	0
T12	0	3	0	0
T49	0	4	0	0
T51	0	6	0	0
T57	0	6	0	0
T59	0	1	0	0
T64	0	2	0	0
T65	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54074054	12880	0	0
T2	7828	3	0	0
T3	10355	0	0	0
T4	14042	4	0	0
T5	19004	4	0	0
T6	6625	0	0	0
T7	12384	2	0	0
T8	5983	0	0	0
T9	19520	4	0	0
T10	14079	15	0	0
T11	17177	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54074054	1023	0	0
T10	14079	3	0	0
T11	17177	0	0	0
T12	24557	0	0	0
T13	28827	0	0	0
T14	18911	0	0	0
T22	17837	0	0	0
T23	107142	0	0	0
T24	28911	0	0	0
T49	0	4	0	0
T51	0	5	0	0
T53	0	13	0	0
T55	0	2	0	0
T57	32908	8	0	0
T64	27083	4	0	0
T65	0	4	0	0
T90	0	1	0	0
T91	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54074054	12880	0	0
T2	7828	3	0	0
T3	10355	0	0	0
T4	14042	4	0	0
T5	19004	4	0	0
T6	6625	0	0	0
T7	12384	2	0	0
T8	5983	0	0	0
T9	19520	4	0	0
T10	14079	15	0	0
T11	17177	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54074054	1023	0	0
T10	14079	3	0	0
T11	17177	0	0	0
T12	24557	0	0	0
T13	28827	0	0	0
T14	18911	0	0	0
T22	17837	0	0	0
T23	107142	0	0	0
T24	28911	0	0	0
T49	0	4	0	0
T51	0	5	0	0
T53	0	13	0	0
T55	0	2	0	0
T57	32908	8	0	0
T64	27083	4	0	0
T65	0	4	0	0
T90	0	1	0	0
T91	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037914	12950	0	0
T2	3914	3	0	0
T3	5177	0	0	0
T4	7022	4	0	0
T5	9502	4	0	0
T6	3312	0	0	0
T7	6193	2	0	0
T8	2991	0	0	0
T9	9761	4	0	0
T10	7039	15	0	0
T11	8588	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037914	1042	0	0
T14	9455	0	0	0
T22	8920	0	0	0
T23	53578	0	0	0
T24	14459	0	0	0
T49	0	5	0	0
T51	0	7	0	0
T53	0	13	0	0
T55	0	3	0	0
T57	16455	6	0	0
T58	4673	0	0	0
T64	13541	4	0	0
T65	14328	4	0	0
T79	6808	0	0	0
T89	45335	0	0	0
T90	0	1	0	0
T91	0	6	0	0
T92	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037914	12950	0	0
T2	3914	3	0	0
T3	5177	0	0	0
T4	7022	4	0	0
T5	9502	4	0	0
T6	3312	0	0	0
T7	6193	2	0	0
T8	2991	0	0	0
T9	9761	4	0	0
T10	7039	15	0	0
T11	8588	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037914	1042	0	0
T14	9455	0	0	0
T22	8920	0	0	0
T23	53578	0	0	0
T24	14459	0	0	0
T49	0	5	0	0
T51	0	7	0	0
T53	0	13	0	0
T55	0	3	0	0
T57	16455	6	0	0
T58	4673	0	0	0
T64	13541	4	0	0
T65	14328	4	0	0
T79	6808	0	0	0
T89	45335	0	0	0
T90	0	1	0	0
T91	0	6	0	0
T92	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037678	13002	0	0
T2	3913	3	0	0
T3	5176	0	0	0
T4	7023	4	0	0
T5	9503	5	0	0
T6	3312	0	0	0
T7	6190	2	0	0
T8	2991	0	0	0
T9	9761	4	0	0
T10	7040	15	0	0
T11	8588	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037678	1085	0	0
T5	9503	1	0	0
T6	3312	0	0	0
T7	6190	0	0	0
T8	2991	0	0	0
T9	9761	0	0	0
T10	7040	0	0	0
T11	8588	0	0	0
T12	12278	0	0	0
T13	14412	0	0	0
T49	0	6	0	0
T51	0	7	0	0
T53	0	15	0	0
T55	0	3	0	0
T57	0	7	0	0
T59	0	1	0	0
T64	13542	5	0	0
T65	0	6	0	0
T91	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037678	13002	0	0
T2	3913	3	0	0
T3	5176	0	0	0
T4	7023	4	0	0
T5	9503	5	0	0
T6	3312	0	0	0
T7	6190	2	0	0
T8	2991	0	0	0
T9	9761	4	0	0
T10	7040	15	0	0
T11	8588	3	0	0
T12	0	16	0	0
T22	0	4	0	0
T64	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27037678	1085	0	0
T5	9503	1	0	0
T6	3312	0	0	0
T7	6190	0	0	0
T8	2991	0	0	0
T9	9761	0	0	0
T10	7040	0	0	0
T11	8588	0	0	0
T12	12278	0	0	0
T13	14412	0	0	0
T49	0	6	0	0
T51	0	7	0	0
T53	0	15	0	0
T55	0	3	0	0
T57	0	7	0	0
T59	0	1	0	0
T64	13542	5	0	0
T65	0	6	0	0
T91	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705966	21913	0	0
T1	324	2	0	0
T2	243	4	0	0
T3	322	2	0	0
T4	438	6	0	0
T5	592	6	0	0
T6	205	1	0	0
T7	386	5	0	0
T8	185	1	0	0
T9	609	6	0	0
T10	439	16	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705966	1118	0	0
T14	589	0	0	0
T22	556	0	0	0
T23	3418	0	0	0
T24	906	0	0	0
T49	0	8	0	0
T51	0	6	0	0
T53	0	15	0	0
T55	0	4	0	0
T56	0	1	0	0
T57	1026	10	0	0
T58	292	0	0	0
T64	845	6	0	0
T65	894	7	0	0
T79	424	0	0	0
T89	2892	0	0	0
T91	0	8	0	0
T93	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705966	21913	0	0
T1	324	2	0	0
T2	243	4	0	0
T3	322	2	0	0
T4	438	6	0	0
T5	592	6	0	0
T6	205	1	0	0
T7	386	5	0	0
T8	185	1	0	0
T9	609	6	0	0
T10	439	16	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705966	1118	0	0
T14	589	0	0	0
T22	556	0	0	0
T23	3418	0	0	0
T24	906	0	0	0
T49	0	8	0	0
T51	0	6	0	0
T53	0	15	0	0
T55	0	4	0	0
T56	0	1	0	0
T57	1026	10	0	0
T58	292	0	0	0
T64	845	6	0	0
T65	894	7	0	0
T79	424	0	0	0
T89	2892	0	0	0
T91	0	8	0	0
T93	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14408	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	4	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1187	0	0
T14	4727	0	0	0
T22	4459	0	0	0
T23	26788	0	0	0
T24	7230	0	0	0
T49	0	7	0	0
T51	0	8	0	0
T53	0	17	0	0
T55	0	6	0	0
T57	8226	7	0	0
T58	2336	0	0	0
T64	6771	7	0	0
T65	7162	8	0	0
T79	3404	0	0	0
T88	0	8	0	0
T89	22672	0	0	0
T91	0	8	0	0
T93	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14408	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	4	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1187	0	0
T14	4727	0	0	0
T22	4459	0	0	0
T23	26788	0	0	0
T24	7230	0	0	0
T49	0	7	0	0
T51	0	8	0	0
T53	0	17	0	0
T55	0	6	0	0
T57	8226	7	0	0
T58	2336	0	0	0
T64	6771	7	0	0
T65	7162	8	0	0
T79	3404	0	0	0
T88	0	8	0	0
T89	22672	0	0	0
T91	0	8	0	0
T93	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14450	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	4	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	5	0	0
T64	0	7	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1217	0	0
T14	4727	0	0	0
T22	4459	1	0	0
T23	26788	0	0	0
T24	7230	0	0	0
T49	0	10	0	0
T51	0	7	0	0
T53	0	12	0	0
T55	0	6	0	0
T56	0	1	0	0
T57	8226	11	0	0
T58	2336	0	0	0
T59	0	1	0	0
T64	6771	7	0	0
T65	7162	10	0	0
T79	3404	0	0	0
T89	22672	0	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14450	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	4	0	0
T6	1656	0	0	0
T7	3095	4	0	0
T8	1494	0	0	0
T9	4878	4	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	5	0	0
T64	0	7	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1217	0	0
T14	4727	0	0	0
T22	4459	1	0	0
T23	26788	0	0	0
T24	7230	0	0	0
T49	0	10	0	0
T51	0	7	0	0
T53	0	12	0	0
T55	0	6	0	0
T56	0	1	0	0
T57	8226	11	0	0
T58	2336	0	0	0
T59	0	1	0	0
T64	6771	7	0	0
T65	7162	10	0	0
T79	3404	0	0	0
T89	22672	0	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14522	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	5	0	0
T6	1656	0	0	0
T7	3095	5	0	0
T8	1494	0	0	0
T9	4878	5	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	10	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1292	0	0
T5	4750	1	0	0
T6	1656	0	0	0
T7	3095	1	0	0
T8	1494	0	0	0
T9	4878	1	0	0
T10	3518	0	0	0
T11	4293	0	0	0
T12	6138	0	0	0
T13	7208	0	0	0
T49	0	11	0	0
T51	0	4	0	0
T53	0	15	0	0
T55	0	8	0	0
T57	0	12	0	0
T64	6771	10	0	0
T65	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	14522	0	0
T2	1955	3	0	0
T3	2587	0	0	0
T4	3510	4	0	0
T5	4750	5	0	0
T6	1656	0	0	0
T7	3095	5	0	0
T8	1494	0	0	0
T9	4878	5	0	0
T10	3518	16	0	0
T11	4293	4	0	0
T12	0	17	0	0
T22	0	4	0	0
T64	0	10	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13518665	1292	0	0
T5	4750	1	0	0
T6	1656	0	0	0
T7	3095	1	0	0
T8	1494	0	0	0
T9	4878	1	0	0
T10	3518	0	0	0
T11	4293	0	0	0
T12	6138	0	0	0
T13	7208	0	0	0
T49	0	11	0	0
T51	0	4	0	0
T53	0	15	0	0
T55	0	8	0	0
T57	0	12	0	0
T64	6771	10	0	0
T65	0	10	0	0