Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12812309	9876	0	0
alert_regwen_rd_A	12812309	6823	0	0
cpu_regwen_rd_A	12812309	6801	0	0
sw_rst_ctrl_n_0_rd_A	12812309	11983	0	0
sw_rst_ctrl_n_1_rd_A	12812309	11971	0	0
sw_rst_ctrl_n_2_rd_A	12812309	11935	0	0
sw_rst_ctrl_n_3_rd_A	12812309	12241	0	0
sw_rst_ctrl_n_4_rd_A	12812309	11881	0	0
sw_rst_ctrl_n_5_rd_A	12812309	11973	0	0
sw_rst_ctrl_n_6_rd_A	12812309	11763	0	0
sw_rst_ctrl_n_7_rd_A	12812309	11651	0	0
sw_rst_regwen_0_rd_A	12812309	7317	0	0
sw_rst_regwen_1_rd_A	12812309	7434	0	0
sw_rst_regwen_2_rd_A	12812309	7407	0	0
sw_rst_regwen_3_rd_A	12812309	7241	0	0
sw_rst_regwen_4_rd_A	12812309	7450	0	0
sw_rst_regwen_5_rd_A	12812309	7416	0	0
sw_rst_regwen_6_rd_A	12812309	7295	0	0
sw_rst_regwen_7_rd_A	12812309	7441	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	9876	0	0
T68	10573	4	0	0
T74	4034	317	0	0
T75	5004	26	0	0
T76	3033	24	0	0
T77	10588	627	0	0
T78	20782	2	0	0
T97	3130	8	0	0
T98	4711	702	0	0
T99	3222	346	0	0
T100	2846	120	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	6823	0	0
T16	3030	0	0	0
T42	0	71	0	0
T51	41915	51	0	0
T52	39770	30	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	0	0	0
T56	6011	0	0	0
T62	55205	0	0	0
T86	0	81	0	0
T90	1948	0	0	0
T108	1821	0	0	0
T109	0	66	0	0
T113	0	55	0	0
T114	0	266	0	0
T138	0	60	0	0
T139	0	296	0	0
T140	0	87	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	6801	0	0
T16	3030	0	0	0
T42	0	68	0	0
T51	41915	53	0	0
T52	39770	29	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	0	0	0
T56	6011	0	0	0
T62	55205	0	0	0
T86	0	53	0	0
T90	1948	0	0	0
T108	1821	0	0	0
T109	0	68	0	0
T113	0	58	0	0
T114	0	311	0	0
T138	0	24	0	0
T139	0	270	0	0
T140	0	100	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11983	0	0
T12	4929	41	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	4	0	0
T51	0	122	0	0
T52	0	41	0	0
T55	0	128	0	0
T56	0	16	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	14	0	0
T86	0	95	0	0
T89	17830	0	0	0
T91	0	81	0	0
T141	0	48	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11971	0	0
T12	4929	60	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	11	0	0
T51	0	107	0	0
T52	0	30	0	0
T55	0	116	0	0
T56	0	7	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	10	0	0
T86	0	72	0	0
T89	17830	0	0	0
T91	0	82	0	0
T141	0	47	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11935	0	0
T12	4929	47	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	2	0	0
T51	0	124	0	0
T52	0	41	0	0
T55	0	107	0	0
T56	0	24	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	14	0	0
T86	0	85	0	0
T89	17830	0	0	0
T91	0	71	0	0
T141	0	55	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	12241	0	0
T12	4929	63	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	14	0	0
T51	0	147	0	0
T52	0	46	0	0
T55	0	95	0	0
T56	0	10	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	5	0	0
T86	0	59	0	0
T89	17830	0	0	0
T91	0	78	0	0
T141	0	63	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11881	0	0
T12	4929	65	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	7	0	0
T51	0	133	0	0
T52	0	35	0	0
T55	0	124	0	0
T56	0	12	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	7	0	0
T86	0	64	0	0
T89	17830	0	0	0
T91	0	91	0	0
T141	0	38	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11973	0	0
T12	4929	59	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	12	0	0
T51	0	133	0	0
T52	0	54	0	0
T55	0	113	0	0
T56	0	13	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	17	0	0
T86	0	70	0	0
T89	17830	0	0	0
T91	0	72	0	0
T141	0	50	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11763	0	0
T12	4929	68	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	7	0	0
T38	0	6	0	0
T51	0	94	0	0
T52	0	37	0	0
T55	0	133	0	0
T56	0	22	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T86	0	88	0	0
T89	17830	0	0	0
T91	0	86	0	0
T141	0	49	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	11651	0	0
T12	4929	53	0	0
T14	4588	0	0	0
T22	4362	0	0	0
T23	23240	0	0	0
T24	6549	0	0	0
T37	0	9	0	0
T51	0	142	0	0
T52	0	56	0	0
T55	0	88	0	0
T56	0	14	0	0
T57	8207	0	0	0
T64	6728	0	0	0
T65	7097	0	0	0
T79	3260	0	0	0
T85	0	11	0	0
T86	0	92	0	0
T89	17830	0	0	0
T91	0	70	0	0
T141	0	63	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7317	0	0
T16	3030	0	0	0
T38	0	4	0	0
T42	0	89	0	0
T51	41915	54	0	0
T52	39770	63	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	33	0	0
T56	6011	6	0	0
T62	55205	0	0	0
T85	0	9	0	0
T86	0	67	0	0
T90	1948	0	0	0
T91	0	24	0	0
T108	1821	0	0	0
T142	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7434	0	0
T16	3030	0	0	0
T38	0	3	0	0
T42	0	76	0	0
T51	41915	36	0	0
T52	39770	20	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	34	0	0
T56	6011	6	0	0
T62	55205	0	0	0
T85	0	15	0	0
T86	0	95	0	0
T90	1948	0	0	0
T91	0	5	0	0
T108	1821	0	0	0
T142	0	27	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7407	0	0
T16	3030	0	0	0
T38	0	5	0	0
T42	0	72	0	0
T51	41915	40	0	0
T52	39770	31	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	18	0	0
T56	6011	3	0	0
T62	55205	0	0	0
T85	0	6	0	0
T86	0	61	0	0
T90	1948	0	0	0
T91	0	11	0	0
T108	1821	0	0	0
T142	0	17	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7241	0	0
T16	3030	0	0	0
T38	0	9	0	0
T42	0	77	0	0
T51	41915	61	0	0
T52	39770	23	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	51	0	0
T56	6011	13	0	0
T62	55205	0	0	0
T85	0	6	0	0
T86	0	74	0	0
T90	1948	0	0	0
T91	0	23	0	0
T108	1821	0	0	0
T142	0	9	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7450	0	0
T16	3030	0	0	0
T42	0	76	0	0
T51	41915	45	0	0
T52	39770	33	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	23	0	0
T56	6011	16	0	0
T62	55205	0	0	0
T85	0	1	0	0
T86	0	76	0	0
T90	1948	0	0	0
T91	0	28	0	0
T108	1821	0	0	0
T109	0	56	0	0
T142	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7416	0	0
T16	3030	0	0	0
T38	0	7	0	0
T42	0	75	0	0
T51	41915	37	0	0
T52	39770	66	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	35	0	0
T56	6011	5	0	0
T62	55205	0	0	0
T85	0	2	0	0
T86	0	89	0	0
T90	1948	0	0	0
T91	0	25	0	0
T108	1821	0	0	0
T142	0	13	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7295	0	0
T16	3030	0	0	0
T38	0	9	0	0
T42	0	79	0	0
T51	41915	66	0	0
T52	39770	22	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	49	0	0
T56	6011	0	0	0
T62	55205	0	0	0
T85	0	6	0	0
T86	0	79	0	0
T90	1948	0	0	0
T91	0	10	0	0
T108	1821	0	0	0
T109	0	54	0	0
T142	0	16	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12812309	7441	0	0
T16	3030	0	0	0
T38	0	3	0	0
T42	0	62	0	0
T51	41915	59	0	0
T52	39770	43	0	0
T53	26274	0	0	0
T54	2134	0	0	0
T55	8653	24	0	0
T56	6011	5	0	0
T62	55205	0	0	0
T85	0	1	0	0
T86	0	82	0	0
T90	1948	0	0	0
T91	0	11	0	0
T108	1821	0	0	0
T142	0	2	0	0