Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8480

1

T3

7

T12

12

T22

29

auto[1]

11433

1

T3

1

T4

4

T5

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6158	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6717	1			T1	1		T2	1		T3	1
reset_info_cp[2]	3045	1			T4	1		T5	1		T9	1
reset_info_cp[4]	4029	1			T4	1		T5	1		T9	1
reset_info_cp[8]	118	1			T12	1		T22	1		T88	1
reset_info_cp[16]	105	1			T9	1		T108	1		T28	1
reset_info_cp[32]	110	1			T12	1		T26	2		T107	1
reset_info_cp[64]	129	1			T24	1		T88	1		T26	1
reset_info_cp[128]	108	1			T3	2		T4	1		T12	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3241	1			T22	9		T88	11		T26	17
reset_info_cp[1]	auto[1]	2870	1			T4	1		T5	1		T9	1
reset_info_cp[2]	auto[0]	969	1			T22	4		T38	2		T107	2
reset_info_cp[2]	auto[1]	2076	1			T4	1		T5	1		T9	1
reset_info_cp[4]	auto[0]	1475	1			T22	5		T88	3		T38	3
reset_info_cp[4]	auto[1]	2554	1			T4	1		T5	1		T9	1
reset_info_cp[8]	auto[0]	45	1			T12	1		T22	1		T43	1
reset_info_cp[8]	auto[1]	73	1			T88	1		T46	1		T28	2
reset_info_cp[16]	auto[0]	39	1			T164	1		T118	1		T115	1
reset_info_cp[16]	auto[1]	66	1			T9	1		T108	1		T28	1
reset_info_cp[32]	auto[0]	51	1			T12	1		T55	1		T56	2
reset_info_cp[32]	auto[1]	59	1			T26	2		T107	1		T46	1
reset_info_cp[64]	auto[0]	56	1			T43	4		T165	2		T83	1
reset_info_cp[64]	auto[1]	73	1			T24	1		T88	1		T26	1
reset_info_cp[128]	auto[0]	44	1			T3	2		T12	1		T92	1
reset_info_cp[128]	auto[1]	64	1			T4	1		T46	1		T55	1