Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.46 99.40 99.31 100.00 99.83 99.46 98.77


Total tests in report: 606
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
83.84 83.84 94.59 94.59 87.16 87.16 89.57 89.57 92.92 92.92 88.56 88.56 50.25 50.25 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.503677718
90.24 6.40 97.24 2.64 93.41 6.25 91.16 1.59 97.81 4.89 92.60 4.04 69.21 18.97 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2196949006
92.71 2.47 97.66 0.42 93.62 0.21 95.73 4.57 98.15 0.34 93.27 0.67 77.83 8.62 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1419868491
94.82 2.11 98.38 0.72 95.35 1.73 96.06 0.34 98.99 0.84 93.94 0.67 86.21 8.37 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.4105325942
96.30 1.48 98.98 0.60 95.98 0.62 98.74 2.68 99.83 0.84 97.58 3.63 86.70 0.49 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.621734347
97.03 0.73 99.10 0.12 96.32 0.35 98.99 0.25 99.83 0.00 98.79 1.21 89.16 2.46 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.2921660694
97.60 0.57 99.10 0.00 97.02 0.69 98.99 0.00 99.83 0.00 98.79 0.00 91.87 2.71 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2954328200
97.94 0.34 99.10 0.00 97.09 0.07 98.99 0.00 99.83 0.00 98.79 0.00 93.84 1.97 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4072288228
98.27 0.33 99.40 0.30 97.43 0.35 99.58 0.59 99.83 0.00 98.79 0.00 94.58 0.74 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3026374884
98.60 0.33 99.40 0.00 97.43 0.00 99.58 0.00 99.83 0.00 98.79 0.00 96.55 1.97 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2846691732
98.84 0.25 99.40 0.00 97.43 0.00 99.58 0.00 99.83 0.00 98.79 0.00 98.03 1.48 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1262889083
99.08 0.24 99.40 0.00 98.61 1.18 99.58 0.00 99.83 0.00 98.79 0.00 98.28 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2224069411
99.17 0.09 99.40 0.00 98.61 0.00 99.58 0.00 99.83 0.00 99.06 0.27 98.52 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.4001868114
99.25 0.08 99.40 0.00 98.61 0.00 99.92 0.34 99.83 0.00 99.19 0.13 98.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.3548341863
99.31 0.07 99.40 0.00 99.03 0.42 99.92 0.00 99.83 0.00 99.19 0.00 98.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.3478155148
99.36 0.04 99.40 0.00 99.03 0.00 99.92 0.00 99.83 0.00 99.19 0.00 98.77 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3422039221
99.39 0.03 99.40 0.00 99.24 0.21 99.92 0.00 99.83 0.00 99.19 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4217522839
99.41 0.02 99.40 0.00 99.24 0.00 99.92 0.00 99.83 0.00 99.33 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.2672484005
99.44 0.02 99.40 0.00 99.24 0.00 99.92 0.00 99.83 0.00 99.46 0.13 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1788246982
99.45 0.01 99.40 0.00 99.24 0.00 100.00 0.08 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2415015224
99.46 0.01 99.40 0.00 99.31 0.07 100.00 0.00 99.83 0.00 99.46 0.00 98.77 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.762082517

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.3833316517
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3983938696
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.542736718
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.1588406292
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.228646233
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2271572967
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.2764074624
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1358415926
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.4268261729
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3438317342
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2958860751
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.3671810817
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1222170688
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3914143244
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3410394827
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.4040743988
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1689027597
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.1370736169
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.830272991
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.41986166
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1941118640
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.2528135412
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.3941044262
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1194469542
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2982940323
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.543868521
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.579249023
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.409415741
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1308673027
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.594828088
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3592505836
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1840469959
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3701325733
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.491449936
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.2653967748
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1858416466
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1630811386
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.2762272045
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.3267467380
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.694859378
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.2287563842
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1762753939
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2466156894
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.3550770264
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3629799842
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.2827071693
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1436315623
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.3250108777
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.33042268
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.3940174861
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1050717490
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.4031918831
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1826051967
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.829967023
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.2609208453
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.3807545391
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.4132285970
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.819609663
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.366306301
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.4013368494
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1473153148
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3289273419
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.697470709
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.3952660021
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.418823476
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.3534767094
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.3126071113
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4109005074
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.223017373
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2891123051
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.2259869550
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2396631149
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.961818761
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3911188261
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.2024142127
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.1502560444
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.1779668011
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.2303809436
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.4176125604
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.3395909737
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.1732708911
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.2805257370
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.1120352936
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3876018836
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.2445054902
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.1855247257
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.1348604092
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.2647674650
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1126172609
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.1687627832
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.3128120643
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.2489274688
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1023938615
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3186469512
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.1336500326
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1140964862
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.3867240097
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.2198838668
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1306504975
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3607369966
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/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1789781888
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.649197019
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.120041233
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.823369820
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.1525825333
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.1757462003
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1886097980
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2067144435
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.1080585157
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.440783800
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2537156895
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.579415849
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2155158642
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3129875456
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2718910010
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.3003480250
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3848386014
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3851024559
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2337200148
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.1995152697
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.1880088950
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3071213013
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3427424520
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1962217845
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2104846483
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1211524366
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2345637984
/workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.4274880416



Total test records in report: 606
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1788246982 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 205332941 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3026374884 Sep 24 09:37:30 PM UTC 24 Sep 24 09:37:32 PM UTC 24 76777882 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.3422039221 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 98238825 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2846691732 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 106327577 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.503677718 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 202955838 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.728120849 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:32 PM UTC 24 301081742 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.1886097980 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:46 PM UTC 24 371665786 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.3779148237 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 196286503 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.1747411900 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 101776095 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.2952348071 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 192203417 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.939709917 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 84785237 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.704529668 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 70404099 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.3305150013 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 307527103 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1952545954 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:33 PM UTC 24 181204139 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1016152235 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:34 PM UTC 24 504824593 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1810452259 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:34 PM UTC 24 182110729 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.2007015332 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:35 PM UTC 24 57954965 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.2196949006 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:35 PM UTC 24 411742155 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.3707334581 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:35 PM UTC 24 805866820 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1444910419 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:35 PM UTC 24 186411554 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.3246170551 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:35 PM UTC 24 126828117 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.4188668062 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:35 PM UTC 24 303024789 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.1575414754 Sep 24 09:37:33 PM UTC 24 Sep 24 09:37:35 PM UTC 24 189532037 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.1310561895 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:36 PM UTC 24 329871941 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.676693156 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:36 PM UTC 24 195953145 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3836571505 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:36 PM UTC 24 141161036 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.4125104912 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:36 PM UTC 24 155192906 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2254534793 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:37 PM UTC 24 302331895 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.2921660694 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:37 PM UTC 24 937869456 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.1419868491 Sep 24 09:37:29 PM UTC 24 Sep 24 09:37:37 PM UTC 24 1271421893 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.2441389546 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:37 PM UTC 24 382775460 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.1416116406 Sep 24 09:37:35 PM UTC 24 Sep 24 09:37:38 PM UTC 24 79202751 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.1789063830 Sep 24 09:37:35 PM UTC 24 Sep 24 09:37:38 PM UTC 24 77786455 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1369654954 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:38 PM UTC 24 869667035 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.2932236028 Sep 24 09:37:35 PM UTC 24 Sep 24 09:37:38 PM UTC 24 114898739 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3639770097 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:38 PM UTC 24 104280999 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.876907817 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:38 PM UTC 24 68909955 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3548740998 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:38 PM UTC 24 301079140 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.2047528775 Sep 24 09:37:35 PM UTC 24 Sep 24 09:37:39 PM UTC 24 250159646 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.2306242067 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:39 PM UTC 24 139397076 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.3537417101 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:39 PM UTC 24 159790078 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3518293274 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:39 PM UTC 24 266572383 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1166199538 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:39 PM UTC 24 78239206 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.49558405 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:40 PM UTC 24 302524512 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.1422124166 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:40 PM UTC 24 102415006 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1142250414 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:40 PM UTC 24 125825642 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.2179565334 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:41 PM UTC 24 1375916964 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.2415015224 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:41 PM UTC 24 1957596290 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.77735581 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:41 PM UTC 24 52647264 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4277812364 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:41 PM UTC 24 119915596 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.415202247 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:41 PM UTC 24 186114542 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1312467506 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:41 PM UTC 24 196994506 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.4244379040 Sep 24 09:37:35 PM UTC 24 Sep 24 09:37:41 PM UTC 24 819166090 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.573430945 Sep 24 09:37:32 PM UTC 24 Sep 24 09:37:42 PM UTC 24 1960960582 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.3227752610 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:42 PM UTC 24 222289501 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.66845164 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:42 PM UTC 24 356373996 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.4121547449 Sep 24 09:37:40 PM UTC 24 Sep 24 09:37:42 PM UTC 24 61279605 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.649197019 Sep 24 09:37:40 PM UTC 24 Sep 24 09:37:43 PM UTC 24 151195954 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.1525825333 Sep 24 09:37:40 PM UTC 24 Sep 24 09:37:43 PM UTC 24 112564179 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.311915991 Sep 24 09:37:40 PM UTC 24 Sep 24 09:37:43 PM UTC 24 301400617 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1262889083 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:44 PM UTC 24 1226424557 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2593759100 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:44 PM UTC 24 71068726 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.823369820 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:44 PM UTC 24 102324082 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3473538587 Sep 24 09:37:34 PM UTC 24 Sep 24 09:37:45 PM UTC 24 1961551714 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.1789781888 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:45 PM UTC 24 301209395 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.579415849 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:45 PM UTC 24 223447045 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.2718910010 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:45 PM UTC 24 190122640 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3851024559 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:45 PM UTC 24 159289620 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2067144435 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:45 PM UTC 24 228024588 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.3585783451 Sep 24 09:37:39 PM UTC 24 Sep 24 09:37:45 PM UTC 24 784777682 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.4112883050 Sep 24 09:37:37 PM UTC 24 Sep 24 09:37:46 PM UTC 24 1967217425 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.1080585157 Sep 24 09:37:44 PM UTC 24 Sep 24 09:37:46 PM UTC 24 69076466 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.3129875456 Sep 24 09:37:43 PM UTC 24 Sep 24 09:37:46 PM UTC 24 97909489 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.2537156895 Sep 24 09:37:44 PM UTC 24 Sep 24 09:37:46 PM UTC 24 302029491 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.4172934183 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:47 PM UTC 24 2268678411 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3071213013 Sep 24 09:37:45 PM UTC 24 Sep 24 09:37:47 PM UTC 24 140026300 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3848386014 Sep 24 09:37:43 PM UTC 24 Sep 24 09:37:47 PM UTC 24 370539008 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.120041233 Sep 24 09:37:41 PM UTC 24 Sep 24 09:37:48 PM UTC 24 1377157300 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.2104846483 Sep 24 09:37:45 PM UTC 24 Sep 24 09:37:48 PM UTC 24 230998266 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.2337200148 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:48 PM UTC 24 80440292 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.4274880416 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:49 PM UTC 24 146527979 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.3506756806 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:49 PM UTC 24 113368746 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.1962217845 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:49 PM UTC 24 103449605 ps
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T180 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1211524366 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:49 PM UTC 24 195247910 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.2345637984 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:50 PM UTC 24 368209686 ps
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T183 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.2037621635 Sep 24 09:37:48 PM UTC 24 Sep 24 09:37:50 PM UTC 24 68165688 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.2155158642 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:50 PM UTC 24 947411613 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.4054151122 Sep 24 09:37:48 PM UTC 24 Sep 24 09:37:50 PM UTC 24 161368472 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.4034710847 Sep 24 09:37:48 PM UTC 24 Sep 24 09:37:51 PM UTC 24 301442749 ps
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T186 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.11031809 Sep 24 09:37:49 PM UTC 24 Sep 24 09:37:51 PM UTC 24 67162173 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.3567586798 Sep 24 09:37:49 PM UTC 24 Sep 24 09:37:52 PM UTC 24 175612413 ps
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T30 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.1385771806 Sep 24 09:37:42 PM UTC 24 Sep 24 09:37:52 PM UTC 24 2246136772 ps
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T119 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3427424520 Sep 24 09:37:45 PM UTC 24 Sep 24 09:37:53 PM UTC 24 1703453755 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.3546504824 Sep 24 09:37:50 PM UTC 24 Sep 24 09:37:53 PM UTC 24 95950521 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.1878691567 Sep 24 09:37:51 PM UTC 24 Sep 24 09:37:53 PM UTC 24 95332423 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.3534159540 Sep 24 09:37:51 PM UTC 24 Sep 24 09:37:53 PM UTC 24 80957708 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.3424107102 Sep 24 09:37:51 PM UTC 24 Sep 24 09:37:54 PM UTC 24 302273701 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.9471838 Sep 24 09:37:48 PM UTC 24 Sep 24 09:37:54 PM UTC 24 742575776 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3755156515 Sep 24 09:37:51 PM UTC 24 Sep 24 09:37:54 PM UTC 24 111564111 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3914455686 Sep 24 09:37:51 PM UTC 24 Sep 24 09:37:54 PM UTC 24 225820710 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.3547210879 Sep 24 09:37:49 PM UTC 24 Sep 24 09:37:54 PM UTC 24 777446559 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1024815570 Sep 24 09:37:36 PM UTC 24 Sep 24 09:37:55 PM UTC 24 8452343367 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.1559020282 Sep 24 09:37:50 PM UTC 24 Sep 24 09:37:55 PM UTC 24 359736776 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.59861757 Sep 24 09:37:52 PM UTC 24 Sep 24 09:37:55 PM UTC 24 65068421 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.1995152697 Sep 24 09:37:46 PM UTC 24 Sep 24 09:37:55 PM UTC 24 1959054432 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.1207739973 Sep 24 09:37:52 PM UTC 24 Sep 24 09:37:55 PM UTC 24 96408806 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.4089879043 Sep 24 09:37:52 PM UTC 24 Sep 24 09:37:55 PM UTC 24 213743258 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.4167882724 Sep 24 09:37:52 PM UTC 24 Sep 24 09:37:55 PM UTC 24 301525196 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.1516507430 Sep 24 09:37:54 PM UTC 24 Sep 24 09:37:56 PM UTC 24 111820949 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.768054216 Sep 24 09:37:54 PM UTC 24 Sep 24 09:37:56 PM UTC 24 98165105 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.2022513608 Sep 24 09:37:54 PM UTC 24 Sep 24 09:37:56 PM UTC 24 192904603 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.1090665663 Sep 24 09:37:52 PM UTC 24 Sep 24 09:37:56 PM UTC 24 528999257 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.1458852818 Sep 24 09:37:54 PM UTC 24 Sep 24 09:37:57 PM UTC 24 151539709 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.1954900982 Sep 24 09:37:55 PM UTC 24 Sep 24 09:38:06 PM UTC 24 2443641172 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.3352649682 Sep 24 09:37:54 PM UTC 24 Sep 24 09:37:57 PM UTC 24 138818458 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.2775934815 Sep 24 09:37:55 PM UTC 24 Sep 24 09:37:57 PM UTC 24 81732392 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.775127748 Sep 24 09:37:55 PM UTC 24 Sep 24 09:37:57 PM UTC 24 164730839 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3206251377 Sep 24 09:37:55 PM UTC 24 Sep 24 09:37:57 PM UTC 24 302162781 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.2281030287 Sep 24 09:37:48 PM UTC 24 Sep 24 09:37:58 PM UTC 24 2270471107 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.462477493 Sep 24 09:37:55 PM UTC 24 Sep 24 09:37:58 PM UTC 24 261331985 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.4072288228 Sep 24 09:37:31 PM UTC 24 Sep 24 09:37:59 PM UTC 24 5288980342 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.4001699584 Sep 24 09:37:57 PM UTC 24 Sep 24 09:37:59 PM UTC 24 60984780 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.1205014696 Sep 24 09:37:56 PM UTC 24 Sep 24 09:37:59 PM UTC 24 280237625 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.647020736 Sep 24 09:37:57 PM UTC 24 Sep 24 09:38:00 PM UTC 24 153819457 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.3743077097 Sep 24 09:37:57 PM UTC 24 Sep 24 09:38:00 PM UTC 24 302750057 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.6109211 Sep 24 09:37:52 PM UTC 24 Sep 24 09:38:00 PM UTC 24 1277463452 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.1419581539 Sep 24 09:37:52 PM UTC 24 Sep 24 09:38:00 PM UTC 24 1633501208 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.880241340 Sep 24 09:37:57 PM UTC 24 Sep 24 09:38:00 PM UTC 24 229566663 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1665909794 Sep 24 09:37:56 PM UTC 24 Sep 24 09:38:00 PM UTC 24 514579642 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.3497855695 Sep 24 09:37:58 PM UTC 24 Sep 24 09:38:00 PM UTC 24 102286574 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.3486736685 Sep 24 09:37:58 PM UTC 24 Sep 24 09:38:01 PM UTC 24 189904890 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3905625180 Sep 24 09:37:58 PM UTC 24 Sep 24 09:38:01 PM UTC 24 302404973 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.737810465 Sep 24 09:37:54 PM UTC 24 Sep 24 09:38:01 PM UTC 24 993505416 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.738468271 Sep 24 09:37:51 PM UTC 24 Sep 24 09:38:01 PM UTC 24 1964010528 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.1503656657 Sep 24 09:37:32 PM UTC 24 Sep 24 09:38:01 PM UTC 24 16639289109 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.621734347 Sep 24 09:37:29 PM UTC 24 Sep 24 09:38:01 PM UTC 24 17366340459 ps
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T205 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.4096908446 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:06 PM UTC 24 200111538 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3217540777 Sep 24 09:37:39 PM UTC 24 Sep 24 09:38:01 PM UTC 24 4170113704 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.3809927107 Sep 24 09:37:59 PM UTC 24 Sep 24 09:38:01 PM UTC 24 62897586 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.4156561333 Sep 24 09:38:00 PM UTC 24 Sep 24 09:38:02 PM UTC 24 140207091 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.1978526149 Sep 24 09:37:58 PM UTC 24 Sep 24 09:38:02 PM UTC 24 327280549 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3817856893 Sep 24 09:37:59 PM UTC 24 Sep 24 09:38:02 PM UTC 24 115203419 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3981050486 Sep 24 09:38:01 PM UTC 24 Sep 24 09:38:03 PM UTC 24 65739035 ps
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T115 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.4001868114 Sep 24 09:37:55 PM UTC 24 Sep 24 09:38:03 PM UTC 24 1721205487 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.2684326779 Sep 24 09:38:01 PM UTC 24 Sep 24 09:38:04 PM UTC 24 302530455 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.1916399656 Sep 24 09:38:01 PM UTC 24 Sep 24 09:38:04 PM UTC 24 262076956 ps
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T216 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.3532704991 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:05 PM UTC 24 70077834 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.3890792832 Sep 24 09:38:02 PM UTC 24 Sep 24 09:38:05 PM UTC 24 253197440 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.2193461894 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:05 PM UTC 24 220901908 ps
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T220 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1481311506 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:06 PM UTC 24 179357497 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.2598679847 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:06 PM UTC 24 301649732 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.1011551634 Sep 24 09:38:03 PM UTC 24 Sep 24 09:38:06 PM UTC 24 266622510 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.4237746951 Sep 24 09:38:04 PM UTC 24 Sep 24 09:38:06 PM UTC 24 95776352 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.3356209401 Sep 24 09:38:01 PM UTC 24 Sep 24 09:38:06 PM UTC 24 827740149 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3683251557 Sep 24 09:38:04 PM UTC 24 Sep 24 09:38:06 PM UTC 24 97361163 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.2551266720 Sep 24 09:37:34 PM UTC 24 Sep 24 09:38:07 PM UTC 24 6220285720 ps
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T229 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.139711476 Sep 24 09:38:04 PM UTC 24 Sep 24 09:38:08 PM UTC 24 338792499 ps
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T290 /workspaces/repo/scratch/os_regression_2024_09_23/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.1941135092 Sep 24 09:38:18 PM UTC 24 Sep 24 09:38:22 PM UTC 24 383570012 ps
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