Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7964

1

T3

16

T4

20

T10

9

auto[1]

10933

1

T1

4

T3

1

T4

26

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5765	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6443	1			T1	2		T2	1		T3	1
reset_info_cp[2]	2932	1			T1	1		T4	8		T6	1
reset_info_cp[4]	3794	1			T1	1		T4	11		T6	1
reset_info_cp[8]	120	1			T3	2		T4	1		T54	1
reset_info_cp[16]	123	1			T3	1		T62	1		T44	1
reset_info_cp[32]	114	1			T3	1		T62	1		T55	2
reset_info_cp[64]	110	1			T3	1		T23	1		T62	1
reset_info_cp[128]	116	1			T23	1		T55	3		T43	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	3070	1			T4	2		T22	14		T23	22
reset_info_cp[1]	auto[1]	2753	1			T1	1		T4	14		T6	1
reset_info_cp[2]	auto[0]	913	1			T4	6		T22	7		T54	7
reset_info_cp[2]	auto[1]	2019	1			T1	1		T4	2		T6	1
reset_info_cp[4]	auto[0]	1396	1			T4	5		T22	7		T54	9
reset_info_cp[4]	auto[1]	2398	1			T1	1		T4	6		T6	1
reset_info_cp[8]	auto[0]	52	1			T3	2		T95	1		T96	1
reset_info_cp[8]	auto[1]	68	1			T4	1		T54	1		T43	1
reset_info_cp[16]	auto[0]	57	1			T3	1		T62	1		T41	1
reset_info_cp[16]	auto[1]	66	1			T44	1		T27	2		T28	1
reset_info_cp[32]	auto[0]	39	1			T3	1		T62	1		T55	1
reset_info_cp[32]	auto[1]	75	1			T55	1		T42	1		T43	1
reset_info_cp[64]	auto[0]	41	1			T3	1		T62	1		T96	1
reset_info_cp[64]	auto[1]	69	1			T23	1		T26	1		T27	1
reset_info_cp[128]	auto[0]	49	1			T55	3		T96	1		T135	2
reset_info_cp[128]	auto[1]	67	1			T23	1		T43	1		T28	1