| | | | | | | |
tb.dut.AlertsKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.ParameterMatch_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.PwrKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.ResetsKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.RstEnKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.TlAReadyKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.TlDValidKnownO_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A
| 0 | 0 | 11182148 | 70 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1591058 | 963268 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8923 | 8418 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 6794 | 6289 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1591058 | 945218 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A
| 0 | 0 | 11182148 | 12761 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A
| 0 | 0 | 11182148 | 117651 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A
| 0 | 0 | 11182148 | 6521481 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A
| 0 | 0 | 11182148 | 187922 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A
| 0 | 0 | 11182148 | 12761 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A
| 0 | 0 | 11182148 | 117651 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A
| 0 | 0 | 11182148 | 6521481 | 0 | 0 |
|
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A
| 0 | 0 | 11182148 | 187922 | 0 | 0 |
|
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A
| 0 | 0 | 52510496 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A
| 0 | 0 | 52510496 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A
| 0 | 0 | 50408579 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A
| 0 | 0 | 50408579 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A
| 0 | 0 | 25205250 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A
| 0 | 0 | 25205250 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A
| 0 | 0 | 12601978 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A
| 0 | 0 | 12601978 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A
| 0 | 0 | 25205103 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A
| 0 | 0 | 25205103 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A
| 0 | 0 | 1591058 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A
| 0 | 0 | 1591058 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A
| 0 | 0 | 1591058 | 6799 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A
| 0 | 0 | 1591058 | 213 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A
| 0 | 0 | 1591058 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A
| 0 | 0 | 12601978 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A
| 0 | 0 | 12601978 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A
| 0 | 0 | 11182148 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A
| 0 | 0 | 12033793 | 7424 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A
| 0 | 0 | 12033793 | 4612 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A
| 0 | 0 | 12033793 | 4640 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A
| 0 | 0 | 12033793 | 7807 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A
| 0 | 0 | 12033793 | 7926 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A
| 0 | 0 | 12033793 | 7778 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A
| 0 | 0 | 12033793 | 7784 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A
| 0 | 0 | 12033793 | 8155 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A
| 0 | 0 | 12033793 | 8107 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A
| 0 | 0 | 12033793 | 8048 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A
| 0 | 0 | 12033793 | 8015 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A
| 0 | 0 | 12033793 | 5062 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A
| 0 | 0 | 12033793 | 5073 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A
| 0 | 0 | 12033793 | 5115 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A
| 0 | 0 | 12033793 | 5008 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A
| 0 | 0 | 12033793 | 5140 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A
| 0 | 0 | 12033793 | 4962 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A
| 0 | 0 | 12033793 | 5192 | 0 | 0 |
|
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A
| 0 | 0 | 12033793 | 5049 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A
| 0 | 0 | 12601978 | 13991 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A
| 0 | 0 | 12601978 | 22485 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A
| 0 | 0 | 12601978 | 14052 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A
| 0 | 0 | 12601978 | 22540 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A
| 0 | 0 | 12601978 | 14096 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A
| 0 | 0 | 12601978 | 22589 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A
| 0 | 0 | 25205250 | 12843 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A
| 0 | 0 | 25205250 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A
| 0 | 0 | 12601978 | 12861 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A
| 0 | 0 | 12601978 | 21413 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A
| 0 | 0 | 50408579 | 12834 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A
| 0 | 0 | 50408579 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A
| 0 | 0 | 52510496 | 12890 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A
| 0 | 0 | 52510496 | 21413 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A
| 0 | 0 | 25205103 | 12832 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A
| 0 | 0 | 25205103 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A
| 0 | 0 | 1591058 | 50 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A
| 0 | 0 | 1591058 | 8585 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A
| 0 | 0 | 12601978 | 13760 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A
| 0 | 0 | 12601978 | 22248 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A
| 0 | 0 | 50408579 | 13786 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A
| 0 | 0 | 50408579 | 22278 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A
| 0 | 0 | 25205250 | 13820 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A
| 0 | 0 | 25205250 | 22325 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A
| 0 | 0 | 52510496 | 12841 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A
| 0 | 0 | 52510496 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A
| 0 | 0 | 1591058 | 13428 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A
| 0 | 0 | 1591058 | 21456 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A
| 0 | 0 | 25205103 | 13915 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A
| 0 | 0 | 25205103 | 22404 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A
| 0 | 0 | 1591058 | 12783 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A
| 0 | 0 | 1591058 | 21346 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A
| 0 | 0 | 25205250 | 12787 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A
| 0 | 0 | 25205250 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A
| 0 | 0 | 12601978 | 12811 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A
| 0 | 0 | 12601978 | 21413 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A
| 0 | 0 | 50408579 | 12787 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A
| 0 | 0 | 50408579 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A
| 0 | 0 | 52510496 | 12839 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A
| 0 | 0 | 52510496 | 21413 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A
| 0 | 0 | 25205103 | 12780 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A
| 0 | 0 | 25205103 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A
| 0 | 0 | 1591058 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A
| 0 | 0 | 52510496 | 27 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A
| 0 | 0 | 25205250 | 27 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A
| 0 | 0 | 25205250 | 2396 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A
| 0 | 0 | 12601978 | 8602 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A
| 0 | 0 | 50408579 | 21 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A
| 0 | 0 | 25205103 | 26 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A
| 0 | 0 | 25205103 | 2396 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A
| 0 | 0 | 12601978 | 12784 | 0 | 0 |
|
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A
| 0 | 0 | 12601978 | 21363 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A
| 0 | 0 | 12601978 | 13646 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A
| 0 | 0 | 12601978 | 1043 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A
| 0 | 0 | 12601978 | 13646 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A
| 0 | 0 | 12601978 | 1043 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A
| 0 | 0 | 50408579 | 12386 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A
| 0 | 0 | 50408579 | 992 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A
| 0 | 0 | 50408579 | 12386 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A
| 0 | 0 | 50408579 | 992 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOff_A
| 0 | 0 | 25205250 | 12434 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A
| 0 | 0 | 25205250 | 992 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOff_A
| 0 | 0 | 25205250 | 12434 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstNOn_A
| 0 | 0 | 25205250 | 992 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOff_A
| 0 | 0 | 25205103 | 12513 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstEnOn_A
| 0 | 0 | 25205103 | 1075 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOff_A
| 0 | 0 | 25205103 | 12513 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[3].RstNOn_A
| 0 | 0 | 25205103 | 1075 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOff_A
| 0 | 0 | 1591058 | 21019 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A
| 0 | 0 | 1591058 | 1086 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOff_A
| 0 | 0 | 1591058 | 21019 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstNOn_A
| 0 | 0 | 1591058 | 1086 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOff_A
| 0 | 0 | 12601978 | 13881 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A
| 0 | 0 | 12601978 | 1153 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOff_A
| 0 | 0 | 12601978 | 13881 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A
| 0 | 0 | 12601978 | 1153 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOff_A
| 0 | 0 | 12601978 | 13935 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A
| 0 | 0 | 12601978 | 1215 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOff_A
| 0 | 0 | 12601978 | 13935 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A
| 0 | 0 | 12601978 | 1215 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOff_A
| 0 | 0 | 12601978 | 13984 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A
| 0 | 0 | 12601978 | 1258 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOff_A
| 0 | 0 | 12601978 | 13984 | 0 | 0 |
|
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A
| 0 | 0 | 12601978 | 1258 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 12033793 | 1088311 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 12033793 | 7032697 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 12033793 | 7032697 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 12033793 | 1844373 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 12033793 | 7032697 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 12033793 | 7032697 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 12034413 | 487566 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 12033793 | 5216 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 12034413 | 792964 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 12034413 | 934186 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 12033793 | 5751 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 12034413 | 1088407 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 12034413 | 1844542 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 12034413 | 1088407 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 12034413 | 1844542 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 12034413 | 1844542 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 12034413 | 1844542 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 12033793 | 3244 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 12033793 | 2847 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_alert_info.CntStoreSlot_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_alert_info.CntWidth_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_cpu_info.CntStoreSlot_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_cpu_info.CntWidth_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A
| 0 | 0 | 12601978 | 7554617 | 0 | 0 |
|
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 12601978 | 7554617 | 0 | 0 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6388074 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22483 | 21978 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6383156 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22537 | 22032 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6390180 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22586 | 22081 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 27270159 | 0 | 0 |
|
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 50408579 | 26180281 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205250 | 13080019 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6513337 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6513337 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 27270460 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205103 | 13080250 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6374392 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22248 | 21743 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 50408579 | 25625981 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22273 | 21768 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205250 | 12828111 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22321 | 21816 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 26979538 | 0 | 0 |
|
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205103 | 12796108 | 0 | 0 |
|
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22400 | 21895 | 0 | 0 |
|
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21296 | 20791 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1591058 | 792406 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 22396 | 21891 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 27978642 | 0 | 0 |
|
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21296 | 20791 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 1591058 | 829708 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 50408579 | 26859820 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205250 | 13420071 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6683258 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6683258 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 27978286 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205103 | 13420178 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 52510496 | 31498831 | 0 | 0 |
|
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 50408579 | 30238002 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205250 | 15115297 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 7554617 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 25205103 | 15115304 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 8602 | 8097 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21413 | 20908 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A
| 0 | 0 | 12601978 | 6613168 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 505 | 505 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A
| 0 | 0 | 11182148 | 6482261 | 0 | 0 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 12033793 | 951714 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 12033793 | 951591 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 12033793 | 509333 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 620 | 620 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 12033793 | 442258 | 0 | 0 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0
| 0 | 0 | 21363 | 20858 | 0 | 0 |
|
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1
| 0 | 0 | 2662 | 2157 | 0 | 0 |
|