| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| T539 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.1335244832 | Oct 03 11:35:31 AM UTC 24 | Oct 03 11:36:06 AM UTC 24 | 7021835334 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3251281368 | Oct 03 11:35:56 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 2470968348 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2389591011 | Oct 03 11:35:47 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 4541112476 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3686446365 | Oct 03 11:35:52 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 7885042427 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2306293601 | Oct 03 11:35:56 AM UTC 24 | Oct 03 11:36:45 AM UTC 24 | 15760115839 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3578227133 | Oct 03 11:35:58 AM UTC 24 | Oct 03 11:36:00 AM UTC 24 | 95111536 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.832226859 | Oct 03 11:35:58 AM UTC 24 | Oct 03 11:36:00 AM UTC 24 | 84192884 ps | ||
| T68 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1638196950 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:01 AM UTC 24 | 151825597 ps | ||
| T69 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.931121121 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:01 AM UTC 24 | 108230499 ps | ||
| T70 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1331744411 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:01 AM UTC 24 | 108700556 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.856552544 | Oct 03 11:35:57 AM UTC 24 | Oct 03 11:36:01 AM UTC 24 | 263491277 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3129722461 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:01 AM UTC 24 | 134657137 ps | ||
| T113 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.141921521 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:02 AM UTC 24 | 91907982 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.677144202 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:02 AM UTC 24 | 101318366 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1083715861 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:03 AM UTC 24 | 248035274 ps | ||
| T78 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1701661082 | Oct 03 11:36:00 AM UTC 24 | Oct 03 11:36:03 AM UTC 24 | 208871696 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2074622089 | Oct 03 11:36:00 AM UTC 24 | Oct 03 11:36:03 AM UTC 24 | 149273140 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.208239492 | Oct 03 11:35:57 AM UTC 24 | Oct 03 11:36:03 AM UTC 24 | 778490969 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1649570187 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:04 AM UTC 24 | 103741993 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3080860553 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:04 AM UTC 24 | 805502327 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.3511224150 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:04 AM UTC 24 | 67272060 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.136186196 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:04 AM UTC 24 | 97412937 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.421846875 | Oct 03 11:36:01 AM UTC 24 | Oct 03 11:36:05 AM UTC 24 | 168910851 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4193244074 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:05 AM UTC 24 | 128870143 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3080583032 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:05 AM UTC 24 | 105234080 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1753140341 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:05 AM UTC 24 | 815159633 ps | ||
| T100 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.1145329352 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:06 AM UTC 24 | 86164462 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3417559360 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:06 AM UTC 24 | 99950843 ps | ||
| T88 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2113326120 | Oct 03 11:36:01 AM UTC 24 | Oct 03 11:36:06 AM UTC 24 | 953073008 ps | ||
| T116 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3858141187 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:06 AM UTC 24 | 281356894 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2602638818 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 207159888 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2306237063 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 83900176 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2629683494 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 132122547 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.2434762077 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 75745668 ps | ||
| T92 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3766125337 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:07 AM UTC 24 | 810370205 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3410284553 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:08 AM UTC 24 | 131231807 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.449802897 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:08 AM UTC 24 | 747780538 ps | ||
| T91 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2422205307 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:08 AM UTC 24 | 124867314 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.847844674 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:08 AM UTC 24 | 210278446 ps | ||
| T93 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2467576680 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 155317278 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3335331260 | Oct 03 11:36:06 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 94617308 ps | ||
| T124 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3394659752 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 800407498 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2366269376 | Oct 03 11:36:02 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 1189044036 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.3226999827 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 80938815 ps | ||
| T122 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2080737509 | Oct 03 11:36:06 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 261577688 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2216729394 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 142788024 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2829705115 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 95400123 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2217716002 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:09 AM UTC 24 | 193775313 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.309316897 | Oct 03 11:35:59 AM UTC 24 | Oct 03 11:36:10 AM UTC 24 | 1997722924 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2176388216 | Oct 03 11:36:03 AM UTC 24 | Oct 03 11:36:10 AM UTC 24 | 811709393 ps | ||
| T123 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3636737293 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:10 AM UTC 24 | 125913582 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.966704030 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:10 AM UTC 24 | 64488408 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1913312273 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:10 AM UTC 24 | 123872844 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2572324038 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:11 AM UTC 24 | 83413266 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2969194652 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:11 AM UTC 24 | 201655709 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2483977398 | Oct 03 11:36:07 AM UTC 24 | Oct 03 11:36:11 AM UTC 24 | 872538725 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.2591812463 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:11 AM UTC 24 | 150825673 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.604081544 | Oct 03 11:36:06 AM UTC 24 | Oct 03 11:36:11 AM UTC 24 | 924168718 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3909272423 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 64407691 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2510306199 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 483537486 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.483849525 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 107652823 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.307114583 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 64114513 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2201095019 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 78452319 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3469636470 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 125201920 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1027966587 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:12 AM UTC 24 | 221944349 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3663524273 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:13 AM UTC 24 | 393451662 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1175905508 | Oct 03 11:36:08 AM UTC 24 | Oct 03 11:36:13 AM UTC 24 | 862834326 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1257242910 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 62113944 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2062618245 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:13 AM UTC 24 | 531656043 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2703540458 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 74870756 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2261631948 | Oct 03 11:36:10 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 438995937 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.194664405 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 115782152 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2697134414 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 67066696 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1229799944 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 121911894 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3825879728 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:14 AM UTC 24 | 197737654 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1188481616 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:15 AM UTC 24 | 242193822 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1465982491 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:15 AM UTC 24 | 252749564 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3182150121 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:15 AM UTC 24 | 340499373 ps | ||
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| T584 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3479134686 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 172738887 ps | ||
| T585 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3793493151 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 798753076 ps | ||
| T586 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3700682911 | Oct 03 11:36:05 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 2030582191 ps | ||
| T587 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1266810666 | Oct 03 11:36:14 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 81664182 ps | ||
| T588 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.62936398 | Oct 03 11:36:12 AM UTC 24 | Oct 03 11:36:16 AM UTC 24 | 931947470 ps | ||
| T589 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1784755622 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 56496351 ps | ||
| T590 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.869657233 | Oct 03 11:36:14 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 108440863 ps | ||
| T591 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3048811017 | Oct 03 11:36:14 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 78022604 ps | ||
| T592 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2851192458 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 142500249 ps | ||
| T593 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.463050823 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 66579727 ps | ||
| T594 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2609723963 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 157158523 ps | ||
| T595 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1842453588 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:17 AM UTC 24 | 118189876 ps | ||
| T596 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.11995673 | Oct 03 11:36:14 AM UTC 24 | Oct 03 11:36:18 AM UTC 24 | 264989073 ps | ||
| T597 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1532316872 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:18 AM UTC 24 | 197743024 ps | ||
| T134 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.206653918 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:18 AM UTC 24 | 474665300 ps | ||
| T598 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3785229222 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:18 AM UTC 24 | 220817814 ps | ||
| T599 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1669137209 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:18 AM UTC 24 | 557776944 ps | ||
| T600 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1290193780 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 74151776 ps | ||
| T125 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1992037137 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 1028917374 ps | ||
| T601 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2670023879 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 64195883 ps | ||
| T602 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1277846051 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 195064625 ps | ||
| T603 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2196854290 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:19 AM UTC 24 | 153115491 ps | ||
| T604 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3560763365 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 76240405 ps | ||
| T605 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1440137516 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 205522885 ps | ||
| T606 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1463714436 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 173993070 ps | ||
| T607 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2117955576 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 90278298 ps | ||
| T608 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.608036028 | Oct 03 11:36:15 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 630322823 ps | ||
| T609 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3910462650 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 175900799 ps | ||
| T610 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2279008232 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 495293720 ps | ||
| T611 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2395852686 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:20 AM UTC 24 | 262110682 ps | ||
| T612 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3321533640 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:21 AM UTC 24 | 901784274 ps | ||
| T613 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1927834018 | Oct 03 11:36:17 AM UTC 24 | Oct 03 11:36:22 AM UTC 24 | 466157126 ps | ||
| T614 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1482143612 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:23 AM UTC 24 | 66329822 ps | ||
| T615 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1133834405 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 60066458 ps | ||
| T616 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1677104654 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 102072187 ps | ||
| T617 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.387542757 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 132694718 ps | ||
| T618 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4006571772 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 96032649 ps | ||
| T619 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3250414048 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 106665514 ps | ||
| T620 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.140492201 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:24 AM UTC 24 | 175871806 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1836042618 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:25 AM UTC 24 | 940278929 ps | ||
| T126 | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1623659124 | Oct 03 11:36:21 AM UTC 24 | Oct 03 11:36:26 AM UTC 24 | 946881559 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.973852530 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 122582106 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 11:32:18 AM UTC 24 |
| Finished | Oct 03 11:32:21 AM UTC 24 |
| Peak memory | 210752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973852530 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.973852530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.2237134479 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 369660748 ps |
| CPU time | 3.51 seconds |
| Started | Oct 03 11:32:28 AM UTC 24 |
| Finished | Oct 03 11:32:33 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237134479 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.2237134479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.1269548277 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1451917061 ps |
| CPU time | 8.28 seconds |
| Started | Oct 03 11:32:23 AM UTC 24 |
| Finished | Oct 03 11:32:32 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269548277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.1269548277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.1701661082 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 208871696 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 11:36:00 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1701661082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_w ith_rand_reset.1701661082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm.2969117645 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 8425014753 ps |
| CPU time | 18.48 seconds |
| Started | Oct 03 11:32:34 AM UTC 24 |
| Finished | Oct 03 11:32:53 AM UTC 24 |
| Peak memory | 244336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969117645 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.2969117645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2686900015 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1961955299 ps |
| CPU time | 10.16 seconds |
| Started | Oct 03 11:32:32 AM UTC 24 |
| Finished | Oct 03 11:32:44 AM UTC 24 |
| Peak memory | 244420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686900015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.2686900015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.1831425781 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 6301287241 ps |
| CPU time | 33.62 seconds |
| Started | Oct 03 11:32:34 AM UTC 24 |
| Finished | Oct 03 11:33:09 AM UTC 24 |
| Peak memory | 220336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831425781 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.1831425781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.3080860553 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 805502327 ps |
| CPU time | 3.89 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:04 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080860553 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.3080860553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_errors.3663524273 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 393451662 ps |
| CPU time | 3.2 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:13 AM UTC 24 |
| Peak memory | 221796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663524273 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.3663524273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.1146516239 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2439685110 ps |
| CPU time | 9.97 seconds |
| Started | Oct 03 11:32:51 AM UTC 24 |
| Finished | Oct 03 11:33:02 AM UTC 24 |
| Peak memory | 244544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146516239 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1146516239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2684781900 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 182577646 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 11:32:31 AM UTC 24 |
| Finished | Oct 03 11:32:34 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684781900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.2684781900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.3511665477 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 65829406 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 11:32:34 AM UTC 24 |
| Finished | Oct 03 11:32:36 AM UTC 24 |
| Peak memory | 209964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511665477 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3511665477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.1470447137 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 150985657 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 11:32:25 AM UTC 24 |
| Finished | Oct 03 11:32:27 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470447137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.1470447137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.3394659752 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 800407498 ps |
| CPU time | 2.93 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394659752 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.3394659752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_cnsty.891572112 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1272958234 ps |
| CPU time | 6.42 seconds |
| Started | Oct 03 11:33:53 AM UTC 24 |
| Finished | Oct 03 11:34:00 AM UTC 24 |
| Peak memory | 243724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891572112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.891572112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.208239492 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 778490969 ps |
| CPU time | 4.73 seconds |
| Started | Oct 03 11:35:57 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208239492 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.208239492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.1331744411 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 108700556 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331744411 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.1331744411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1319155262 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 84901393 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:32:22 AM UTC 24 |
| Finished | Oct 03 11:32:24 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319155262 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.1319155262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.1083715861 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 248035274 ps |
| CPU time | 2.86 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083715861 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1083715861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.764606417 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3193635179 ps |
| CPU time | 18.06 seconds |
| Started | Oct 03 11:32:39 AM UTC 24 |
| Finished | Oct 03 11:32:59 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764606417 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.764606417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.931121121 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 108230499 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931121121 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.931121121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.309316897 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1997722924 ps |
| CPU time | 9.85 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:10 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309316897 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.309316897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.3578227133 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 95111536 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 11:35:58 AM UTC 24 |
| Finished | Oct 03 11:36:00 AM UTC 24 |
| Peak memory | 208032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578227133 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.3578227133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.3129722461 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 134657137 ps |
| CPU time | 1.45 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3129722461 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_w ith_rand_reset.3129722461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.832226859 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 84192884 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:35:58 AM UTC 24 |
| Finished | Oct 03 11:36:00 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832226859 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.832226859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.856552544 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 263491277 ps |
| CPU time | 2.87 seconds |
| Started | Oct 03 11:35:57 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 219824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856552544 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.856552544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.677144202 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 101318366 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:02 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677144202 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.677144202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.1753140341 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 815159633 ps |
| CPU time | 5.22 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:05 AM UTC 24 |
| Peak memory | 208852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753140341 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.1753140341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.1638196950 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 151825597 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638196950 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.1638196950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.141921521 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 91907982 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:35:59 AM UTC 24 |
| Finished | Oct 03 11:36:02 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141921521 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.141921521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2074622089 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 149273140 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:36:00 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074622089 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.2074622089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.194664405 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 115782152 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=194664405 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_w ith_rand_reset.194664405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.2703540458 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 74870756 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 207696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703540458 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.2703540458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3825879728 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 197737654 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 207788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825879728 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_same_csr_outstanding.3825879728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.1465982491 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 252749564 ps |
| CPU time | 2.64 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:15 AM UTC 24 |
| Peak memory | 221800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465982491 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.1465982491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.62936398 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 931947470 ps |
| CPU time | 3.83 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62936398 -assert nopostproc +UVM_TESTNAM E=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.62936398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.1229799944 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 121911894 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 207828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1229799944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_mem_rw_ with_rand_reset.1229799944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2697134414 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 67066696 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697134414 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2697134414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1188481616 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 242193822 ps |
| CPU time | 2.25 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:15 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188481616 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_same_csr_outstanding.1188481616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3182150121 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 340499373 ps |
| CPU time | 2.55 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:15 AM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182150121 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.3182150121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.608451911 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 829455315 ps |
| CPU time | 2.87 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608451911 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.608451911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.869657233 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 108440863 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:36:14 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=869657233 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_w ith_rand_reset.869657233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.1266810666 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 81664182 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:36:14 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266810666 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.1266810666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.3048811017 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 78022604 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:36:14 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048811017 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_same_csr_outstanding.3048811017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.3479134686 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 172738887 ps |
| CPU time | 2.72 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 217704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479134686 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3479134686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3793493151 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 798753076 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 11:36:12 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793493151 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.3793493151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.1842453588 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 118189876 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1842453588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_ with_rand_reset.1842453588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.1257242910 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 62113944 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257242910 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.1257242910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2851192458 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 142500249 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851192458 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_same_csr_outstanding.2851192458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.11995673 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 264989073 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 11:36:14 AM UTC 24 |
| Finished | Oct 03 11:36:18 AM UTC 24 |
| Peak memory | 217676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11995673 -assert nopostproc +UVM_TESTNAME=rstmgr_bas e_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.11995673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.206653918 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 474665300 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:18 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206653918 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.206653918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.1532316872 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 197743024 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:18 AM UTC 24 |
| Peak memory | 207828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1532316872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_ with_rand_reset.1532316872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.463050823 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 66579727 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463050823 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.463050823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.2609723963 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 157158523 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609723963 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_same_csr_outstanding.2609723963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_errors.3785229222 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 220817814 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:18 AM UTC 24 |
| Peak memory | 217912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785229222 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3785229222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.1992037137 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1028917374 ps |
| CPU time | 3.37 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 208788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992037137 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1992037137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.1277846051 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 195064625 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 217620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1277846051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_ with_rand_reset.1277846051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.1784755622 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 56496351 ps |
| CPU time | 0.81 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:17 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784755622 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.1784755622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.1440137516 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 205522885 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 207744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440137516 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_same_csr_outstanding.1440137516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.608036028 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 630322823 ps |
| CPU time | 3.93 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 217696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608036028 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.608036028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.1669137209 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 557776944 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:36:15 AM UTC 24 |
| Finished | Oct 03 11:36:18 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669137209 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.1669137209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.3910462650 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 175900799 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3910462650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_ with_rand_reset.3910462650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.1290193780 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 74151776 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290193780 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.1290193780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.2196854290 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 153115491 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196854290 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_same_csr_outstanding.2196854290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.2395852686 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 262110682 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 221928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395852686 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2395852686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.3321533640 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 901784274 ps |
| CPU time | 3.23 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:21 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321533640 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.3321533640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.1463714436 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 173993070 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1463714436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_mem_rw_ with_rand_reset.1463714436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.2670023879 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 64195883 ps |
| CPU time | 0.98 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670023879 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2670023879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.3560763365 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 76240405 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 207836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560763365 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_same_csr_outstanding.3560763365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.2117955576 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 90278298 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117955576 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2117955576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2279008232 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 495293720 ps |
| CPU time | 1.92 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:20 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279008232 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.2279008232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.140492201 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 175871806 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=140492201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_w ith_rand_reset.140492201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.1482143612 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 66329822 ps |
| CPU time | 0.81 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:23 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482143612 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.1482143612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4006571772 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 96032649 ps |
| CPU time | 1.73 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 207792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006571772 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_same_csr_outstanding.4006571772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.1927834018 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 466157126 ps |
| CPU time | 3.67 seconds |
| Started | Oct 03 11:36:17 AM UTC 24 |
| Finished | Oct 03 11:36:22 AM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927834018 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1927834018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1836042618 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 940278929 ps |
| CPU time | 3.15 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:25 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836042618 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.1836042618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.3250414048 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 106665514 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3250414048 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_ with_rand_reset.3250414048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.1133834405 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 60066458 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133834405 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.1133834405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.387542757 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 132694718 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387542757 -assert nopostproc +U VM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_same_csr_outstanding.387542757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.1677104654 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 102072187 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:24 AM UTC 24 |
| Peak memory | 217588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677104654 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1677104654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.1623659124 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 946881559 ps |
| CPU time | 3.21 seconds |
| Started | Oct 03 11:36:21 AM UTC 24 |
| Finished | Oct 03 11:36:26 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623659124 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.1623659124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3080583032 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 105234080 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:05 AM UTC 24 |
| Peak memory | 208844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080583032 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3080583032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.2366269376 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1189044036 ps |
| CPU time | 6.13 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366269376 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.2366269376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.1649570187 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 103741993 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:04 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649570187 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.1649570187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.136186196 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 97412937 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:04 AM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=136186196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_wi th_rand_reset.136186196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.3511224150 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 67272060 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:04 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511224150 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.3511224150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.4193244074 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 128870143 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:05 AM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193244074 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.4193244074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.421846875 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 168910851 ps |
| CPU time | 3.17 seconds |
| Started | Oct 03 11:36:01 AM UTC 24 |
| Finished | Oct 03 11:36:05 AM UTC 24 |
| Peak memory | 208896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421846875 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.421846875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2113326120 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 953073008 ps |
| CPU time | 4.09 seconds |
| Started | Oct 03 11:36:01 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 208836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113326120 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.2113326120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_aliasing.2602638818 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 207159888 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 208724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602638818 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.2602638818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.2176388216 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 811709393 ps |
| CPU time | 5.59 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:10 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176388216 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.2176388216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3417559360 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 99950843 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417559360 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3417559360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.2629683494 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 132122547 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2629683494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_w ith_rand_reset.2629683494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.1145329352 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 86164462 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145329352 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1145329352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.3858141187 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 281356894 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 207724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858141187 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.3858141187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_errors.449802897 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 747780538 ps |
| CPU time | 4.78 seconds |
| Started | Oct 03 11:36:02 AM UTC 24 |
| Finished | Oct 03 11:36:08 AM UTC 24 |
| Peak memory | 221908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449802897 -assert nopostproc +UVM_TESTNAME=rstmgr_ba se_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/r stmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.449802897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_tl_intg_err.3766125337 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 810370205 ps |
| CPU time | 3.02 seconds |
| Started | Oct 03 11:36:03 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766125337 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.3766125337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.847844674 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 210278446 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:08 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847844674 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.847844674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.3700682911 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2030582191 ps |
| CPU time | 9.85 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:16 AM UTC 24 |
| Peak memory | 208908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700682911 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.3700682911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.2306237063 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 83900176 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 207768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306237063 -assert nopostproc +UVM_TESTNAME =rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.2306237063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.2422205307 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 124867314 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:08 AM UTC 24 |
| Peak memory | 217560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2422205307 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_w ith_rand_reset.2422205307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_rw.2434762077 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 75745668 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434762077 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.2434762077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.3410284553 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 131231807 ps |
| CPU time | 1.55 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:08 AM UTC 24 |
| Peak memory | 207708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410284553 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.3410284553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_errors.2467576680 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 155317278 ps |
| CPU time | 2.8 seconds |
| Started | Oct 03 11:36:05 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 221876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467576680 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2467576680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.2217716002 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 193775313 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2217716002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_w ith_rand_reset.2217716002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_csr_rw.3335331260 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 94617308 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 11:36:06 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335331260 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.3335331260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.2216729394 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 142788024 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216729394 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_same_csr_outstanding.2216729394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_errors.2080737509 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 261577688 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 11:36:06 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 207892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080737509 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2080737509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/5.rstmgr_tl_intg_err.604081544 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 924168718 ps |
| CPU time | 3.92 seconds |
| Started | Oct 03 11:36:06 AM UTC 24 |
| Finished | Oct 03 11:36:11 AM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604081544 -assert nopostproc +UVM_TESTNA ME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.604081544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1913312273 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 123872844 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:10 AM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1913312273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_w ith_rand_reset.1913312273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_csr_rw.3226999827 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 80938815 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 207640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226999827 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.3226999827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.2829705115 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 95400123 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 207764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829705115 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_same_csr_outstanding.2829705115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_errors.3636737293 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 125913582 ps |
| CPU time | 2.65 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:10 AM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636737293 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.3636737293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.2483977398 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 872538725 ps |
| CPU time | 3.52 seconds |
| Started | Oct 03 11:36:07 AM UTC 24 |
| Finished | Oct 03 11:36:11 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483977398 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.2483977398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.2969194652 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 201655709 ps |
| CPU time | 1.4 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:11 AM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2969194652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_w ith_rand_reset.2969194652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_csr_rw.966704030 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 64488408 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:10 AM UTC 24 |
| Peak memory | 207216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966704030 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.966704030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.2572324038 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 83413266 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:11 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572324038 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_same_csr_outstanding.2572324038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_errors.2591812463 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 150825673 ps |
| CPU time | 2.1 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:11 AM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591812463 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2591812463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1175905508 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 862834326 ps |
| CPU time | 3.84 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:13 AM UTC 24 |
| Peak memory | 208828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175905508 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.1175905508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.3469636470 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 125201920 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 217556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3469636470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_w ith_rand_reset.3469636470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_csr_rw.3909272423 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 64407691 ps |
| CPU time | 1.02 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909272423 -assert nopostproc +UVM_TESTNAME=rstmg r_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3909272423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.1027966587 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 221944349 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027966587 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_same_csr_outstanding.1027966587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/8.rstmgr_tl_intg_err.2510306199 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 483537486 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 11:36:08 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 208752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510306199 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.2510306199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.483849525 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 107652823 ps |
| CPU time | 0.96 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 207704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=483849525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_wi th_rand_reset.483849525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_csr_rw.307114583 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 64114513 ps |
| CPU time | 1.13 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 207700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307114583 -assert nopostproc +UVM_TESTNAME=rstmgr _base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 2/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.307114583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.2201095019 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 78452319 ps |
| CPU time | 1.11 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:12 AM UTC 24 |
| Peak memory | 207772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201095019 -assert nopostproc + UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_same_csr_outstanding.2201095019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_errors.2261631948 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 438995937 ps |
| CPU time | 2.94 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:14 AM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261631948 -assert nopostproc +UVM_TESTNAME=rstmgr_b ase_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/ rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.2261631948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2062618245 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 531656043 ps |
| CPU time | 2.41 seconds |
| Started | Oct 03 11:36:10 AM UTC 24 |
| Finished | Oct 03 11:36:13 AM UTC 24 |
| Peak memory | 208772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062618245 -assert nopostproc +UVM_TESTN AME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.2062618245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.147447969 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 303534355 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:32:32 AM UTC 24 |
| Finished | Oct 03 11:32:35 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147447969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.147447969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.1060173412 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 63148511 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 11:32:41 AM UTC 24 |
| Finished | Oct 03 11:32:43 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060173412 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1060173412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.285674841 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1276035401 ps |
| CPU time | 9.02 seconds |
| Started | Oct 03 11:32:38 AM UTC 24 |
| Finished | Oct 03 11:32:48 AM UTC 24 |
| Peak memory | 243584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285674841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.285674841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.947548617 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 301693866 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 11:32:38 AM UTC 24 |
| Finished | Oct 03 11:32:41 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947548617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.947548617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.2377086475 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 173524307 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:32:35 AM UTC 24 |
| Finished | Oct 03 11:32:37 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377086475 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.2377086475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.1232832069 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1101946880 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 11:32:35 AM UTC 24 |
| Finished | Oct 03 11:32:43 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232832069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.1232832069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.3684235567 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8297262304 ps |
| CPU time | 15.42 seconds |
| Started | Oct 03 11:32:41 AM UTC 24 |
| Finished | Oct 03 11:32:57 AM UTC 24 |
| Peak memory | 243616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684235567 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.3684235567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2964104802 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 178034114 ps |
| CPU time | 2.07 seconds |
| Started | Oct 03 11:32:37 AM UTC 24 |
| Finished | Oct 03 11:32:40 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964104802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2964104802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.895076801 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 221455843 ps |
| CPU time | 2.27 seconds |
| Started | Oct 03 11:32:35 AM UTC 24 |
| Finished | Oct 03 11:32:38 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895076801 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.895076801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.455547019 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 132200928 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 11:32:36 AM UTC 24 |
| Finished | Oct 03 11:32:40 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455547019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.455547019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.1404802376 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 186661447 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:32:35 AM UTC 24 |
| Finished | Oct 03 11:32:38 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404802376 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.1404802376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_alert_test.2524956451 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 56495716 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:33:34 AM UTC 24 |
| Finished | Oct 03 11:33:37 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524956451 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2524956451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_cnsty.1071432377 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2442084719 ps |
| CPU time | 12.32 seconds |
| Started | Oct 03 11:33:33 AM UTC 24 |
| Finished | Oct 03 11:33:46 AM UTC 24 |
| Peak memory | 244472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071432377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.1071432377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_leaf_rst_shadow_attack.499015521 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 301998252 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 11:33:33 AM UTC 24 |
| Finished | Oct 03 11:33:36 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499015521 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.499015521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_por_stretcher.1630631604 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 165443912 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:33:29 AM UTC 24 |
| Finished | Oct 03 11:33:31 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630631604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.1630631604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_reset.2341525184 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 886909314 ps |
| CPU time | 5.88 seconds |
| Started | Oct 03 11:33:29 AM UTC 24 |
| Finished | Oct 03 11:33:36 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341525184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.2341525184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.575140373 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 114527937 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:33:31 AM UTC 24 |
| Finished | Oct 03 11:33:34 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575140373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.575140373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_smoke.2669712863 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 200817993 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 11:33:28 AM UTC 24 |
| Finished | Oct 03 11:33:31 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669712863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.2669712863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_stress_all.455693093 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 14733229973 ps |
| CPU time | 54.06 seconds |
| Started | Oct 03 11:33:33 AM UTC 24 |
| Finished | Oct 03 11:34:29 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455693093 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.455693093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst.74781002 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 480790409 ps |
| CPU time | 3.61 seconds |
| Started | Oct 03 11:33:30 AM UTC 24 |
| Finished | Oct 03 11:33:35 AM UTC 24 |
| Peak memory | 220208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74781002 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.74781002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/10.rstmgr_sw_rst_reset_race.693132394 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 210454538 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:33:30 AM UTC 24 |
| Finished | Oct 03 11:33:33 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693132394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.693132394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/10.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_alert_test.2323642048 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 68773844 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:33:39 AM UTC 24 |
| Finished | Oct 03 11:33:41 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323642048 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.2323642048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_cnsty.3639233806 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2438594716 ps |
| CPU time | 13.01 seconds |
| Started | Oct 03 11:33:38 AM UTC 24 |
| Finished | Oct 03 11:33:52 AM UTC 24 |
| Peak memory | 243716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639233806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3639233806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_leaf_rst_shadow_attack.1952217282 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 301984646 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:33:38 AM UTC 24 |
| Finished | Oct 03 11:33:41 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952217282 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.1952217282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_por_stretcher.2357919951 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 107120156 ps |
| CPU time | 0.95 seconds |
| Started | Oct 03 11:33:34 AM UTC 24 |
| Finished | Oct 03 11:33:36 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357919951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2357919951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_reset.1814055949 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1753121028 ps |
| CPU time | 8.95 seconds |
| Started | Oct 03 11:33:35 AM UTC 24 |
| Finished | Oct 03 11:33:45 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814055949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.1814055949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2319620443 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 176914516 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:33:36 AM UTC 24 |
| Finished | Oct 03 11:33:39 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319620443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2319620443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_smoke.4179107864 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 117823665 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 11:33:34 AM UTC 24 |
| Finished | Oct 03 11:33:37 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179107864 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.4179107864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_stress_all.66311891 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2807012975 ps |
| CPU time | 13.01 seconds |
| Started | Oct 03 11:33:38 AM UTC 24 |
| Finished | Oct 03 11:33:52 AM UTC 24 |
| Peak memory | 220592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66311891 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.66311891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst.296742076 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 426911667 ps |
| CPU time | 3.78 seconds |
| Started | Oct 03 11:33:36 AM UTC 24 |
| Finished | Oct 03 11:33:42 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296742076 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.296742076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/11.rstmgr_sw_rst_reset_race.608803958 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 99912639 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:33:36 AM UTC 24 |
| Finished | Oct 03 11:33:39 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608803958 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.608803958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/11.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_alert_test.2685230497 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 76904721 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:33:45 AM UTC 24 |
| Finished | Oct 03 11:33:47 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685230497 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2685230497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_cnsty.1483444695 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1263420099 ps |
| CPU time | 8.84 seconds |
| Started | Oct 03 11:33:42 AM UTC 24 |
| Finished | Oct 03 11:33:52 AM UTC 24 |
| Peak memory | 243720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483444695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.1483444695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_leaf_rst_shadow_attack.2726417862 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 301570982 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 11:33:43 AM UTC 24 |
| Finished | Oct 03 11:33:46 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726417862 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.2726417862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_por_stretcher.3264657423 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 158522811 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:33:40 AM UTC 24 |
| Finished | Oct 03 11:33:42 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264657423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.3264657423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.4101737207 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1291579170 ps |
| CPU time | 9.66 seconds |
| Started | Oct 03 11:33:40 AM UTC 24 |
| Finished | Oct 03 11:33:51 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101737207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.4101737207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3878696514 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 180529362 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:33:42 AM UTC 24 |
| Finished | Oct 03 11:33:45 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878696514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3878696514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_smoke.3967989688 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 202539297 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:33:40 AM UTC 24 |
| Finished | Oct 03 11:33:43 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967989688 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.3967989688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_stress_all.592421913 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 5837370911 ps |
| CPU time | 23.2 seconds |
| Started | Oct 03 11:33:44 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 211604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592421913 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.592421913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst.3776262111 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 134613662 ps |
| CPU time | 2.44 seconds |
| Started | Oct 03 11:33:41 AM UTC 24 |
| Finished | Oct 03 11:33:45 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776262111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.3776262111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/12.rstmgr_sw_rst_reset_race.3208447440 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 210490995 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 11:33:40 AM UTC 24 |
| Finished | Oct 03 11:33:43 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208447440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.3208447440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/12.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_alert_test.1312220616 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 67446042 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:33:50 AM UTC 24 |
| Finished | Oct 03 11:33:53 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312220616 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.1312220616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_cnsty.3585138623 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1265132213 ps |
| CPU time | 7.61 seconds |
| Started | Oct 03 11:33:48 AM UTC 24 |
| Finished | Oct 03 11:33:57 AM UTC 24 |
| Peak memory | 243440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585138623 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.3585138623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_leaf_rst_shadow_attack.1693983285 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 301367630 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 11:33:49 AM UTC 24 |
| Finished | Oct 03 11:33:52 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693983285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.1693983285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_por_stretcher.2801307848 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 156407175 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:33:46 AM UTC 24 |
| Finished | Oct 03 11:33:48 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801307848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.2801307848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_reset.476131866 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1828297234 ps |
| CPU time | 10.69 seconds |
| Started | Oct 03 11:33:47 AM UTC 24 |
| Finished | Oct 03 11:33:59 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476131866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.476131866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2875373379 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 181247466 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:33:48 AM UTC 24 |
| Finished | Oct 03 11:33:51 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875373379 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2875373379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_smoke.2235976263 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 116653635 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:33:46 AM UTC 24 |
| Finished | Oct 03 11:33:49 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235976263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.2235976263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_stress_all.2899291813 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 11955338529 ps |
| CPU time | 49.96 seconds |
| Started | Oct 03 11:33:49 AM UTC 24 |
| Finished | Oct 03 11:34:41 AM UTC 24 |
| Peak memory | 220528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899291813 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.2899291813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst.1126816286 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 136831200 ps |
| CPU time | 2.31 seconds |
| Started | Oct 03 11:33:47 AM UTC 24 |
| Finished | Oct 03 11:33:50 AM UTC 24 |
| Peak memory | 220256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126816286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.1126816286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/13.rstmgr_sw_rst_reset_race.2095847213 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 144696564 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 11:33:47 AM UTC 24 |
| Finished | Oct 03 11:33:49 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095847213 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.2095847213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/13.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_alert_test.4242670032 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 63857271 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:33:54 AM UTC 24 |
| Finished | Oct 03 11:33:56 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242670032 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.4242670032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_leaf_rst_shadow_attack.246010873 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 302282751 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:33:53 AM UTC 24 |
| Finished | Oct 03 11:33:56 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246010873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.246010873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_por_stretcher.1044105912 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 78163813 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:33:52 AM UTC 24 |
| Finished | Oct 03 11:33:54 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044105912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.1044105912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_reset.1124066703 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1958549733 ps |
| CPU time | 7.15 seconds |
| Started | Oct 03 11:33:52 AM UTC 24 |
| Finished | Oct 03 11:34:00 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124066703 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.1124066703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.1459334306 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 113825951 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:33:53 AM UTC 24 |
| Finished | Oct 03 11:33:55 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459334306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.1459334306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_smoke.879351100 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 113152408 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 11:33:51 AM UTC 24 |
| Finished | Oct 03 11:33:53 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879351100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.879351100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_stress_all.4187995197 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 210566400 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:33:54 AM UTC 24 |
| Finished | Oct 03 11:33:57 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187995197 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.4187995197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst.1821846186 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 120650789 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:33:53 AM UTC 24 |
| Finished | Oct 03 11:33:56 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821846186 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.1821846186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/14.rstmgr_sw_rst_reset_race.2905449087 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 215955589 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 11:33:52 AM UTC 24 |
| Finished | Oct 03 11:33:55 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905449087 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.2905449087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/14.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_alert_test.2774578133 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 61987118 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:33:58 AM UTC 24 |
| Finished | Oct 03 11:34:00 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774578133 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.2774578133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_cnsty.4152468641 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1272708101 ps |
| CPU time | 5.95 seconds |
| Started | Oct 03 11:33:57 AM UTC 24 |
| Finished | Oct 03 11:34:04 AM UTC 24 |
| Peak memory | 244408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152468641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.4152468641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_leaf_rst_shadow_attack.1025708886 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 301276665 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 11:33:58 AM UTC 24 |
| Finished | Oct 03 11:34:01 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025708886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.1025708886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_por_stretcher.529363944 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 176451010 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 11:33:55 AM UTC 24 |
| Finished | Oct 03 11:33:58 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529363944 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.529363944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_reset.2389543121 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 724238798 ps |
| CPU time | 4.41 seconds |
| Started | Oct 03 11:33:55 AM UTC 24 |
| Finished | Oct 03 11:34:01 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389543121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2389543121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2565575745 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 144483194 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:33:57 AM UTC 24 |
| Finished | Oct 03 11:33:59 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565575745 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2565575745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_smoke.449277301 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 193069854 ps |
| CPU time | 2.18 seconds |
| Started | Oct 03 11:33:55 AM UTC 24 |
| Finished | Oct 03 11:33:59 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449277301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.449277301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_stress_all.1529158705 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5628155091 ps |
| CPU time | 27.66 seconds |
| Started | Oct 03 11:33:58 AM UTC 24 |
| Finished | Oct 03 11:34:27 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529158705 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.1529158705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst.2110483860 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 122244810 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 11:33:57 AM UTC 24 |
| Finished | Oct 03 11:34:00 AM UTC 24 |
| Peak memory | 220304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110483860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2110483860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/15.rstmgr_sw_rst_reset_race.2789740499 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 153816842 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:33:57 AM UTC 24 |
| Finished | Oct 03 11:33:59 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789740499 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.2789740499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/15.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_alert_test.783704606 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 65946703 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:34:02 AM UTC 24 |
| Finished | Oct 03 11:34:04 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783704606 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.783704606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_cnsty.3779318827 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1264708838 ps |
| CPU time | 6.45 seconds |
| Started | Oct 03 11:34:01 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 244512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779318827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3779318827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_leaf_rst_shadow_attack.332387311 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 301492638 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 11:34:01 AM UTC 24 |
| Finished | Oct 03 11:34:04 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332387311 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.332387311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_por_stretcher.2051915280 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 85071124 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:33:59 AM UTC 24 |
| Finished | Oct 03 11:34:01 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051915280 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.2051915280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_reset.1900235542 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1096500764 ps |
| CPU time | 5.6 seconds |
| Started | Oct 03 11:33:59 AM UTC 24 |
| Finished | Oct 03 11:34:06 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900235542 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.1900235542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.1352462172 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 96199476 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:34:01 AM UTC 24 |
| Finished | Oct 03 11:34:03 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352462172 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.1352462172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_smoke.3756452537 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 126903943 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 11:33:59 AM UTC 24 |
| Finished | Oct 03 11:34:02 AM UTC 24 |
| Peak memory | 208940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756452537 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.3756452537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_stress_all.3274155675 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 5242743416 ps |
| CPU time | 30.74 seconds |
| Started | Oct 03 11:34:01 AM UTC 24 |
| Finished | Oct 03 11:34:33 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274155675 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.3274155675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst.2736020621 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 506085303 ps |
| CPU time | 4.63 seconds |
| Started | Oct 03 11:33:59 AM UTC 24 |
| Finished | Oct 03 11:34:05 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736020621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.2736020621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/16.rstmgr_sw_rst_reset_race.3335487799 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 143107815 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 11:33:59 AM UTC 24 |
| Finished | Oct 03 11:34:02 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335487799 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.3335487799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/16.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_alert_test.2838400598 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 65874423 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:34:06 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838400598 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.2838400598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_cnsty.944685507 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1279089056 ps |
| CPU time | 5.66 seconds |
| Started | Oct 03 11:34:05 AM UTC 24 |
| Finished | Oct 03 11:34:11 AM UTC 24 |
| Peak memory | 244512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944685507 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.944685507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_leaf_rst_shadow_attack.3823936154 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 302455978 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:34:05 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823936154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.3823936154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_por_stretcher.3934391888 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 180902665 ps |
| CPU time | 1.48 seconds |
| Started | Oct 03 11:34:02 AM UTC 24 |
| Finished | Oct 03 11:34:05 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934391888 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3934391888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_reset.1875959527 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 686419594 ps |
| CPU time | 4.51 seconds |
| Started | Oct 03 11:34:02 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875959527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.1875959527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.3645203095 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 106195593 ps |
| CPU time | 1.44 seconds |
| Started | Oct 03 11:34:04 AM UTC 24 |
| Finished | Oct 03 11:34:07 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645203095 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.3645203095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_smoke.4007940514 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 203649544 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:34:02 AM UTC 24 |
| Finished | Oct 03 11:34:05 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007940514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4007940514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_stress_all.1646329944 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 130824081 ps |
| CPU time | 1.61 seconds |
| Started | Oct 03 11:34:06 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646329944 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.1646329944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst.559027148 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 132111482 ps |
| CPU time | 2.52 seconds |
| Started | Oct 03 11:34:03 AM UTC 24 |
| Finished | Oct 03 11:34:07 AM UTC 24 |
| Peak memory | 220276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559027148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.559027148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/17.rstmgr_sw_rst_reset_race.1885648740 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 89449258 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:34:03 AM UTC 24 |
| Finished | Oct 03 11:34:06 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885648740 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.1885648740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/17.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_alert_test.1951008732 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 75161366 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:34:09 AM UTC 24 |
| Finished | Oct 03 11:34:11 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951008732 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.1951008732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_cnsty.2662478807 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1277825259 ps |
| CPU time | 5.58 seconds |
| Started | Oct 03 11:34:08 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 243664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662478807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2662478807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_leaf_rst_shadow_attack.1016906443 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 301449420 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 11:34:09 AM UTC 24 |
| Finished | Oct 03 11:34:11 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016906443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.1016906443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_por_stretcher.1066631926 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 118831510 ps |
| CPU time | 1.25 seconds |
| Started | Oct 03 11:34:06 AM UTC 24 |
| Finished | Oct 03 11:34:08 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066631926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1066631926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_reset.1657700286 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 766781075 ps |
| CPU time | 6.3 seconds |
| Started | Oct 03 11:34:07 AM UTC 24 |
| Finished | Oct 03 11:34:14 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657700286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.1657700286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.2708061156 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 142995088 ps |
| CPU time | 1.72 seconds |
| Started | Oct 03 11:34:08 AM UTC 24 |
| Finished | Oct 03 11:34:11 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708061156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.2708061156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_smoke.2322929466 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 254537653 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 11:34:06 AM UTC 24 |
| Finished | Oct 03 11:34:09 AM UTC 24 |
| Peak memory | 209788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322929466 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2322929466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_stress_all.3799349497 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1000335294 ps |
| CPU time | 6.46 seconds |
| Started | Oct 03 11:34:09 AM UTC 24 |
| Finished | Oct 03 11:34:16 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799349497 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.3799349497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst.1441670513 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 371315969 ps |
| CPU time | 3.25 seconds |
| Started | Oct 03 11:34:07 AM UTC 24 |
| Finished | Oct 03 11:34:11 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441670513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1441670513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/18.rstmgr_sw_rst_reset_race.1620753987 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 267775928 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 11:34:07 AM UTC 24 |
| Finished | Oct 03 11:34:10 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620753987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.1620753987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/18.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_alert_test.3004370092 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 91818487 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 11:34:12 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004370092 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3004370092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_cnsty.689879468 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1978502020 ps |
| CPU time | 11.31 seconds |
| Started | Oct 03 11:34:12 AM UTC 24 |
| Finished | Oct 03 11:34:25 AM UTC 24 |
| Peak memory | 244416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689879468 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.689879468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_leaf_rst_shadow_attack.4229333853 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 302666141 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 11:34:12 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229333853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.4229333853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_por_stretcher.1647894706 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 191109035 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:34:10 AM UTC 24 |
| Finished | Oct 03 11:34:12 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647894706 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.1647894706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_reset.533586166 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1778717626 ps |
| CPU time | 10.85 seconds |
| Started | Oct 03 11:34:10 AM UTC 24 |
| Finished | Oct 03 11:34:22 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533586166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.533586166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.720170392 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 109193003 ps |
| CPU time | 1.54 seconds |
| Started | Oct 03 11:34:12 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720170392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.720170392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_smoke.352944907 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 234487846 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 11:34:10 AM UTC 24 |
| Finished | Oct 03 11:34:13 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352944907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.352944907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_stress_all.942139005 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5595246166 ps |
| CPU time | 23.03 seconds |
| Started | Oct 03 11:34:12 AM UTC 24 |
| Finished | Oct 03 11:34:37 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942139005 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.942139005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst.2135642086 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 144284159 ps |
| CPU time | 2.59 seconds |
| Started | Oct 03 11:34:11 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135642086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2135642086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/19.rstmgr_sw_rst_reset_race.771266292 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 211735234 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 11:34:10 AM UTC 24 |
| Finished | Oct 03 11:34:13 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771266292 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.771266292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/19.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.1080164710 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 76487191 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:32:48 AM UTC 24 |
| Finished | Oct 03 11:32:50 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080164710 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1080164710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.712870125 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1273370667 ps |
| CPU time | 8.17 seconds |
| Started | Oct 03 11:32:44 AM UTC 24 |
| Finished | Oct 03 11:32:54 AM UTC 24 |
| Peak memory | 253900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712870125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.712870125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3892951219 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 301941899 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 11:32:44 AM UTC 24 |
| Finished | Oct 03 11:32:48 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892951219 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3892951219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.1877943143 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 141902563 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:32:41 AM UTC 24 |
| Finished | Oct 03 11:32:43 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877943143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.1877943143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.1265322364 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1575382438 ps |
| CPU time | 8.72 seconds |
| Started | Oct 03 11:32:42 AM UTC 24 |
| Finished | Oct 03 11:32:52 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265322364 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1265322364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm.3864587253 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 8304423576 ps |
| CPU time | 28.63 seconds |
| Started | Oct 03 11:32:48 AM UTC 24 |
| Finished | Oct 03 11:33:18 AM UTC 24 |
| Peak memory | 243572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864587253 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3864587253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1363195322 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 178279265 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 11:32:44 AM UTC 24 |
| Finished | Oct 03 11:32:47 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363195322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.1363195322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.1028295827 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 202194086 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 11:32:41 AM UTC 24 |
| Finished | Oct 03 11:32:44 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028295827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1028295827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.64972870 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 287448193 ps |
| CPU time | 2.49 seconds |
| Started | Oct 03 11:32:45 AM UTC 24 |
| Finished | Oct 03 11:32:49 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64972870 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.64972870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.984373926 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 363167083 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 11:32:44 AM UTC 24 |
| Finished | Oct 03 11:32:49 AM UTC 24 |
| Peak memory | 211140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984373926 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.984373926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.1115609990 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 156567561 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 11:32:44 AM UTC 24 |
| Finished | Oct 03 11:32:47 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115609990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.1115609990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_alert_test.2150732728 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 63454107 ps |
| CPU time | 1.08 seconds |
| Started | Oct 03 11:34:16 AM UTC 24 |
| Finished | Oct 03 11:34:18 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150732728 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.2150732728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_cnsty.1430610818 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1273131441 ps |
| CPU time | 7.04 seconds |
| Started | Oct 03 11:34:16 AM UTC 24 |
| Finished | Oct 03 11:34:24 AM UTC 24 |
| Peak memory | 243992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430610818 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.1430610818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_leaf_rst_shadow_attack.85869429 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 301025092 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 11:34:16 AM UTC 24 |
| Finished | Oct 03 11:34:19 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85869429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.85869429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_por_stretcher.97984589 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 203659183 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 11:34:14 AM UTC 24 |
| Finished | Oct 03 11:34:16 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97984589 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.97984589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_reset.3732092445 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1065906900 ps |
| CPU time | 6.08 seconds |
| Started | Oct 03 11:34:14 AM UTC 24 |
| Finished | Oct 03 11:34:21 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732092445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.3732092445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2629824090 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 104736913 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:34:15 AM UTC 24 |
| Finished | Oct 03 11:34:17 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629824090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2629824090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_smoke.2607339937 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 110778019 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:34:13 AM UTC 24 |
| Finished | Oct 03 11:34:15 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607339937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.2607339937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_stress_all.199070805 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2140173499 ps |
| CPU time | 8.96 seconds |
| Started | Oct 03 11:34:16 AM UTC 24 |
| Finished | Oct 03 11:34:26 AM UTC 24 |
| Peak memory | 222316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199070805 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.199070805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst.200336831 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 136482460 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 11:34:15 AM UTC 24 |
| Finished | Oct 03 11:34:19 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200336831 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.200336831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/20.rstmgr_sw_rst_reset_race.1867492127 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 186998442 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:34:14 AM UTC 24 |
| Finished | Oct 03 11:34:17 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867492127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1867492127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/20.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_alert_test.3230667685 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 71981205 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:34:20 AM UTC 24 |
| Finished | Oct 03 11:34:22 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230667685 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.3230667685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_cnsty.1275917394 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2223330251 ps |
| CPU time | 14.08 seconds |
| Started | Oct 03 11:34:20 AM UTC 24 |
| Finished | Oct 03 11:34:35 AM UTC 24 |
| Peak memory | 244436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275917394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1275917394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_leaf_rst_shadow_attack.1723833942 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 304284931 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:34:20 AM UTC 24 |
| Finished | Oct 03 11:34:23 AM UTC 24 |
| Peak memory | 239140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723833942 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.1723833942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_por_stretcher.2436159237 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 74485616 ps |
| CPU time | 1.07 seconds |
| Started | Oct 03 11:34:18 AM UTC 24 |
| Finished | Oct 03 11:34:20 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436159237 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2436159237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_reset.1877918439 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 988256878 ps |
| CPU time | 6.06 seconds |
| Started | Oct 03 11:34:18 AM UTC 24 |
| Finished | Oct 03 11:34:25 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877918439 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.1877918439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.2044578705 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 146156786 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:34:19 AM UTC 24 |
| Finished | Oct 03 11:34:22 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044578705 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.2044578705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_smoke.2675031195 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 120284288 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:34:16 AM UTC 24 |
| Finished | Oct 03 11:34:19 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675031195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.2675031195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_stress_all.3229813556 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 15209361944 ps |
| CPU time | 61.98 seconds |
| Started | Oct 03 11:34:20 AM UTC 24 |
| Finished | Oct 03 11:35:24 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229813556 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3229813556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst.2946029934 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 127314149 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 11:34:18 AM UTC 24 |
| Finished | Oct 03 11:34:21 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946029934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2946029934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/21.rstmgr_sw_rst_reset_race.1996566139 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 220530607 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 11:34:18 AM UTC 24 |
| Finished | Oct 03 11:34:20 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996566139 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1996566139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/21.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_alert_test.825254121 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 82363837 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:34:26 AM UTC 24 |
| Finished | Oct 03 11:34:29 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825254121 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.825254121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_cnsty.1033337150 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1283043493 ps |
| CPU time | 8.32 seconds |
| Started | Oct 03 11:34:24 AM UTC 24 |
| Finished | Oct 03 11:34:33 AM UTC 24 |
| Peak memory | 244116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033337150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.1033337150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_leaf_rst_shadow_attack.3258337953 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 302324664 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:34:25 AM UTC 24 |
| Finished | Oct 03 11:34:28 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258337953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.3258337953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_por_stretcher.3364138812 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 224323676 ps |
| CPU time | 1.68 seconds |
| Started | Oct 03 11:34:21 AM UTC 24 |
| Finished | Oct 03 11:34:24 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364138812 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3364138812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_reset.416442650 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1016032177 ps |
| CPU time | 6.28 seconds |
| Started | Oct 03 11:34:21 AM UTC 24 |
| Finished | Oct 03 11:34:29 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416442650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.416442650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.426455088 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 179698186 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 11:34:24 AM UTC 24 |
| Finished | Oct 03 11:34:27 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426455088 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.426455088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_smoke.3781120979 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 240737726 ps |
| CPU time | 2.6 seconds |
| Started | Oct 03 11:34:21 AM UTC 24 |
| Finished | Oct 03 11:34:25 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781120979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.3781120979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_stress_all.1902208771 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1188324536 ps |
| CPU time | 6.43 seconds |
| Started | Oct 03 11:34:25 AM UTC 24 |
| Finished | Oct 03 11:34:33 AM UTC 24 |
| Peak memory | 220464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902208771 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.1902208771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst.922814389 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 132035986 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 11:34:23 AM UTC 24 |
| Finished | Oct 03 11:34:26 AM UTC 24 |
| Peak memory | 220276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922814389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.922814389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/22.rstmgr_sw_rst_reset_race.1734352395 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 249117166 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 11:34:23 AM UTC 24 |
| Finished | Oct 03 11:34:26 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734352395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.1734352395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/22.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_alert_test.924172775 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 62277773 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:34:30 AM UTC 24 |
| Finished | Oct 03 11:34:32 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924172775 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.924172775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_cnsty.1028959051 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2462381654 ps |
| CPU time | 10.83 seconds |
| Started | Oct 03 11:34:28 AM UTC 24 |
| Finished | Oct 03 11:34:40 AM UTC 24 |
| Peak memory | 243796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028959051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1028959051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_leaf_rst_shadow_attack.1909077314 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 302821204 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:34:29 AM UTC 24 |
| Finished | Oct 03 11:34:31 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909077314 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.1909077314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_por_stretcher.2893204912 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 83613040 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 11:34:26 AM UTC 24 |
| Finished | Oct 03 11:34:28 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893204912 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.2893204912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_reset.2239570578 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1515634952 ps |
| CPU time | 6.64 seconds |
| Started | Oct 03 11:34:27 AM UTC 24 |
| Finished | Oct 03 11:34:35 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239570578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2239570578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1400071246 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 143483797 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:34:28 AM UTC 24 |
| Finished | Oct 03 11:34:30 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400071246 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1400071246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_smoke.1125879341 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 196276569 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 11:34:26 AM UTC 24 |
| Finished | Oct 03 11:34:29 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125879341 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1125879341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_stress_all.264291889 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6447538592 ps |
| CPU time | 24.29 seconds |
| Started | Oct 03 11:34:30 AM UTC 24 |
| Finished | Oct 03 11:34:56 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264291889 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.264291889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst.621543785 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 116119757 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 11:34:28 AM UTC 24 |
| Finished | Oct 03 11:34:30 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621543785 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.621543785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/23.rstmgr_sw_rst_reset_race.4128104853 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 89739473 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:34:27 AM UTC 24 |
| Finished | Oct 03 11:34:30 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128104853 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.4128104853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/23.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_alert_test.1026508091 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 71241782 ps |
| CPU time | 0.94 seconds |
| Started | Oct 03 11:34:34 AM UTC 24 |
| Finished | Oct 03 11:34:36 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026508091 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1026508091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_cnsty.3413333163 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1272867325 ps |
| CPU time | 9.14 seconds |
| Started | Oct 03 11:34:33 AM UTC 24 |
| Finished | Oct 03 11:34:43 AM UTC 24 |
| Peak memory | 243732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413333163 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.3413333163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1737884538 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 303029356 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:34:34 AM UTC 24 |
| Finished | Oct 03 11:34:36 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737884538 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1737884538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_por_stretcher.1237705014 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 118039564 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:34:30 AM UTC 24 |
| Finished | Oct 03 11:34:33 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237705014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.1237705014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_reset.1451295252 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1272124520 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 11:34:30 AM UTC 24 |
| Finished | Oct 03 11:34:39 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451295252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.1451295252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.3536202591 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 102990507 ps |
| CPU time | 1.47 seconds |
| Started | Oct 03 11:34:31 AM UTC 24 |
| Finished | Oct 03 11:34:34 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536202591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.3536202591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_smoke.967288841 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 225244576 ps |
| CPU time | 2.4 seconds |
| Started | Oct 03 11:34:30 AM UTC 24 |
| Finished | Oct 03 11:34:34 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967288841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.967288841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_stress_all.938922532 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5151071265 ps |
| CPU time | 20.2 seconds |
| Started | Oct 03 11:34:34 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938922532 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.938922532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst.457013381 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 427774483 ps |
| CPU time | 4.02 seconds |
| Started | Oct 03 11:34:31 AM UTC 24 |
| Finished | Oct 03 11:34:36 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457013381 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.457013381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/24.rstmgr_sw_rst_reset_race.2083073424 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 203081764 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:34:31 AM UTC 24 |
| Finished | Oct 03 11:34:34 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083073424 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.2083073424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/24.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_alert_test.3612611889 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 63612129 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:34:38 AM UTC 24 |
| Finished | Oct 03 11:34:40 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612611889 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.3612611889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_cnsty.3731412939 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 1273784587 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 11:34:36 AM UTC 24 |
| Finished | Oct 03 11:34:45 AM UTC 24 |
| Peak memory | 244456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731412939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3731412939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_leaf_rst_shadow_attack.4217318509 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 301994702 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:34:37 AM UTC 24 |
| Finished | Oct 03 11:34:39 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217318509 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.4217318509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_por_stretcher.2660059906 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 121528603 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:34:34 AM UTC 24 |
| Finished | Oct 03 11:34:36 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660059906 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.2660059906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_reset.1729967029 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1049544457 ps |
| CPU time | 5.57 seconds |
| Started | Oct 03 11:34:35 AM UTC 24 |
| Finished | Oct 03 11:34:42 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729967029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.1729967029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.3991591495 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 156707349 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 11:34:36 AM UTC 24 |
| Finished | Oct 03 11:34:39 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991591495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.3991591495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_smoke.1177042893 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 198247341 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:34:34 AM UTC 24 |
| Finished | Oct 03 11:34:37 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177042893 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.1177042893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_stress_all.264920752 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3816148461 ps |
| CPU time | 21.64 seconds |
| Started | Oct 03 11:34:38 AM UTC 24 |
| Finished | Oct 03 11:35:01 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264920752 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.264920752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst.3573668502 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 111320123 ps |
| CPU time | 1.86 seconds |
| Started | Oct 03 11:34:35 AM UTC 24 |
| Finished | Oct 03 11:34:38 AM UTC 24 |
| Peak memory | 210056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573668502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.3573668502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/25.rstmgr_sw_rst_reset_race.4194232232 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 199620726 ps |
| CPU time | 2.04 seconds |
| Started | Oct 03 11:34:35 AM UTC 24 |
| Finished | Oct 03 11:34:38 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194232232 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.4194232232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/25.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_alert_test.2021437658 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 69832121 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 11:34:41 AM UTC 24 |
| Finished | Oct 03 11:34:43 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021437658 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2021437658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_cnsty.2270221416 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1958134529 ps |
| CPU time | 8.15 seconds |
| Started | Oct 03 11:34:41 AM UTC 24 |
| Finished | Oct 03 11:34:50 AM UTC 24 |
| Peak memory | 244536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270221416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.2270221416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_leaf_rst_shadow_attack.2561837153 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 302115178 ps |
| CPU time | 1.41 seconds |
| Started | Oct 03 11:34:41 AM UTC 24 |
| Finished | Oct 03 11:34:43 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561837153 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.2561837153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_por_stretcher.3189332768 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 131188730 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:34:38 AM UTC 24 |
| Finished | Oct 03 11:34:40 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189332768 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3189332768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_reset.1321674788 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 854704709 ps |
| CPU time | 5.51 seconds |
| Started | Oct 03 11:34:38 AM UTC 24 |
| Finished | Oct 03 11:34:44 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321674788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.1321674788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.148423445 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 176403252 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 11:34:39 AM UTC 24 |
| Finished | Oct 03 11:34:42 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148423445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.148423445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_smoke.3671506052 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 225564278 ps |
| CPU time | 2.48 seconds |
| Started | Oct 03 11:34:38 AM UTC 24 |
| Finished | Oct 03 11:34:41 AM UTC 24 |
| Peak memory | 211296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671506052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.3671506052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_stress_all.2053335841 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 109986568 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:34:41 AM UTC 24 |
| Finished | Oct 03 11:34:44 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053335841 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.2053335841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst.9841112 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 467951026 ps |
| CPU time | 3.08 seconds |
| Started | Oct 03 11:34:39 AM UTC 24 |
| Finished | Oct 03 11:34:43 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9841112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/ default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.9841112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/26.rstmgr_sw_rst_reset_race.3554997082 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 75861529 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:34:39 AM UTC 24 |
| Finished | Oct 03 11:34:41 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554997082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.3554997082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/26.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_alert_test.3404494327 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 67613444 ps |
| CPU time | 1.12 seconds |
| Started | Oct 03 11:34:45 AM UTC 24 |
| Finished | Oct 03 11:34:47 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404494327 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.3404494327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_cnsty.1686433127 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1271964884 ps |
| CPU time | 6.17 seconds |
| Started | Oct 03 11:34:43 AM UTC 24 |
| Finished | Oct 03 11:34:51 AM UTC 24 |
| Peak memory | 243740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686433127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.1686433127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_leaf_rst_shadow_attack.1694285951 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 302204619 ps |
| CPU time | 1.32 seconds |
| Started | Oct 03 11:34:44 AM UTC 24 |
| Finished | Oct 03 11:34:46 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694285951 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.1694285951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_por_stretcher.4106699699 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 178953443 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:34:42 AM UTC 24 |
| Finished | Oct 03 11:34:45 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106699699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.4106699699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_reset.201104973 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1803050866 ps |
| CPU time | 12.23 seconds |
| Started | Oct 03 11:34:42 AM UTC 24 |
| Finished | Oct 03 11:34:56 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201104973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.201104973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.2802118681 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 184826499 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:34:42 AM UTC 24 |
| Finished | Oct 03 11:34:46 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802118681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.2802118681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_smoke.321818494 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 120536780 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:34:41 AM UTC 24 |
| Finished | Oct 03 11:34:44 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321818494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.321818494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_stress_all.24475556 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 10161404587 ps |
| CPU time | 48.45 seconds |
| Started | Oct 03 11:34:44 AM UTC 24 |
| Finished | Oct 03 11:35:34 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24475556 -assert nopostproc +UVM_TESTNAME=rs tmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.24475556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst.1191160776 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 381405267 ps |
| CPU time | 3.3 seconds |
| Started | Oct 03 11:34:42 AM UTC 24 |
| Finished | Oct 03 11:34:47 AM UTC 24 |
| Peak memory | 220052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191160776 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.1191160776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/27.rstmgr_sw_rst_reset_race.1830814631 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 151114101 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:34:42 AM UTC 24 |
| Finished | Oct 03 11:34:45 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830814631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.1830814631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/27.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_alert_test.2620548089 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 70280628 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:34:48 AM UTC 24 |
| Finished | Oct 03 11:34:51 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620548089 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.2620548089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_cnsty.42226028 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1960215041 ps |
| CPU time | 11.97 seconds |
| Started | Oct 03 11:34:46 AM UTC 24 |
| Finished | Oct 03 11:35:00 AM UTC 24 |
| Peak memory | 244476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42226028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.42226028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3108083453 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 300949307 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:34:47 AM UTC 24 |
| Finished | Oct 03 11:34:51 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108083453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3108083453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_por_stretcher.1291155532 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 91789728 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:34:45 AM UTC 24 |
| Finished | Oct 03 11:34:47 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291155532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1291155532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_reset.1594033722 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2084875706 ps |
| CPU time | 7.13 seconds |
| Started | Oct 03 11:34:45 AM UTC 24 |
| Finished | Oct 03 11:34:53 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594033722 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.1594033722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1594009247 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 179068472 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 11:34:46 AM UTC 24 |
| Finished | Oct 03 11:34:50 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594009247 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1594009247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_smoke.536634136 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 185040608 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:34:45 AM UTC 24 |
| Finished | Oct 03 11:34:48 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536634136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.536634136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_stress_all.2960420911 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1863589932 ps |
| CPU time | 8.57 seconds |
| Started | Oct 03 11:34:47 AM UTC 24 |
| Finished | Oct 03 11:34:58 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960420911 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.2960420911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst.1777226730 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 462578436 ps |
| CPU time | 2.98 seconds |
| Started | Oct 03 11:34:46 AM UTC 24 |
| Finished | Oct 03 11:34:50 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777226730 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.1777226730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/28.rstmgr_sw_rst_reset_race.654920788 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 68357477 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:34:46 AM UTC 24 |
| Finished | Oct 03 11:34:49 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654920788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.654920788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/28.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_alert_test.3346571914 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 76744753 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:34:52 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 210128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346571914 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.3346571914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_cnsty.2555182297 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2438017439 ps |
| CPU time | 9.21 seconds |
| Started | Oct 03 11:34:51 AM UTC 24 |
| Finished | Oct 03 11:35:01 AM UTC 24 |
| Peak memory | 244480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555182297 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2555182297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_leaf_rst_shadow_attack.3130649485 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 302496940 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:34:52 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 240052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130649485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.3130649485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_por_stretcher.1567231777 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 109321701 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:34:49 AM UTC 24 |
| Finished | Oct 03 11:34:51 AM UTC 24 |
| Peak memory | 210120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567231777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.1567231777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_reset.4291745797 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1258406810 ps |
| CPU time | 5.2 seconds |
| Started | Oct 03 11:34:49 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291745797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.4291745797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.3667921050 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 191355906 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:34:51 AM UTC 24 |
| Finished | Oct 03 11:34:54 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667921050 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.3667921050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_smoke.3963967569 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 183659394 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 11:34:49 AM UTC 24 |
| Finished | Oct 03 11:34:52 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963967569 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.3963967569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_stress_all.4010801704 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 9653283808 ps |
| CPU time | 35.9 seconds |
| Started | Oct 03 11:34:52 AM UTC 24 |
| Finished | Oct 03 11:35:30 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010801704 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.4010801704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst.2453721137 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 133205182 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 11:34:51 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453721137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.2453721137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/29.rstmgr_sw_rst_reset_race.302147018 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 69823858 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:34:50 AM UTC 24 |
| Finished | Oct 03 11:34:52 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302147018 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.302147018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/29.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.2018129676 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 89274137 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 11:32:53 AM UTC 24 |
| Finished | Oct 03 11:32:55 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018129676 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2018129676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.519336203 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 301565166 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:32:52 AM UTC 24 |
| Finished | Oct 03 11:32:55 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519336203 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.519336203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.537705520 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 133120001 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:32:49 AM UTC 24 |
| Finished | Oct 03 11:32:51 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537705520 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.537705520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.8925301 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1708220292 ps |
| CPU time | 9.74 seconds |
| Started | Oct 03 11:32:49 AM UTC 24 |
| Finished | Oct 03 11:33:00 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8925301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=r stmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.8925301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm.3040207178 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 16746947823 ps |
| CPU time | 33.16 seconds |
| Started | Oct 03 11:32:53 AM UTC 24 |
| Finished | Oct 03 11:33:27 AM UTC 24 |
| Peak memory | 244136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040207178 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3040207178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.3739679544 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 99319631 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:32:50 AM UTC 24 |
| Finished | Oct 03 11:32:53 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739679544 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.3739679544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.2733093166 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 118699851 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 11:32:49 AM UTC 24 |
| Finished | Oct 03 11:32:52 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733093166 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2733093166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.3952722274 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 158789062 ps |
| CPU time | 2.09 seconds |
| Started | Oct 03 11:32:52 AM UTC 24 |
| Finished | Oct 03 11:32:56 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952722274 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.3952722274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.2998563330 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 385074329 ps |
| CPU time | 2.56 seconds |
| Started | Oct 03 11:32:50 AM UTC 24 |
| Finished | Oct 03 11:32:54 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998563330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2998563330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.4142877720 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 165040394 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 11:32:49 AM UTC 24 |
| Finished | Oct 03 11:32:52 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142877720 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.4142877720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_alert_test.2960550099 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 55535263 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:34:58 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960550099 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.2960550099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_cnsty.1005022978 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2450470648 ps |
| CPU time | 9.63 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 244520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005022978 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.1005022978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1525292921 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 301567209 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:34:59 AM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525292921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1525292921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_por_stretcher.3888734099 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 129207409 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:34:53 AM UTC 24 |
| Finished | Oct 03 11:34:56 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888734099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.3888734099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_reset.777564635 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 912922970 ps |
| CPU time | 5.58 seconds |
| Started | Oct 03 11:34:54 AM UTC 24 |
| Finished | Oct 03 11:35:00 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777564635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.777564635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.820451013 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 174315846 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:34:59 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820451013 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.820451013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_smoke.2629219783 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 108909713 ps |
| CPU time | 1.97 seconds |
| Started | Oct 03 11:34:52 AM UTC 24 |
| Finished | Oct 03 11:34:55 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629219783 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.2629219783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_stress_all.3787741297 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1673887206 ps |
| CPU time | 10.25 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:35:08 AM UTC 24 |
| Peak memory | 220272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787741297 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.3787741297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst.4242317470 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 143318459 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 11:34:55 AM UTC 24 |
| Finished | Oct 03 11:34:58 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242317470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.4242317470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/30.rstmgr_sw_rst_reset_race.3563478150 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 209954599 ps |
| CPU time | 2.12 seconds |
| Started | Oct 03 11:34:55 AM UTC 24 |
| Finished | Oct 03 11:34:58 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563478150 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.3563478150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/30.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_alert_test.996566202 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 68950315 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:35:00 AM UTC 24 |
| Finished | Oct 03 11:35:02 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996566202 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.996566202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_cnsty.434951915 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2429849705 ps |
| CPU time | 8.77 seconds |
| Started | Oct 03 11:34:59 AM UTC 24 |
| Finished | Oct 03 11:35:09 AM UTC 24 |
| Peak memory | 244540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434951915 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.434951915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_leaf_rst_shadow_attack.3778302236 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 306152642 ps |
| CPU time | 1.35 seconds |
| Started | Oct 03 11:34:59 AM UTC 24 |
| Finished | Oct 03 11:35:01 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778302236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.3778302236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_por_stretcher.845390393 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 191985765 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:34:57 AM UTC 24 |
| Finished | Oct 03 11:35:00 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845390393 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.845390393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_reset.1382603519 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 1416042052 ps |
| CPU time | 8.68 seconds |
| Started | Oct 03 11:34:58 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382603519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.1382603519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.1910575101 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 177282947 ps |
| CPU time | 1.87 seconds |
| Started | Oct 03 11:34:59 AM UTC 24 |
| Finished | Oct 03 11:35:02 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910575101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.1910575101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_smoke.862122712 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 114942833 ps |
| CPU time | 1.79 seconds |
| Started | Oct 03 11:34:56 AM UTC 24 |
| Finished | Oct 03 11:34:59 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862122712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.862122712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_stress_all.3191976629 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 8652733249 ps |
| CPU time | 35.09 seconds |
| Started | Oct 03 11:35:00 AM UTC 24 |
| Finished | Oct 03 11:35:37 AM UTC 24 |
| Peak memory | 220528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191976629 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3191976629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst.4222438736 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 121689171 ps |
| CPU time | 2.42 seconds |
| Started | Oct 03 11:34:59 AM UTC 24 |
| Finished | Oct 03 11:35:02 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222438736 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.4222438736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/31.rstmgr_sw_rst_reset_race.997761394 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 163444283 ps |
| CPU time | 1.84 seconds |
| Started | Oct 03 11:34:58 AM UTC 24 |
| Finished | Oct 03 11:35:01 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997761394 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.997761394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/31.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_alert_test.303071840 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 67318561 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:35:04 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303071840 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.303071840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_cnsty.4292707133 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1270912938 ps |
| CPU time | 7.6 seconds |
| Started | Oct 03 11:35:03 AM UTC 24 |
| Finished | Oct 03 11:35:12 AM UTC 24 |
| Peak memory | 243336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292707133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.4292707133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4157050327 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 301068969 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 11:35:03 AM UTC 24 |
| Finished | Oct 03 11:35:06 AM UTC 24 |
| Peak memory | 239556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157050327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4157050327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_por_stretcher.589848619 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 129775503 ps |
| CPU time | 1.06 seconds |
| Started | Oct 03 11:35:00 AM UTC 24 |
| Finished | Oct 03 11:35:02 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589848619 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.589848619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_reset.1609094027 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 826251843 ps |
| CPU time | 6.32 seconds |
| Started | Oct 03 11:35:01 AM UTC 24 |
| Finished | Oct 03 11:35:09 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609094027 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.1609094027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.935205969 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 97609883 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:35:02 AM UTC 24 |
| Finished | Oct 03 11:35:04 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935205969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.935205969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_smoke.170733375 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 125525934 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 11:35:00 AM UTC 24 |
| Finished | Oct 03 11:35:03 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170733375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.170733375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_stress_all.3755828839 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1610408900 ps |
| CPU time | 7.91 seconds |
| Started | Oct 03 11:35:03 AM UTC 24 |
| Finished | Oct 03 11:35:12 AM UTC 24 |
| Peak memory | 211332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755828839 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.3755828839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst.3733699861 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 325817625 ps |
| CPU time | 3.69 seconds |
| Started | Oct 03 11:35:02 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733699861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.3733699861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/32.rstmgr_sw_rst_reset_race.651182452 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 107866747 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:35:02 AM UTC 24 |
| Finished | Oct 03 11:35:04 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651182452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.651182452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/32.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_alert_test.733473090 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 72399525 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:11 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733473090 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.733473090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_cnsty.2422665987 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1281037623 ps |
| CPU time | 5.99 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:15 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422665987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.2422665987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_leaf_rst_shadow_attack.118568113 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 302285714 ps |
| CPU time | 1.91 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:11 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118568113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.118568113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_por_stretcher.189076323 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 97454926 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:35:04 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189076323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.189076323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_reset.518919147 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 653742872 ps |
| CPU time | 5.6 seconds |
| Started | Oct 03 11:35:04 AM UTC 24 |
| Finished | Oct 03 11:35:11 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518919147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.518919147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2568708675 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 178696816 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:35:05 AM UTC 24 |
| Finished | Oct 03 11:35:08 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568708675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2568708675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_smoke.3479660882 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 111331395 ps |
| CPU time | 1.76 seconds |
| Started | Oct 03 11:35:04 AM UTC 24 |
| Finished | Oct 03 11:35:07 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479660882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.3479660882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_stress_all.2537044048 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6159255189 ps |
| CPU time | 34.02 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:44 AM UTC 24 |
| Peak memory | 220524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537044048 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.2537044048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst.218883128 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 545085939 ps |
| CPU time | 3.34 seconds |
| Started | Oct 03 11:35:05 AM UTC 24 |
| Finished | Oct 03 11:35:10 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218883128 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.218883128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/33.rstmgr_sw_rst_reset_race.3062459578 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 166486857 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 11:35:04 AM UTC 24 |
| Finished | Oct 03 11:35:08 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062459578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.3062459578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/33.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_alert_test.3087558548 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 70152396 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:15 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087558548 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.3087558548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_cnsty.1821018392 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1964757259 ps |
| CPU time | 11.19 seconds |
| Started | Oct 03 11:35:10 AM UTC 24 |
| Finished | Oct 03 11:35:22 AM UTC 24 |
| Peak memory | 244048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821018392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1821018392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_leaf_rst_shadow_attack.1014547215 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 301696109 ps |
| CPU time | 1.94 seconds |
| Started | Oct 03 11:35:11 AM UTC 24 |
| Finished | Oct 03 11:35:14 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014547215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.1014547215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_por_stretcher.83816865 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 92865603 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:11 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83816865 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.83816865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_reset.129966016 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1558130626 ps |
| CPU time | 6.46 seconds |
| Started | Oct 03 11:35:09 AM UTC 24 |
| Finished | Oct 03 11:35:17 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129966016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.129966016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.1139771112 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 176194363 ps |
| CPU time | 1.82 seconds |
| Started | Oct 03 11:35:10 AM UTC 24 |
| Finished | Oct 03 11:35:13 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139771112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.1139771112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_smoke.1422233828 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 197990716 ps |
| CPU time | 2.15 seconds |
| Started | Oct 03 11:35:08 AM UTC 24 |
| Finished | Oct 03 11:35:12 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422233828 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1422233828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_stress_all.1669964485 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 8552972755 ps |
| CPU time | 36.03 seconds |
| Started | Oct 03 11:35:11 AM UTC 24 |
| Finished | Oct 03 11:35:48 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669964485 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.1669964485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst.3648449293 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 298331641 ps |
| CPU time | 3.46 seconds |
| Started | Oct 03 11:35:10 AM UTC 24 |
| Finished | Oct 03 11:35:14 AM UTC 24 |
| Peak memory | 220064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648449293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.3648449293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/34.rstmgr_sw_rst_reset_race.2202779024 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 158120210 ps |
| CPU time | 1.77 seconds |
| Started | Oct 03 11:35:09 AM UTC 24 |
| Finished | Oct 03 11:35:12 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202779024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.2202779024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/34.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_alert_test.2560018151 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 62405365 ps |
| CPU time | 1.18 seconds |
| Started | Oct 03 11:35:14 AM UTC 24 |
| Finished | Oct 03 11:35:16 AM UTC 24 |
| Peak memory | 210028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560018151 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.2560018151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_cnsty.2559220566 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1953956228 ps |
| CPU time | 7.97 seconds |
| Started | Oct 03 11:35:14 AM UTC 24 |
| Finished | Oct 03 11:35:23 AM UTC 24 |
| Peak memory | 244456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559220566 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.2559220566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_leaf_rst_shadow_attack.1573712359 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 302824988 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 11:35:14 AM UTC 24 |
| Finished | Oct 03 11:35:17 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573712359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.1573712359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_por_stretcher.2716972007 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 166155019 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:15 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716972007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.2716972007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_reset.821048263 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 733461742 ps |
| CPU time | 6.11 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:20 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821048263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.821048263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.2231338573 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 111230716 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 11:35:14 AM UTC 24 |
| Finished | Oct 03 11:35:16 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231338573 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.2231338573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_smoke.796306201 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 243660843 ps |
| CPU time | 2.32 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:16 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796306201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.796306201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_stress_all.2368705868 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3734810933 ps |
| CPU time | 15.73 seconds |
| Started | Oct 03 11:35:14 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 220524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368705868 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.2368705868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst.808930052 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 506329101 ps |
| CPU time | 4.14 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:17 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808930052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.808930052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/35.rstmgr_sw_rst_reset_race.957061252 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 236401996 ps |
| CPU time | 2.26 seconds |
| Started | Oct 03 11:35:12 AM UTC 24 |
| Finished | Oct 03 11:35:16 AM UTC 24 |
| Peak memory | 211392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957061252 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.957061252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/35.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_alert_test.2709264049 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 59604745 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 11:35:18 AM UTC 24 |
| Finished | Oct 03 11:35:20 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709264049 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.2709264049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_cnsty.832272609 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2457470930 ps |
| CPU time | 10.55 seconds |
| Started | Oct 03 11:35:16 AM UTC 24 |
| Finished | Oct 03 11:35:28 AM UTC 24 |
| Peak memory | 244604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832272609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.832272609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_leaf_rst_shadow_attack.4242464630 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 301619792 ps |
| CPU time | 2.16 seconds |
| Started | Oct 03 11:35:18 AM UTC 24 |
| Finished | Oct 03 11:35:21 AM UTC 24 |
| Peak memory | 239980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242464630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.4242464630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_por_stretcher.3614614777 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 234370614 ps |
| CPU time | 1.38 seconds |
| Started | Oct 03 11:35:15 AM UTC 24 |
| Finished | Oct 03 11:35:17 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614614777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.3614614777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_reset.2406243077 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 838751473 ps |
| CPU time | 4.61 seconds |
| Started | Oct 03 11:35:16 AM UTC 24 |
| Finished | Oct 03 11:35:22 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406243077 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.2406243077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.239829251 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 184782658 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 11:35:16 AM UTC 24 |
| Finished | Oct 03 11:35:19 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239829251 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.239829251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_smoke.1813842500 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 122737725 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:35:15 AM UTC 24 |
| Finished | Oct 03 11:35:18 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813842500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.1813842500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_stress_all.1964024401 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4945403436 ps |
| CPU time | 22.33 seconds |
| Started | Oct 03 11:35:18 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964024401 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.1964024401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst.2363511611 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 121068983 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 11:35:16 AM UTC 24 |
| Finished | Oct 03 11:35:19 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363511611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.2363511611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/36.rstmgr_sw_rst_reset_race.3887870735 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 224527411 ps |
| CPU time | 2.08 seconds |
| Started | Oct 03 11:35:16 AM UTC 24 |
| Finished | Oct 03 11:35:19 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887870735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.3887870735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/36.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_alert_test.2829625902 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 71161912 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:35:20 AM UTC 24 |
| Finished | Oct 03 11:35:23 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829625902 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.2829625902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_cnsty.520729460 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1273757379 ps |
| CPU time | 7.65 seconds |
| Started | Oct 03 11:35:20 AM UTC 24 |
| Finished | Oct 03 11:35:29 AM UTC 24 |
| Peak memory | 243784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520729460 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.520729460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_leaf_rst_shadow_attack.3574217835 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 302493234 ps |
| CPU time | 2.03 seconds |
| Started | Oct 03 11:35:20 AM UTC 24 |
| Finished | Oct 03 11:35:23 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574217835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.3574217835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_por_stretcher.3714040565 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 86077561 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:35:19 AM UTC 24 |
| Finished | Oct 03 11:35:21 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714040565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.3714040565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_reset.782559939 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1469338770 ps |
| CPU time | 7.1 seconds |
| Started | Oct 03 11:35:19 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782559939 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.782559939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4211808390 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 102957272 ps |
| CPU time | 1.57 seconds |
| Started | Oct 03 11:35:20 AM UTC 24 |
| Finished | Oct 03 11:35:23 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211808390 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4211808390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_smoke.2278818035 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 191203469 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:35:18 AM UTC 24 |
| Finished | Oct 03 11:35:20 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278818035 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.2278818035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_stress_all.2179555014 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1275907697 ps |
| CPU time | 7.32 seconds |
| Started | Oct 03 11:35:20 AM UTC 24 |
| Finished | Oct 03 11:35:29 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179555014 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.2179555014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst.2335629001 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 369496457 ps |
| CPU time | 2.45 seconds |
| Started | Oct 03 11:35:19 AM UTC 24 |
| Finished | Oct 03 11:35:23 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335629001 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.2335629001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/37.rstmgr_sw_rst_reset_race.939678210 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 99206960 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:35:19 AM UTC 24 |
| Finished | Oct 03 11:35:21 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939678210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.939678210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/37.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_alert_test.1262179564 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 77122484 ps |
| CPU time | 1.26 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262179564 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.1262179564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_cnsty.3443673198 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2441209317 ps |
| CPU time | 10.34 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:36 AM UTC 24 |
| Peak memory | 244532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443673198 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.3443673198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_leaf_rst_shadow_attack.341434970 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 302652313 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341434970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.341434970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_por_stretcher.1322491788 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 139072645 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:35:22 AM UTC 24 |
| Finished | Oct 03 11:35:26 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322491788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.1322491788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_reset.216005060 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2036424584 ps |
| CPU time | 8.02 seconds |
| Started | Oct 03 11:35:22 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216005060 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.216005060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.3971934907 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 156912899 ps |
| CPU time | 1.43 seconds |
| Started | Oct 03 11:35:23 AM UTC 24 |
| Finished | Oct 03 11:35:25 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971934907 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.3971934907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_smoke.2075481207 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 255898816 ps |
| CPU time | 2.73 seconds |
| Started | Oct 03 11:35:22 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075481207 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.2075481207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_stress_all.138216886 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5487076139 ps |
| CPU time | 21.96 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:47 AM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138216886 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.138216886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst.717452617 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 148731871 ps |
| CPU time | 2.61 seconds |
| Started | Oct 03 11:35:23 AM UTC 24 |
| Finished | Oct 03 11:35:26 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717452617 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.717452617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/38.rstmgr_sw_rst_reset_race.3561697645 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 76733309 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:35:23 AM UTC 24 |
| Finished | Oct 03 11:35:25 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561697645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.3561697645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/38.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_alert_test.3757229340 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 70412062 ps |
| CPU time | 1.29 seconds |
| Started | Oct 03 11:35:28 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757229340 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.3757229340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_cnsty.1621337863 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2261297713 ps |
| CPU time | 8.42 seconds |
| Started | Oct 03 11:35:27 AM UTC 24 |
| Finished | Oct 03 11:35:36 AM UTC 24 |
| Peak memory | 243792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621337863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.1621337863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_leaf_rst_shadow_attack.773471141 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 301112285 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:35:28 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773471141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.773471141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_por_stretcher.3939292080 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 132907991 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939292080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.3939292080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_reset.4137965680 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1629462151 ps |
| CPU time | 8.17 seconds |
| Started | Oct 03 11:35:26 AM UTC 24 |
| Finished | Oct 03 11:35:35 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137965680 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.4137965680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.2991313883 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 147818507 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 11:35:27 AM UTC 24 |
| Finished | Oct 03 11:35:30 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991313883 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.2991313883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_smoke.4007937599 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 109824371 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:35:24 AM UTC 24 |
| Finished | Oct 03 11:35:27 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007937599 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.4007937599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_stress_all.308130510 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 6102580187 ps |
| CPU time | 25.5 seconds |
| Started | Oct 03 11:35:28 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308130510 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.308130510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst.153668977 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 124315891 ps |
| CPU time | 2.39 seconds |
| Started | Oct 03 11:35:27 AM UTC 24 |
| Finished | Oct 03 11:35:30 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153668977 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.153668977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/39.rstmgr_sw_rst_reset_race.538141360 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 209366349 ps |
| CPU time | 2.19 seconds |
| Started | Oct 03 11:35:26 AM UTC 24 |
| Finished | Oct 03 11:35:29 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538141360 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.538141360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/39.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.1282597651 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 68122251 ps |
| CPU time | 1.1 seconds |
| Started | Oct 03 11:32:59 AM UTC 24 |
| Finished | Oct 03 11:33:01 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282597651 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.1282597651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_cnsty.3525212675 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1966087879 ps |
| CPU time | 11.48 seconds |
| Started | Oct 03 11:32:56 AM UTC 24 |
| Finished | Oct 03 11:33:09 AM UTC 24 |
| Peak memory | 244460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525212675 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.3525212675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.3296967927 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 309959292 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 11:32:57 AM UTC 24 |
| Finished | Oct 03 11:33:00 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296967927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.3296967927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.1098108108 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 92438622 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:32:54 AM UTC 24 |
| Finished | Oct 03 11:32:56 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098108108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.1098108108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.1678070471 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1540670581 ps |
| CPU time | 8.59 seconds |
| Started | Oct 03 11:32:55 AM UTC 24 |
| Finished | Oct 03 11:33:05 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678070471 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.1678070471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm.1527206834 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 17095714100 ps |
| CPU time | 35.72 seconds |
| Started | Oct 03 11:32:59 AM UTC 24 |
| Finished | Oct 03 11:33:36 AM UTC 24 |
| Peak memory | 243436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527206834 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1527206834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3234081796 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 100146887 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:32:56 AM UTC 24 |
| Finished | Oct 03 11:32:59 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234081796 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.3234081796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.3926365982 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 119985839 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:32:54 AM UTC 24 |
| Finished | Oct 03 11:32:57 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926365982 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.3926365982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_stress_all.4035895962 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 10497487435 ps |
| CPU time | 39.9 seconds |
| Started | Oct 03 11:32:57 AM UTC 24 |
| Finished | Oct 03 11:33:39 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035895962 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.4035895962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.3983452990 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 122285088 ps |
| CPU time | 2.63 seconds |
| Started | Oct 03 11:32:56 AM UTC 24 |
| Finished | Oct 03 11:33:00 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983452990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3983452990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.1526751301 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 73661773 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:32:55 AM UTC 24 |
| Finished | Oct 03 11:32:57 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526751301 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.1526751301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_alert_test.3793519782 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 73320594 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:35:31 AM UTC 24 |
| Finished | Oct 03 11:35:33 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793519782 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.3793519782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_cnsty.14912184 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2259591780 ps |
| CPU time | 8.96 seconds |
| Started | Oct 03 11:35:30 AM UTC 24 |
| Finished | Oct 03 11:35:40 AM UTC 24 |
| Peak memory | 244140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14912184 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.14912184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3602395275 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 301749559 ps |
| CPU time | 1.93 seconds |
| Started | Oct 03 11:35:31 AM UTC 24 |
| Finished | Oct 03 11:35:34 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602395275 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3602395275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_por_stretcher.86376597 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 89985205 ps |
| CPU time | 1.3 seconds |
| Started | Oct 03 11:35:29 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86376597 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.86376597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_reset.3579101739 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1532963206 ps |
| CPU time | 5.92 seconds |
| Started | Oct 03 11:35:29 AM UTC 24 |
| Finished | Oct 03 11:35:36 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579101739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.3579101739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.1870983133 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 107438495 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 11:35:30 AM UTC 24 |
| Finished | Oct 03 11:35:32 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870983133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.1870983133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_smoke.3296687598 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 115446298 ps |
| CPU time | 1.52 seconds |
| Started | Oct 03 11:35:28 AM UTC 24 |
| Finished | Oct 03 11:35:31 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296687598 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.3296687598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_stress_all.1335244832 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 7021835334 ps |
| CPU time | 33.42 seconds |
| Started | Oct 03 11:35:31 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 220528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335244832 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1335244832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst.823442274 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 346660986 ps |
| CPU time | 3.44 seconds |
| Started | Oct 03 11:35:30 AM UTC 24 |
| Finished | Oct 03 11:35:34 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823442274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.823442274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/40.rstmgr_sw_rst_reset_race.491089130 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 206408417 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:35:30 AM UTC 24 |
| Finished | Oct 03 11:35:32 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491089130 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.491089130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/40.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_alert_test.511176208 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 78243064 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 11:35:34 AM UTC 24 |
| Finished | Oct 03 11:35:36 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511176208 -assert nopostproc +UVM_TESTNAME=rstm gr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.511176208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_cnsty.3675691974 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2427969366 ps |
| CPU time | 11.49 seconds |
| Started | Oct 03 11:35:33 AM UTC 24 |
| Finished | Oct 03 11:35:45 AM UTC 24 |
| Peak memory | 243788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675691974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.3675691974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_leaf_rst_shadow_attack.2295953644 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 302402025 ps |
| CPU time | 2.06 seconds |
| Started | Oct 03 11:35:34 AM UTC 24 |
| Finished | Oct 03 11:35:37 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295953644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.2295953644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_por_stretcher.1162674470 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 111568975 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:35:31 AM UTC 24 |
| Finished | Oct 03 11:35:34 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162674470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.1162674470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_reset.3198581228 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1265925848 ps |
| CPU time | 7.59 seconds |
| Started | Oct 03 11:35:33 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198581228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.3198581228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.3833749519 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 96570418 ps |
| CPU time | 1.66 seconds |
| Started | Oct 03 11:35:33 AM UTC 24 |
| Finished | Oct 03 11:35:35 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833749519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.3833749519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_smoke.3676476449 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 121787962 ps |
| CPU time | 1.85 seconds |
| Started | Oct 03 11:35:31 AM UTC 24 |
| Finished | Oct 03 11:35:34 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676476449 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.3676476449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_stress_all.4050939614 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6331617156 ps |
| CPU time | 28.8 seconds |
| Started | Oct 03 11:35:34 AM UTC 24 |
| Finished | Oct 03 11:36:04 AM UTC 24 |
| Peak memory | 220232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050939614 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.4050939614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst.1142436731 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 260872426 ps |
| CPU time | 2.98 seconds |
| Started | Oct 03 11:35:33 AM UTC 24 |
| Finished | Oct 03 11:35:37 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142436731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1142436731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/41.rstmgr_sw_rst_reset_race.480150731 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 111537187 ps |
| CPU time | 1.63 seconds |
| Started | Oct 03 11:35:33 AM UTC 24 |
| Finished | Oct 03 11:35:35 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480150731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.480150731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/41.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_alert_test.3902839125 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 68980589 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:39 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902839125 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.3902839125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_cnsty.482857253 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1972169040 ps |
| CPU time | 9.64 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:48 AM UTC 24 |
| Peak memory | 244516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482857253 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.482857253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_leaf_rst_shadow_attack.508278255 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 301405432 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:40 AM UTC 24 |
| Peak memory | 239836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508278255 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.508278255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_por_stretcher.1833692495 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 75696511 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:35:35 AM UTC 24 |
| Finished | Oct 03 11:35:37 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833692495 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.1833692495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_reset.3662053644 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1563296473 ps |
| CPU time | 8.71 seconds |
| Started | Oct 03 11:35:35 AM UTC 24 |
| Finished | Oct 03 11:35:45 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662053644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.3662053644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.26712860 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 109943159 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:39 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26712860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstm gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.26712860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_smoke.3713691310 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 125822788 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:35:35 AM UTC 24 |
| Finished | Oct 03 11:35:38 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713691310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.3713691310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_stress_all.2363574215 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1973219973 ps |
| CPU time | 10.96 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:49 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363574215 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2363574215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst.2528149235 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 289287056 ps |
| CPU time | 3.01 seconds |
| Started | Oct 03 11:35:37 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528149235 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.2528149235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/42.rstmgr_sw_rst_reset_race.131038970 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 110946306 ps |
| CPU time | 1.58 seconds |
| Started | Oct 03 11:35:35 AM UTC 24 |
| Finished | Oct 03 11:35:38 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131038970 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.131038970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/42.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_alert_test.3116562709 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 88364920 ps |
| CPU time | 1.39 seconds |
| Started | Oct 03 11:35:41 AM UTC 24 |
| Finished | Oct 03 11:35:43 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116562709 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.3116562709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_cnsty.2546626692 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2254057955 ps |
| CPU time | 11.1 seconds |
| Started | Oct 03 11:35:40 AM UTC 24 |
| Finished | Oct 03 11:35:52 AM UTC 24 |
| Peak memory | 244184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546626692 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2546626692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_leaf_rst_shadow_attack.4208682788 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 303441185 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:35:40 AM UTC 24 |
| Finished | Oct 03 11:35:43 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208682788 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.4208682788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_por_stretcher.3727829391 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 187695873 ps |
| CPU time | 1.53 seconds |
| Started | Oct 03 11:35:38 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727829391 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.3727829391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_reset.861070830 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 810034955 ps |
| CPU time | 5.96 seconds |
| Started | Oct 03 11:35:38 AM UTC 24 |
| Finished | Oct 03 11:35:45 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861070830 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.861070830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.2306519303 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 151406376 ps |
| CPU time | 1.74 seconds |
| Started | Oct 03 11:35:39 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306519303 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.2306519303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_smoke.2165583759 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 117439248 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 11:35:38 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165583759 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2165583759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_stress_all.329667570 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 5020520060 ps |
| CPU time | 20.52 seconds |
| Started | Oct 03 11:35:41 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 220348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329667570 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.329667570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst.3983680257 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 147818097 ps |
| CPU time | 2.74 seconds |
| Started | Oct 03 11:35:39 AM UTC 24 |
| Finished | Oct 03 11:35:42 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983680257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.3983680257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/43.rstmgr_sw_rst_reset_race.286805554 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 67021770 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:35:38 AM UTC 24 |
| Finished | Oct 03 11:35:41 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286805554 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.286805554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/43.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_alert_test.1026050048 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 61359021 ps |
| CPU time | 1.17 seconds |
| Started | Oct 03 11:35:44 AM UTC 24 |
| Finished | Oct 03 11:35:46 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026050048 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.1026050048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_cnsty.3955299823 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1973752626 ps |
| CPU time | 10.73 seconds |
| Started | Oct 03 11:35:43 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 244484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955299823 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.3955299823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_leaf_rst_shadow_attack.1265028004 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 303743064 ps |
| CPU time | 1.95 seconds |
| Started | Oct 03 11:35:43 AM UTC 24 |
| Finished | Oct 03 11:35:46 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265028004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.1265028004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_por_stretcher.2948441384 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 159245076 ps |
| CPU time | 1.42 seconds |
| Started | Oct 03 11:35:41 AM UTC 24 |
| Finished | Oct 03 11:35:44 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948441384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2948441384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_reset.1166495010 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1280701435 ps |
| CPU time | 5.19 seconds |
| Started | Oct 03 11:35:42 AM UTC 24 |
| Finished | Oct 03 11:35:49 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166495010 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.1166495010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.1128437187 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 109660315 ps |
| CPU time | 1.6 seconds |
| Started | Oct 03 11:35:43 AM UTC 24 |
| Finished | Oct 03 11:35:45 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128437187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.1128437187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_smoke.2897105781 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 114369150 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 11:35:41 AM UTC 24 |
| Finished | Oct 03 11:35:44 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897105781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2897105781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_stress_all.3911166115 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 236865127 ps |
| CPU time | 2.68 seconds |
| Started | Oct 03 11:35:44 AM UTC 24 |
| Finished | Oct 03 11:35:48 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911166115 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3911166115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst.3814247514 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 146404506 ps |
| CPU time | 1.98 seconds |
| Started | Oct 03 11:35:43 AM UTC 24 |
| Finished | Oct 03 11:35:46 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814247514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.3814247514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/44.rstmgr_sw_rst_reset_race.2735023304 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 274571123 ps |
| CPU time | 2.23 seconds |
| Started | Oct 03 11:35:43 AM UTC 24 |
| Finished | Oct 03 11:35:46 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735023304 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.2735023304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/44.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_alert_test.1118424214 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 83693943 ps |
| CPU time | 1.03 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:49 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118424214 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.1118424214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_cnsty.3229875462 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1268285007 ps |
| CPU time | 6.8 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 243852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229875462 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.3229875462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_leaf_rst_shadow_attack.73872350 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 301579543 ps |
| CPU time | 2.17 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:50 AM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73872350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.73872350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_por_stretcher.3570631741 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 202370127 ps |
| CPU time | 1.46 seconds |
| Started | Oct 03 11:35:44 AM UTC 24 |
| Finished | Oct 03 11:35:47 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570631741 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.3570631741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_reset.3882740038 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1815285928 ps |
| CPU time | 8.13 seconds |
| Started | Oct 03 11:35:45 AM UTC 24 |
| Finished | Oct 03 11:35:54 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882740038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.3882740038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.418009445 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 102322411 ps |
| CPU time | 1.5 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:49 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418009445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.418009445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_smoke.814475700 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 249452966 ps |
| CPU time | 2.46 seconds |
| Started | Oct 03 11:35:44 AM UTC 24 |
| Finished | Oct 03 11:35:48 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814475700 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.814475700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_stress_all.2389591011 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4541112476 ps |
| CPU time | 21.21 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:36:09 AM UTC 24 |
| Peak memory | 220652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389591011 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.2389591011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst.294663064 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 137732903 ps |
| CPU time | 1.83 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:50 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294663064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.294663064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/45.rstmgr_sw_rst_reset_race.4086679522 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 300109528 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 11:35:45 AM UTC 24 |
| Finished | Oct 03 11:35:48 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086679522 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.4086679522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/45.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_alert_test.3788112987 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 65274892 ps |
| CPU time | 1.16 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:52 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788112987 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.3788112987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_cnsty.356824289 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1956053743 ps |
| CPU time | 7.49 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:57 AM UTC 24 |
| Peak memory | 244384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356824289 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.356824289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_leaf_rst_shadow_attack.28269112 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 301951237 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:52 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28269112 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.28269112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_por_stretcher.761041848 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 100856518 ps |
| CPU time | 1.05 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:49 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761041848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.761041848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_reset.255385558 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 1378967300 ps |
| CPU time | 7.69 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:56 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255385558 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.255385558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.1545502136 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 174566978 ps |
| CPU time | 1.88 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:51 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545502136 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.1545502136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_smoke.2760183320 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 231875381 ps |
| CPU time | 1.8 seconds |
| Started | Oct 03 11:35:47 AM UTC 24 |
| Finished | Oct 03 11:35:50 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760183320 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2760183320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_stress_all.1977791331 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 589832939 ps |
| CPU time | 3.72 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:54 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977791331 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.1977791331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst.2783610874 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 283910971 ps |
| CPU time | 2.54 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:52 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783610874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2783610874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/46.rstmgr_sw_rst_reset_race.954835616 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 251694054 ps |
| CPU time | 2.37 seconds |
| Started | Oct 03 11:35:49 AM UTC 24 |
| Finished | Oct 03 11:35:52 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954835616 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.954835616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/46.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_alert_test.2054504275 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 54732894 ps |
| CPU time | 0.99 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054504275 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.2054504275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_cnsty.1856248210 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1956052134 ps |
| CPU time | 9.44 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856248210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_cnsty.1856248210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_leaf_rst_shadow_attack.797432811 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 307901244 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:35:52 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797432811 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.797432811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_por_stretcher.2977215118 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 107450976 ps |
| CPU time | 1.33 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:53 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977215118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2977215118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_reset.3965549756 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1384002590 ps |
| CPU time | 6.43 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965549756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.3965549756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.4106580369 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 159029478 ps |
| CPU time | 1.78 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:53 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106580369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.4106580369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_smoke.3540163750 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 251159708 ps |
| CPU time | 1.65 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:53 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540163750 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.3540163750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_stress_all.3686446365 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 7885042427 ps |
| CPU time | 26.15 seconds |
| Started | Oct 03 11:35:52 AM UTC 24 |
| Finished | Oct 03 11:36:19 AM UTC 24 |
| Peak memory | 220524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686446365 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.3686446365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst.2027606377 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 143578805 ps |
| CPU time | 2.77 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:54 AM UTC 24 |
| Peak memory | 220048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027606377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.2027606377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/47.rstmgr_sw_rst_reset_race.4117615527 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 84030589 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:35:50 AM UTC 24 |
| Finished | Oct 03 11:35:53 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117615527 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.4117615527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/47.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_alert_test.1989338807 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 74452829 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:35:55 AM UTC 24 |
| Finished | Oct 03 11:35:57 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989338807 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.1989338807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_cnsty.3531641384 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1955338339 ps |
| CPU time | 8.11 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:36:03 AM UTC 24 |
| Peak memory | 243728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531641384 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.3531641384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1111393936 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 301707242 ps |
| CPU time | 1.89 seconds |
| Started | Oct 03 11:35:55 AM UTC 24 |
| Finished | Oct 03 11:35:57 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111393936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1111393936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_por_stretcher.4223595349 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 174733404 ps |
| CPU time | 1.22 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223595349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.4223595349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_reset.925878162 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1789138272 ps |
| CPU time | 6.55 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:36:01 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925878162 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.925878162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.889520762 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 174736159 ps |
| CPU time | 1.96 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:56 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889520762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.889520762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_smoke.2098153494 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 119527209 ps |
| CPU time | 1.99 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:56 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098153494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2098153494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_stress_all.729164273 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 479026040 ps |
| CPU time | 2.53 seconds |
| Started | Oct 03 11:35:55 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729164273 -assert nopostproc +UVM_TESTNAME=r stmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.729164273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst.608013630 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 450318933 ps |
| CPU time | 3.57 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608013630 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.608013630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/48.rstmgr_sw_rst_reset_race.651609513 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 62776389 ps |
| CPU time | 1.19 seconds |
| Started | Oct 03 11:35:53 AM UTC 24 |
| Finished | Oct 03 11:35:55 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651609513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.651609513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/48.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_alert_test.1893932875 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 81455489 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 210092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893932875 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.1893932875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_cnsty.3251281368 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2470968348 ps |
| CPU time | 9.56 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:36:07 AM UTC 24 |
| Peak memory | 243796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251281368 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.3251281368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_leaf_rst_shadow_attack.4111307141 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 301940572 ps |
| CPU time | 2.01 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:59 AM UTC 24 |
| Peak memory | 239276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111307141 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.4111307141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_por_stretcher.684428735 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 84038569 ps |
| CPU time | 1.01 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684428735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.684428735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_reset.2568415055 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1495078808 ps |
| CPU time | 8.52 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:36:06 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568415055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.2568415055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.3611137669 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 154784360 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611137669 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.3611137669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_smoke.206205319 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 221706927 ps |
| CPU time | 2.28 seconds |
| Started | Oct 03 11:35:55 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206205319 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.206205319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_stress_all.2306293601 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 15760115839 ps |
| CPU time | 47.4 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:36:45 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306293601 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.2306293601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst.71799401 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 140649520 ps |
| CPU time | 2.33 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:59 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71799401 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ= rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.71799401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/49.rstmgr_sw_rst_reset_race.262480290 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 107355518 ps |
| CPU time | 1.09 seconds |
| Started | Oct 03 11:35:56 AM UTC 24 |
| Finished | Oct 03 11:35:58 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262480290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.262480290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/49.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.3600997496 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 93657428 ps |
| CPU time | 1.34 seconds |
| Started | Oct 03 11:33:04 AM UTC 24 |
| Finished | Oct 03 11:33:07 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600997496 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.3600997496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.1256143097 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1278866985 ps |
| CPU time | 8.19 seconds |
| Started | Oct 03 11:33:03 AM UTC 24 |
| Finished | Oct 03 11:33:12 AM UTC 24 |
| Peak memory | 244020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256143097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.1256143097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.2754602014 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 302661973 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 11:33:03 AM UTC 24 |
| Finished | Oct 03 11:33:06 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754602014 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.2754602014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.687694443 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 114482199 ps |
| CPU time | 1.21 seconds |
| Started | Oct 03 11:33:00 AM UTC 24 |
| Finished | Oct 03 11:33:02 AM UTC 24 |
| Peak memory | 210036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687694443 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.687694443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.2483351510 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 1559039736 ps |
| CPU time | 8.14 seconds |
| Started | Oct 03 11:33:01 AM UTC 24 |
| Finished | Oct 03 11:33:10 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483351510 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.2483351510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.2689532332 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 97702331 ps |
| CPU time | 1.56 seconds |
| Started | Oct 03 11:33:02 AM UTC 24 |
| Finished | Oct 03 11:33:05 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689532332 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.2689532332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.1633123825 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 117787180 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:33:00 AM UTC 24 |
| Finished | Oct 03 11:33:02 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633123825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.1633123825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_stress_all.3186855280 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 409834429 ps |
| CPU time | 2.82 seconds |
| Started | Oct 03 11:33:03 AM UTC 24 |
| Finished | Oct 03 11:33:07 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186855280 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.3186855280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.3242377905 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 352415083 ps |
| CPU time | 2.53 seconds |
| Started | Oct 03 11:33:01 AM UTC 24 |
| Finished | Oct 03 11:33:05 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242377905 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3242377905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1318854987 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 81399712 ps |
| CPU time | 1.23 seconds |
| Started | Oct 03 11:33:01 AM UTC 24 |
| Finished | Oct 03 11:33:03 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318854987 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.1318854987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/5.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1213644132 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 63653951 ps |
| CPU time | 1.24 seconds |
| Started | Oct 03 11:33:10 AM UTC 24 |
| Finished | Oct 03 11:33:12 AM UTC 24 |
| Peak memory | 210148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213644132 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1213644132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2285457480 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1265287220 ps |
| CPU time | 9.92 seconds |
| Started | Oct 03 11:33:09 AM UTC 24 |
| Finished | Oct 03 11:33:20 AM UTC 24 |
| Peak memory | 243732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285457480 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2285457480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.2478334827 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 301417801 ps |
| CPU time | 2 seconds |
| Started | Oct 03 11:33:09 AM UTC 24 |
| Finished | Oct 03 11:33:12 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478334827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.2478334827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1842773179 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 94660868 ps |
| CPU time | 1.28 seconds |
| Started | Oct 03 11:33:06 AM UTC 24 |
| Finished | Oct 03 11:33:08 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842773179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.1842773179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.1563746423 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1812887761 ps |
| CPU time | 9.3 seconds |
| Started | Oct 03 11:33:06 AM UTC 24 |
| Finished | Oct 03 11:33:16 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563746423 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1563746423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.1549985867 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 142574119 ps |
| CPU time | 1.71 seconds |
| Started | Oct 03 11:33:08 AM UTC 24 |
| Finished | Oct 03 11:33:11 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549985867 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.1549985867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.4115869835 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 118609786 ps |
| CPU time | 1.64 seconds |
| Started | Oct 03 11:33:06 AM UTC 24 |
| Finished | Oct 03 11:33:08 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115869835 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.4115869835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.2219059622 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3149840472 ps |
| CPU time | 12.11 seconds |
| Started | Oct 03 11:33:10 AM UTC 24 |
| Finished | Oct 03 11:33:23 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219059622 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2219059622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.3770791377 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 329834641 ps |
| CPU time | 3.38 seconds |
| Started | Oct 03 11:33:08 AM UTC 24 |
| Finished | Oct 03 11:33:12 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770791377 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.3770791377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2712173790 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 75493952 ps |
| CPU time | 1.2 seconds |
| Started | Oct 03 11:33:07 AM UTC 24 |
| Finished | Oct 03 11:33:09 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712173790 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.2712173790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/6.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2003462546 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 59822972 ps |
| CPU time | 1.15 seconds |
| Started | Oct 03 11:33:17 AM UTC 24 |
| Finished | Oct 03 11:33:20 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003462546 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.2003462546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.620688966 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1281490106 ps |
| CPU time | 7.4 seconds |
| Started | Oct 03 11:33:14 AM UTC 24 |
| Finished | Oct 03 11:33:22 AM UTC 24 |
| Peak memory | 243784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620688966 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.620688966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.2270656615 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 302156654 ps |
| CPU time | 1.51 seconds |
| Started | Oct 03 11:33:15 AM UTC 24 |
| Finished | Oct 03 11:33:18 AM UTC 24 |
| Peak memory | 239272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270656615 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.2270656615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.2497187082 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 122454177 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 11:33:11 AM UTC 24 |
| Finished | Oct 03 11:33:14 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497187082 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.2497187082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.1781835994 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2100882513 ps |
| CPU time | 9.04 seconds |
| Started | Oct 03 11:33:12 AM UTC 24 |
| Finished | Oct 03 11:33:22 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781835994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.1781835994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.979442420 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 142911834 ps |
| CPU time | 1.67 seconds |
| Started | Oct 03 11:33:14 AM UTC 24 |
| Finished | Oct 03 11:33:17 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979442420 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.979442420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.3102030116 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 188154465 ps |
| CPU time | 2.11 seconds |
| Started | Oct 03 11:33:10 AM UTC 24 |
| Finished | Oct 03 11:33:13 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102030116 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3102030116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.1649267834 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4452156544 ps |
| CPU time | 31.28 seconds |
| Started | Oct 03 11:33:15 AM UTC 24 |
| Finished | Oct 03 11:33:48 AM UTC 24 |
| Peak memory | 211592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649267834 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.1649267834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.826473284 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 152240899 ps |
| CPU time | 2.71 seconds |
| Started | Oct 03 11:33:14 AM UTC 24 |
| Finished | Oct 03 11:33:18 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826473284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.826473284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.3164904313 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 158572882 ps |
| CPU time | 1.81 seconds |
| Started | Oct 03 11:33:13 AM UTC 24 |
| Finished | Oct 03 11:33:16 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164904313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.3164904313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/7.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.2363516511 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 79912906 ps |
| CPU time | 1.27 seconds |
| Started | Oct 03 11:33:23 AM UTC 24 |
| Finished | Oct 03 11:33:25 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363516511 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.2363516511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.4110205392 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2454793371 ps |
| CPU time | 10.86 seconds |
| Started | Oct 03 11:33:21 AM UTC 24 |
| Finished | Oct 03 11:33:33 AM UTC 24 |
| Peak memory | 244508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110205392 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4110205392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.211934641 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 301649857 ps |
| CPU time | 2.05 seconds |
| Started | Oct 03 11:33:22 AM UTC 24 |
| Finished | Oct 03 11:33:25 AM UTC 24 |
| Peak memory | 239984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211934641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.211934641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.860796313 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 106331814 ps |
| CPU time | 1.31 seconds |
| Started | Oct 03 11:33:17 AM UTC 24 |
| Finished | Oct 03 11:33:20 AM UTC 24 |
| Peak memory | 210036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860796313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.860796313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.3232923605 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1835918483 ps |
| CPU time | 11.4 seconds |
| Started | Oct 03 11:33:18 AM UTC 24 |
| Finished | Oct 03 11:33:32 AM UTC 24 |
| Peak memory | 211352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232923605 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.3232923605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.2858288144 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 152450184 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:33:21 AM UTC 24 |
| Finished | Oct 03 11:33:24 AM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858288144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rs tmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.2858288144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3755730362 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 191900306 ps |
| CPU time | 2.13 seconds |
| Started | Oct 03 11:33:17 AM UTC 24 |
| Finished | Oct 03 11:33:21 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755730362 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.3755730362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.3671099257 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5389620804 ps |
| CPU time | 33.94 seconds |
| Started | Oct 03 11:33:22 AM UTC 24 |
| Finished | Oct 03 11:33:58 AM UTC 24 |
| Peak memory | 211528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671099257 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3671099257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3902786607 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 120623448 ps |
| CPU time | 2.29 seconds |
| Started | Oct 03 11:33:19 AM UTC 24 |
| Finished | Oct 03 11:33:23 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902786607 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.3902786607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.3476282440 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 244069465 ps |
| CPU time | 2.14 seconds |
| Started | Oct 03 11:33:19 AM UTC 24 |
| Finished | Oct 03 11:33:23 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476282440 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.3476282440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/8.rstmgr_sw_rst_reset_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3268122458 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 68481984 ps |
| CPU time | 1.04 seconds |
| Started | Oct 03 11:33:28 AM UTC 24 |
| Finished | Oct 03 11:33:30 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268122458 -assert nopostproc +UVM_TESTNAME=rst mgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3268122458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3945498352 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2426927802 ps |
| CPU time | 11.69 seconds |
| Started | Oct 03 11:33:27 AM UTC 24 |
| Finished | Oct 03 11:33:40 AM UTC 24 |
| Peak memory | 244540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945498352 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3945498352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3354588902 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 303074197 ps |
| CPU time | 2.02 seconds |
| Started | Oct 03 11:33:27 AM UTC 24 |
| Finished | Oct 03 11:33:30 AM UTC 24 |
| Peak memory | 239988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354588902 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3354588902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_leaf_rst_shadow_attack/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.1972448144 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 172698664 ps |
| CPU time | 1.36 seconds |
| Started | Oct 03 11:33:23 AM UTC 24 |
| Finished | Oct 03 11:33:26 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972448144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.1972448144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_por_stretcher/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.4188197892 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1431407350 ps |
| CPU time | 7.37 seconds |
| Started | Oct 03 11:33:24 AM UTC 24 |
| Finished | Oct 03 11:33:33 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188197892 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.4188197892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.929222285 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 146330585 ps |
| CPU time | 1.7 seconds |
| Started | Oct 03 11:33:26 AM UTC 24 |
| Finished | Oct 03 11:33:28 AM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929222285 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rst mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.929222285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_sec_cm_scan_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.496660769 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 113857231 ps |
| CPU time | 1.9 seconds |
| Started | Oct 03 11:33:23 AM UTC 24 |
| Finished | Oct 03 11:33:26 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496660769 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.496660769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.1918958905 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 10489331656 ps |
| CPU time | 43.49 seconds |
| Started | Oct 03 11:33:27 AM UTC 24 |
| Finished | Oct 03 11:34:12 AM UTC 24 |
| Peak memory | 220340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918958905 -assert nopostproc +UVM_TESTNAME= rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_02/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.1918958905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.480026753 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 128956711 ps |
| CPU time | 2.34 seconds |
| Started | Oct 03 11:33:24 AM UTC 24 |
| Finished | Oct 03 11:33:28 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480026753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ =rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.480026753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_sw_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.2408774063 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 96525886 ps |
| CPU time | 1.37 seconds |
| Started | Oct 03 11:33:24 AM UTC 24 |
| Finished | Oct 03 11:33:27 AM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408774063 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SE Q=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.2408774063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_02/rstmgr-sim-vcs/9.rstmgr_sw_rst_reset_race/latest |
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