Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

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Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7236

1

T3

6

T7

24

T12

18

auto[1]

10183

1

T2

4

T3

1

T4

4

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5517	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	5907	1			T1	1		T2	2		T3	1
reset_info_cp[2]	2631	1			T2	1		T4	1		T7	8
reset_info_cp[4]	3443	1			T2	1		T4	1		T7	8
reset_info_cp[8]	94	1			T38	1		T97	1		T26	1
reset_info_cp[16]	103	1			T12	2		T25	2		T37	1
reset_info_cp[32]	115	1			T7	1		T12	1		T79	1
reset_info_cp[64]	100	1			T42	1		T97	1		T43	2
reset_info_cp[128]	93	1			T23	1		T38	2		T97	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2791	1			T7	6		T23	6		T25	19
reset_info_cp[1]	auto[1]	2532	1			T2	1		T4	1		T7	6
reset_info_cp[2]	auto[0]	760	1			T7	5		T23	9		T38	4
reset_info_cp[2]	auto[1]	1871	1			T2	1		T4	1		T7	3
reset_info_cp[4]	auto[0]	1239	1			T7	4		T23	4		T38	6
reset_info_cp[4]	auto[1]	2204	1			T2	1		T4	1		T7	4
reset_info_cp[8]	auto[0]	47	1			T98	1		T84	1		T52	1
reset_info_cp[8]	auto[1]	47	1			T38	1		T97	1		T26	1
reset_info_cp[16]	auto[0]	42	1			T12	2		T37	1		T85	1
reset_info_cp[16]	auto[1]	61	1			T25	2		T26	1		T43	1
reset_info_cp[32]	auto[0]	44	1			T12	1		T52	1		T76	1
reset_info_cp[32]	auto[1]	71	1			T7	1		T79	1		T25	1
reset_info_cp[64]	auto[0]	50	1			T97	1		T53	1		T158	1
reset_info_cp[64]	auto[1]	50	1			T42	1		T43	2		T113	1
reset_info_cp[128]	auto[0]	37	1			T23	1		T52	1		T59	2
reset_info_cp[128]	auto[1]	56	1			T38	2		T97	1		T26	1