| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.46 | 99.40 | 99.31 | 100.00 | 99.83 | 99.46 | 98.77 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 83.16 | 83.16 | 95.13 | 95.13 | 79.04 | 79.04 | 89.78 | 89.78 | 94.27 | 94.27 | 90.71 | 90.71 | 50.00 | 50.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.682474159 | ||
| 89.09 | 5.93 | 97.24 | 2.10 | 84.46 | 5.41 | 91.03 | 1.26 | 97.81 | 3.54 | 92.33 | 1.62 | 71.67 | 21.67 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.1932800308 | ||
| 92.02 | 2.93 | 97.36 | 0.12 | 93.62 | 9.16 | 91.91 | 0.88 | 97.81 | 0.00 | 92.60 | 0.27 | 78.82 | 7.14 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.335634765 | ||
| 94.31 | 2.29 | 98.26 | 0.90 | 96.04 | 2.43 | 92.33 | 0.42 | 98.99 | 1.18 | 93.27 | 0.67 | 86.95 | 8.13 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_intg_err.470355979 | ||
| 95.84 | 1.53 | 98.68 | 0.42 | 96.53 | 0.49 | 95.18 | 2.85 | 99.33 | 0.34 | 96.90 | 3.63 | 88.42 | 1.48 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.307553777 | ||
| 97.08 | 1.24 | 99.10 | 0.42 | 96.88 | 0.35 | 98.74 | 3.56 | 99.66 | 0.34 | 97.71 | 0.81 | 90.39 | 1.97 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2371912370 | ||
| 97.82 | 0.74 | 99.10 | 0.00 | 98.27 | 1.39 | 98.91 | 0.17 | 99.83 | 0.17 | 97.71 | 0.00 | 93.10 | 2.71 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_tl_errors.4213370472 | ||
| 98.23 | 0.41 | 99.10 | 0.00 | 98.27 | 0.00 | 98.91 | 0.00 | 99.83 | 0.00 | 97.71 | 0.00 | 95.57 | 2.46 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst_reset_race.2741547785 | ||
| 98.48 | 0.25 | 99.10 | 0.00 | 98.27 | 0.00 | 99.41 | 0.50 | 99.83 | 0.00 | 97.71 | 0.00 | 96.55 | 0.99 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3641951 | ||
| 98.67 | 0.19 | 99.10 | 0.00 | 98.33 | 0.07 | 99.41 | 0.00 | 99.83 | 0.00 | 98.52 | 0.81 | 96.80 | 0.25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_stress_all.326153895 | ||
| 98.83 | 0.16 | 99.10 | 0.00 | 98.33 | 0.00 | 99.41 | 0.00 | 99.83 | 0.00 | 98.52 | 0.00 | 97.78 | 0.99 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2480390612 | ||
| 98.97 | 0.14 | 99.40 | 0.30 | 98.68 | 0.35 | 99.58 | 0.17 | 99.83 | 0.00 | 98.52 | 0.00 | 97.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.4133223582 | ||
| 99.06 | 0.09 | 99.40 | 0.00 | 98.68 | 0.00 | 99.58 | 0.00 | 99.83 | 0.00 | 99.06 | 0.54 | 97.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/12.rstmgr_reset.3653374895 | ||
| 99.13 | 0.08 | 99.40 | 0.00 | 98.68 | 0.00 | 99.92 | 0.34 | 99.83 | 0.00 | 99.19 | 0.13 | 97.78 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_cnsty.3950325626 | ||
| 99.21 | 0.08 | 99.40 | 0.00 | 98.89 | 0.21 | 99.92 | 0.00 | 99.83 | 0.00 | 99.19 | 0.00 | 98.03 | 0.25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2682793730 | ||
| 99.27 | 0.06 | 99.40 | 0.00 | 98.89 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.13 | 98.28 | 0.25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1192992588 | ||
| 99.31 | 0.04 | 99.40 | 0.00 | 98.89 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.00 | 98.52 | 0.25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/6.rstmgr_tl_intg_err.1822410026 | ||
| 99.36 | 0.04 | 99.40 | 0.00 | 98.89 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.00 | 98.77 | 0.25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_stress_all.1200154984 | ||
| 99.39 | 0.03 | 99.40 | 0.00 | 99.10 | 0.21 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_errors.170478271 | ||
| 99.41 | 0.02 | 99.40 | 0.00 | 99.24 | 0.14 | 99.92 | 0.00 | 99.83 | 0.00 | 99.33 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_intg_err.2190133344 | ||
| 99.44 | 0.02 | 99.40 | 0.00 | 99.24 | 0.00 | 99.92 | 0.00 | 99.83 | 0.00 | 99.46 | 0.13 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_rw.2258172992 | ||
| 99.45 | 0.01 | 99.40 | 0.00 | 99.24 | 0.00 | 100.00 | 0.08 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4243328785 | ||
| 99.46 | 0.01 | 99.40 | 0.00 | 99.31 | 0.07 | 100.00 | 0.00 | 99.83 | 0.00 | 99.46 | 0.00 | 98.77 | 0.00 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_intg_err.2270584439 | ||
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_aliasing.1335340937 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3624685872 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.1156618755 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.2418957449 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_csr_rw.706583748 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/0.rstmgr_tl_intg_err.4009928320 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_aliasing.3669461174 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.336936358 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.2738080948 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.2984371133 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.731446766 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.1260635320 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_csr_rw.3032594555 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.2158658086 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_errors.3456047929 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/10.rstmgr_tl_intg_err.2191694342 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.3113859937 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_csr_rw.2580544648 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1723313982 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_errors.3747339853 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/11.rstmgr_tl_intg_err.1965208206 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.1427548541 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_csr_rw.2698743682 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2186048639 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/12.rstmgr_tl_errors.678781014 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_csr_rw.2553709646 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/13.rstmgr_tl_errors.3529188204 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2424081672 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_csr_rw.3001606166 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2119230960 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.4242430782 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_csr_rw.837875805 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_errors.673108457 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3857759091 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.2997732163 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_csr_rw.2724874090 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_errors.3641973637 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/16.rstmgr_tl_intg_err.70784713 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.2365992541 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_csr_rw.462085479 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1339592222 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_errors.1865186581 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/17.rstmgr_tl_intg_err.1023986711 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.2732649505 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_csr_rw.3568578211 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.4108939866 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_errors.291787024 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/18.rstmgr_tl_intg_err.1215292101 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1933669781 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_csr_rw.3023953915 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_errors.690943058 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/19.rstmgr_tl_intg_err.587252108 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.3391208643 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2551380906 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2827712495 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_csr_rw.2901936710 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/2.rstmgr_tl_errors.1121683862 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.202878059 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/3.rstmgr_csr_rw.1960890973 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/cover_reg_top/4.rstmgr_csr_aliasing.2243438632 |
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| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_cnsty.2904757281 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1562207050 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1026521262 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2210137018 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.430733308 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2640265692 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_stress_all.2817395413 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.950452547 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2297691724 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2090656895 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_cnsty.1245919803 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.867216351 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.553258031 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3496102788 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.679969522 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2009564286 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_stress_all.2549046372 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst.207061441 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sw_rst_reset_race.2013449108 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_alert_test.3768293013 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_cnsty.1063575147 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1615334487 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_por_stretcher.2008254576 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_reset.1631799147 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.1686188869 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_smoke.3646686729 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_stress_all.1117758308 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst.3545263957 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/8.rstmgr_sw_rst_reset_race.2891990754 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_alert_test.3237616848 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_cnsty.3657297881 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_leaf_rst_shadow_attack.208259481 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_por_stretcher.3253926957 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_reset.3178963521 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.4208997591 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_smoke.469845273 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_stress_all.3609582283 |
| /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/9.rstmgr_sw_rst.4178650874 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_por_stretcher.1192992588 | Oct 09 06:03:49 AM UTC 24 | Oct 09 06:03:51 AM UTC 24 | 114749756 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_smoke.965890684 | Oct 09 06:03:49 AM UTC 24 | Oct 09 06:03:52 AM UTC 24 | 239622011 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst_reset_race.2240826745 | Oct 09 06:03:50 AM UTC 24 | Oct 09 06:03:53 AM UTC 24 | 121701735 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.2480390612 | Oct 09 06:03:50 AM UTC 24 | Oct 09 06:03:53 AM UTC 24 | 136357096 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_shadow_attack.2234631742 | Oct 09 06:03:51 AM UTC 24 | Oct 09 06:03:54 AM UTC 24 | 302708565 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_sw_rst.1945927585 | Oct 09 06:03:50 AM UTC 24 | Oct 09 06:03:54 AM UTC 24 | 428197325 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_reset.3136715391 | Oct 09 06:03:49 AM UTC 24 | Oct 09 06:03:55 AM UTC 24 | 1143379031 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_alert_test.4133223582 | Oct 09 06:03:53 AM UTC 24 | Oct 09 06:03:55 AM UTC 24 | 62022612 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_por_stretcher.2601536742 | Oct 09 06:03:53 AM UTC 24 | Oct 09 06:03:56 AM UTC 24 | 154694851 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_smoke.682474159 | Oct 09 06:03:53 AM UTC 24 | Oct 09 06:03:56 AM UTC 24 | 234331593 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2066722376 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:03:57 AM UTC 24 | 181690345 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst_reset_race.3822558645 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:03:57 AM UTC 24 | 231905644 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_por_stretcher.3886478052 | Oct 09 06:03:56 AM UTC 24 | Oct 09 06:03:58 AM UTC 24 | 82401716 ps | ||
| T24 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_shadow_attack.815370116 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:03:58 AM UTC 24 | 306918000 ps | ||
| T47 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_alert_test.410200846 | Oct 09 06:03:56 AM UTC 24 | Oct 09 06:03:58 AM UTC 24 | 66914181 ps | ||
| T21 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_smoke.3612941374 | Oct 09 06:03:56 AM UTC 24 | Oct 09 06:03:58 AM UTC 24 | 119606067 ps | ||
| T60 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sw_rst.1932800308 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:03:59 AM UTC 24 | 397866348 ps | ||
| T22 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst_reset_race.410449555 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:03:59 AM UTC 24 | 103328327 ps | ||
| T23 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_stress_all.609821409 | Oct 09 06:03:52 AM UTC 24 | Oct 09 06:03:59 AM UTC 24 | 1606502364 ps | ||
| T79 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.1814267403 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:03:59 AM UTC 24 | 146499906 ps | ||
| T67 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3307007407 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:04:00 AM UTC 24 | 301449297 ps | ||
| T25 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/0.rstmgr_leaf_rst_cnsty.2371912370 | Oct 09 06:03:51 AM UTC 24 | Oct 09 06:04:00 AM UTC 24 | 1979594089 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_alert_test.4291349554 | Oct 09 06:03:58 AM UTC 24 | Oct 09 06:04:00 AM UTC 24 | 60907666 ps | ||
| T36 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_sw_rst.513277759 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:04:00 AM UTC 24 | 396750677 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_por_stretcher.3873024901 | Oct 09 06:03:58 AM UTC 24 | Oct 09 06:04:01 AM UTC 24 | 167400344 ps | ||
| T37 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst_reset_race.3572837273 | Oct 09 06:03:59 AM UTC 24 | Oct 09 06:04:01 AM UTC 24 | 113030516 ps | ||
| T38 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_reset.335634765 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:04:01 AM UTC 24 | 1384135025 ps | ||
| T39 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_smoke.602749952 | Oct 09 06:03:58 AM UTC 24 | Oct 09 06:04:01 AM UTC 24 | 230874827 ps | ||
| T40 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sw_rst.1750575685 | Oct 09 06:03:59 AM UTC 24 | Oct 09 06:04:02 AM UTC 24 | 336402293 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_por_stretcher.1788249997 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:02 AM UTC 24 | 181371905 ps | ||
| T41 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_alert_test.681139703 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:02 AM UTC 24 | 71744032 ps | ||
| T153 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.630589315 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:02 AM UTC 24 | 143452231 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_smoke.113406480 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:02 AM UTC 24 | 120746701 ps | ||
| T154 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_shadow_attack.2875778046 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:03 AM UTC 24 | 302204543 ps | ||
| T149 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst_reset_race.634854902 | Oct 09 06:04:01 AM UTC 24 | Oct 09 06:04:03 AM UTC 24 | 63980672 ps | ||
| T42 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_leaf_rst_cnsty.3641951 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:04:03 AM UTC 24 | 1281417239 ps | ||
| T160 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_leaf_rst_shadow_attack.2096599640 | Oct 09 06:04:02 AM UTC 24 | Oct 09 06:04:04 AM UTC 24 | 302160278 ps | ||
| T152 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.3068817637 | Oct 09 06:04:01 AM UTC 24 | Oct 09 06:04:04 AM UTC 24 | 176526861 ps | ||
| T97 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/2.rstmgr_reset.2166242675 | Oct 09 06:03:57 AM UTC 24 | Oct 09 06:04:04 AM UTC 24 | 1256086439 ps | ||
| T26 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_leaf_rst_cnsty.4243328785 | Oct 09 06:03:54 AM UTC 24 | Oct 09 06:04:04 AM UTC 24 | 1980763024 ps | ||
| T102 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_leaf_rst_shadow_attack.867216351 | Oct 09 06:04:07 AM UTC 24 | Oct 09 06:04:11 AM UTC 24 | 301833592 ps | ||
| T81 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_sw_rst.37198878 | Oct 09 06:04:01 AM UTC 24 | Oct 09 06:04:05 AM UTC 24 | 139196069 ps | ||
| T103 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_alert_test.30084728 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:05 AM UTC 24 | 62743455 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_por_stretcher.4269692149 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:05 AM UTC 24 | 73823388 ps | ||
| T104 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst_reset_race.1455376344 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:05 AM UTC 24 | 166949825 ps | ||
| T82 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_smoke.3272042143 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:05 AM UTC 24 | 211242339 ps | ||
| T105 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.3601728780 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:06 AM UTC 24 | 170946906 ps | ||
| T98 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_reset.132723908 | Oct 09 06:03:58 AM UTC 24 | Oct 09 06:04:06 AM UTC 24 | 1693584801 ps | ||
| T83 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_sw_rst.1161547721 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 357292613 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_por_stretcher.1026521262 | Oct 09 06:04:05 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 184000347 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_alert_test.3281147370 | Oct 09 06:04:04 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 66155428 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_leaf_rst_shadow_attack.1826484723 | Oct 09 06:04:04 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 300865491 ps | ||
| T99 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/4.rstmgr_reset.3889544932 | Oct 09 06:04:01 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 780127472 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_smoke.2640265692 | Oct 09 06:04:04 AM UTC 24 | Oct 09 06:04:07 AM UTC 24 | 128153737 ps | ||
| T84 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst_reset_race.2297691724 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:08 AM UTC 24 | 72109176 ps | ||
| T85 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_stress_all.3287044574 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:08 AM UTC 24 | 1721674313 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_alert_test.1169968838 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:08 AM UTC 24 | 54771725 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_leaf_rst_shadow_attack.1562207050 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:08 AM UTC 24 | 308625711 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.430733308 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:08 AM UTC 24 | 98913100 ps | ||
| T87 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_smoke.2009564286 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:09 AM UTC 24 | 197111353 ps | ||
| T86 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_sw_rst.950452547 | Oct 09 06:04:06 AM UTC 24 | Oct 09 06:04:09 AM UTC 24 | 265485393 ps | ||
| T43 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/3.rstmgr_leaf_rst_cnsty.3836803449 | Oct 09 06:04:00 AM UTC 24 | Oct 09 06:04:09 AM UTC 24 | 2440419955 ps | ||
| T52 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_reset.3496102788 | Oct 09 06:04:07 AM UTC 24 | Oct 09 06:04:13 AM UTC 24 | 904201470 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_por_stretcher.553258031 | Oct 09 06:04:07 AM UTC 24 | Oct 09 06:04:09 AM UTC 24 | 138996389 ps | ||
| T53 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/6.rstmgr_reset.2210137018 | Oct 09 06:04:05 AM UTC 24 | Oct 09 06:04:10 AM UTC 24 | 776707913 ps | ||
| T54 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/5.rstmgr_reset.1846890231 | Oct 09 06:04:03 AM UTC 24 | Oct 09 06:04:10 AM UTC 24 | 1575243758 ps | ||
| T55 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_alert_test.2090656895 | Oct 09 06:04:08 AM UTC 24 | Oct 09 06:04:10 AM UTC 24 | 71701073 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.679969522 | Oct 09 06:04:07 AM UTC 24 | Oct 09 06:04:10 AM UTC 24 | 145244196 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_10_08/rstmgr-sim-vcs/coverage/default/1.rstmgr_sec_cm.307553777 | Oct 09 06:03:56 AM UTC 24 | Oct 09 06:04:10 AM UTC 24 | 8579316821 ps | ||
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