Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11865567	6469	0	0
alert_regwen_rd_A	11865567	6328	0	0
cpu_regwen_rd_A	11865567	6282	0	0
sw_rst_ctrl_n_0_rd_A	11865567	9816	0	0
sw_rst_ctrl_n_1_rd_A	11865567	9631	0	0
sw_rst_ctrl_n_2_rd_A	11865567	9986	0	0
sw_rst_ctrl_n_3_rd_A	11865567	9955	0	0
sw_rst_ctrl_n_4_rd_A	11865567	9890	0	0
sw_rst_ctrl_n_5_rd_A	11865567	9838	0	0
sw_rst_ctrl_n_6_rd_A	11865567	9766	0	0
sw_rst_ctrl_n_7_rd_A	11865567	9725	0	0
sw_rst_regwen_0_rd_A	11865567	6716	0	0
sw_rst_regwen_1_rd_A	11865567	6582	0	0
sw_rst_regwen_2_rd_A	11865567	6800	0	0
sw_rst_regwen_3_rd_A	11865567	6777	0	0
sw_rst_regwen_4_rd_A	11865567	6683	0	0
sw_rst_regwen_5_rd_A	11865567	6594	0	0
sw_rst_regwen_6_rd_A	11865567	6648	0	0
sw_rst_regwen_7_rd_A	11865567	6958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6469	0	0
T72	8656	2	0	0
T75	5673	165	0	0
T77	2720	35	0	0
T78	9770	440	0	0
T79	26054	2	0	0
T80	4323	25	0	0
T95	2170	195	0	0
T96	3997	104	0	0
T97	8985	336	0	0
T99	21306	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6328	0	0
T17	2594	0	0	0
T27	43582	0	0	0
T37	2272	0	0	0
T38	3250	0	0	0
T39	6521	0	0	0
T40	1610	0	0	0
T41	41039	71	0	0
T42	98131	0	0	0
T50	35911	52	0	0
T102	0	41	0	0
T104	3037	0	0	0
T106	0	333	0	0
T107	0	31	0	0
T108	0	69	0	0
T112	0	77	0	0
T132	0	71	0	0
T133	0	161	0	0
T134	0	128	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6282	0	0
T17	2594	0	0	0
T27	43582	0	0	0
T37	2272	0	0	0
T38	3250	0	0	0
T39	6521	0	0	0
T40	1610	0	0	0
T41	41039	78	0	0
T42	98131	0	0	0
T50	35911	52	0	0
T102	0	15	0	0
T104	3037	0	0	0
T106	0	347	0	0
T107	0	30	0	0
T108	0	67	0	0
T112	0	58	0	0
T132	0	74	0	0
T133	0	146	0	0
T134	0	118	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9816	0	0
T1	5875	14	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	17	0	0
T41	0	74	0	0
T50	0	73	0	0
T67	0	137	0	0
T102	0	32	0	0
T104	0	24	0	0
T112	0	41	0	0
T135	0	54	0	0
T136	0	63	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9631	0	0
T1	5875	12	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	18	0	0
T41	0	101	0	0
T50	0	61	0	0
T67	0	134	0	0
T102	0	23	0	0
T104	0	11	0	0
T112	0	53	0	0
T135	0	59	0	0
T136	0	80	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9986	0	0
T1	5875	16	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	18	0	0
T41	0	66	0	0
T50	0	56	0	0
T67	0	190	0	0
T102	0	17	0	0
T104	0	15	0	0
T112	0	53	0	0
T135	0	62	0	0
T136	0	99	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9955	0	0
T1	5875	7	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	16	0	0
T41	0	70	0	0
T50	0	65	0	0
T67	0	142	0	0
T102	0	36	0	0
T104	0	37	0	0
T112	0	50	0	0
T135	0	64	0	0
T136	0	74	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9890	0	0
T1	5875	10	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	22	0	0
T41	0	62	0	0
T50	0	52	0	0
T67	0	124	0	0
T102	0	23	0	0
T104	0	37	0	0
T112	0	65	0	0
T135	0	66	0	0
T136	0	60	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9838	0	0
T1	5875	15	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	19	0	0
T41	0	80	0	0
T50	0	58	0	0
T67	0	142	0	0
T102	0	40	0	0
T104	0	21	0	0
T112	0	52	0	0
T135	0	78	0	0
T136	0	60	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9766	0	0
T1	5875	12	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	36	0	0
T41	0	73	0	0
T50	0	60	0	0
T67	0	138	0	0
T102	0	25	0	0
T104	0	27	0	0
T112	0	56	0	0
T135	0	51	0	0
T136	0	62	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	9725	0	0
T1	5875	18	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T13	0	22	0	0
T41	0	62	0	0
T50	0	61	0	0
T67	0	136	0	0
T102	0	31	0	0
T104	0	42	0	0
T112	0	54	0	0
T135	0	62	0	0
T136	0	77	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6716	0	0
T1	5875	1	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	101	0	0
T50	0	74	0	0
T67	0	24	0	0
T102	0	23	0	0
T106	0	306	0	0
T112	0	77	0	0
T136	0	21	0	0
T137	0	4	0	0
T138	0	6	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6582	0	0
T1	5875	1	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	76	0	0
T50	0	45	0	0
T67	0	27	0	0
T102	0	32	0	0
T106	0	315	0	0
T112	0	57	0	0
T136	0	16	0	0
T137	0	7	0	0
T138	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6800	0	0
T1	5875	11	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	72	0	0
T50	0	46	0	0
T67	0	28	0	0
T102	0	24	0	0
T106	0	288	0	0
T112	0	60	0	0
T136	0	15	0	0
T137	0	7	0	0
T138	0	10	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6777	0	0
T1	5875	11	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	85	0	0
T50	0	67	0	0
T67	0	32	0	0
T102	0	10	0	0
T106	0	264	0	0
T112	0	77	0	0
T136	0	20	0	0
T138	0	15	0	0
T139	0	46	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6683	0	0
T1	5875	8	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	68	0	0
T50	0	73	0	0
T67	0	43	0	0
T102	0	14	0	0
T106	0	279	0	0
T112	0	70	0	0
T136	0	10	0	0
T137	0	1	0	0
T138	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6594	0	0
T1	5875	10	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	84	0	0
T50	0	64	0	0
T67	0	30	0	0
T102	0	28	0	0
T106	0	236	0	0
T112	0	46	0	0
T136	0	17	0	0
T137	0	13	0	0
T138	0	5	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6648	0	0
T1	5875	16	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	81	0	0
T50	0	71	0	0
T67	0	48	0	0
T102	0	29	0	0
T106	0	249	0	0
T112	0	45	0	0
T136	0	4	0	0
T137	0	6	0	0
T138	0	9	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11865567	6958	0	0
T1	5875	7	0	0
T2	3527	0	0	0
T3	3858	0	0	0
T4	4029	0	0	0
T5	16833	0	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	0	0	0
T41	0	81	0	0
T50	0	53	0	0
T67	0	36	0	0
T102	0	26	0	0
T106	0	331	0	0
T112	0	74	0	0
T136	0	27	0	0
T137	0	4	0	0
T138	0	4	0	0