Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

32                      
33         1/1            always_comb reset_or_disable = !rst_slow_ni || disable_sva;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	10985983	12527	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	10985983	115843	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	10985983	6504782	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	10985983	185480	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	10985983	12527	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	10985983	115843	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	10985983	6504782	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	10985983	185480	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	12527	0	0
T1	5875	4	0	0
T2	3527	0	0	0
T3	3858	16	0	0
T4	4029	4	0	0
T5	16833	29	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	4	0	0
T11	0	4	0	0
T13	0	12	0	0
T14	0	78	0	0
T25	0	4	0	0
T26	0	13	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	115843	0	0
T1	5875	38	0	0
T2	3527	0	0	0
T3	3858	144	0	0
T4	4029	38	0	0
T5	16833	270	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	37	0	0
T11	0	37	0	0
T13	0	108	0	0
T14	0	754	0	0
T25	0	37	0	0
T26	0	117	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	6504782	0	0
T1	5875	4952	0	0
T2	3527	935	0	0
T3	3858	3005	0	0
T4	4029	3084	0	0
T5	16833	7252	0	0
T6	6278	645	0	0
T7	7943	7339	0	0
T8	8808	8168	0	0
T9	4746	809	0	0
T10	2773	1822	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	185480	0	0
T1	5875	55	0	0
T2	3527	0	0	0
T3	3858	235	0	0
T4	4029	65	0	0
T5	16833	447	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	53	0	0
T11	0	69	0	0
T13	0	175	0	0
T14	0	1180	0	0
T25	0	57	0	0
T26	0	192	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	12527	0	0
T1	5875	4	0	0
T2	3527	0	0	0
T3	3858	16	0	0
T4	4029	4	0	0
T5	16833	29	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	4	0	0
T11	0	4	0	0
T13	0	12	0	0
T14	0	78	0	0
T25	0	4	0	0
T26	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	115843	0	0
T1	5875	38	0	0
T2	3527	0	0	0
T3	3858	144	0	0
T4	4029	38	0	0
T5	16833	270	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	37	0	0
T11	0	37	0	0
T13	0	108	0	0
T14	0	754	0	0
T25	0	37	0	0
T26	0	117	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	6504782	0	0
T1	5875	4952	0	0
T2	3527	935	0	0
T3	3858	3005	0	0
T4	4029	3084	0	0
T5	16833	7252	0	0
T6	6278	645	0	0
T7	7943	7339	0	0
T8	8808	8168	0	0
T9	4746	809	0	0
T10	2773	1822	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10985983	185480	0	0
T1	5875	55	0	0
T2	3527	0	0	0
T3	3858	235	0	0
T4	4029	65	0	0
T5	16833	447	0	0
T6	6278	0	0	0
T7	7943	0	0	0
T8	8808	0	0	0
T9	4746	0	0	0
T10	2773	53	0	0
T11	0	69	0	0
T13	0	175	0	0
T14	0	1180	0	0
T25	0	57	0	0
T26	0	192	0	0