Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	588981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

353177

1

T1

144

T3

124

T4

76

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	501542	1			T1	186		T2	1		T3	144
values[0x0]	220215	1			T1	98		T3	85		T4	54
values[0x1]	220401	1			T1	95		T3	65		T4	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	494087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

448071

1

T1

175

T2

1

T3

151

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3481	1			T3	1		T5	14		T8	1
valid_sources[0x01]	3823	1			T4	2		T5	16		T14	10
valid_sources[0x02]	2846	1			T3	1		T4	2		T5	9
valid_sources[0x03]	3250	1			T3	2		T5	9		T10	6
valid_sources[0x04]	3121	1			T3	1		T4	1		T5	10
valid_sources[0x05]	3259	1			T1	5		T3	1		T4	4
valid_sources[0x06]	3955	1			T4	4		T5	8		T10	3
valid_sources[0x07]	4674	1			T3	1		T4	1		T5	13
valid_sources[0x08]	2973	1			T3	1		T5	4		T14	6
valid_sources[0x09]	4731	1			T3	1		T5	11		T10	3
valid_sources[0x0a]	3728	1			T3	3		T5	8		T10	1
valid_sources[0x0b]	3555	1			T5	9		T10	1		T14	9
valid_sources[0x0c]	5462	1			T5	16		T14	12		T67	3
valid_sources[0x0d]	2989	1			T3	1		T5	14		T12	17
valid_sources[0x0e]	3275	1			T3	5		T5	6		T13	2
valid_sources[0x0f]	3207	1			T3	7		T5	11		T11	3
valid_sources[0x10]	3692	1			T1	6		T4	1		T5	6
valid_sources[0x11]	3727	1			T3	1		T5	9		T8	3
valid_sources[0x12]	4658	1			T1	5		T3	1		T5	12
valid_sources[0x13]	3886	1			T3	3		T5	17		T10	1
valid_sources[0x14]	2875	1			T4	6		T5	7		T10	2
valid_sources[0x15]	5078	1			T1	15		T3	2		T5	11
valid_sources[0x16]	2999	1			T5	14		T11	2		T12	3
valid_sources[0x17]	3189	1			T3	1		T5	12		T12	6
valid_sources[0x18]	3201	1			T3	1		T5	7		T8	1
valid_sources[0x19]	3503	1			T3	1		T5	7		T11	2
valid_sources[0x1a]	3832	1			T3	1		T5	10		T10	1
valid_sources[0x1b]	3979	1			T3	2		T5	7		T10	1
valid_sources[0x1c]	3245	1			T3	1		T5	11		T10	3
valid_sources[0x1d]	3960	1			T5	10		T10	2		T12	4
valid_sources[0x1e]	3212	1			T3	2		T5	11		T14	15
valid_sources[0x1f]	3419	1			T5	16		T10	5		T14	16
valid_sources[0x20]	3796	1			T3	1		T4	2		T5	9
valid_sources[0x21]	3056	1			T3	1		T4	1		T5	11
valid_sources[0x22]	3855	1			T5	9		T12	3		T14	16
valid_sources[0x23]	3695	1			T5	15		T14	12		T67	7
valid_sources[0x24]	7432	1			T3	1		T4	2		T5	8
valid_sources[0x25]	3366	1			T5	11		T10	1		T14	13
valid_sources[0x26]	4111	1			T3	1		T5	17		T10	1
valid_sources[0x27]	3527	1			T3	4		T4	1		T5	13
valid_sources[0x28]	4562	1			T3	1		T5	11		T10	2
valid_sources[0x29]	3263	1			T3	2		T5	10		T14	12
valid_sources[0x2a]	3634	1			T5	15		T11	2		T12	5
valid_sources[0x2b]	4229	1			T1	7		T4	1		T5	11
valid_sources[0x2c]	3860	1			T3	4		T4	1		T5	8
valid_sources[0x2d]	3756	1			T1	5		T3	1		T4	1
valid_sources[0x2e]	4428	1			T3	1		T4	4		T5	6
valid_sources[0x2f]	3571	1			T3	1		T5	6		T11	1
valid_sources[0x30]	7162	1			T4	1		T5	12		T10	2
valid_sources[0x31]	3293	1			T3	2		T5	13		T11	1
valid_sources[0x32]	3805	1			T5	9		T10	4		T14	11
valid_sources[0x33]	3808	1			T3	1		T4	10		T5	16
valid_sources[0x34]	3390	1			T3	1		T5	10		T10	2
valid_sources[0x35]	3002	1			T3	1		T4	4		T5	12
valid_sources[0x36]	3289	1			T3	4		T5	12		T11	2
valid_sources[0x37]	4366	1			T4	3		T5	15		T12	2
valid_sources[0x38]	3469	1			T1	31		T3	3		T4	2
valid_sources[0x39]	3124	1			T3	1		T4	2		T5	11
valid_sources[0x3a]	2641	1			T4	1		T5	5		T10	1
valid_sources[0x3b]	3350	1			T4	1		T5	10		T13	1
valid_sources[0x3c]	3596	1			T3	1		T4	1		T5	9
valid_sources[0x3d]	3283	1			T1	3		T3	1		T4	2
valid_sources[0x3e]	3318	1			T5	10		T10	3		T14	10
valid_sources[0x3f]	3154	1			T3	2		T5	9		T8	1
valid_sources[0x40]	4073	1			T1	7		T3	4		T5	11
valid_sources[0x41]	2974	1			T1	17		T3	1		T4	4
valid_sources[0x42]	3342	1			T5	18		T11	4		T14	10
valid_sources[0x43]	2990	1			T1	13		T3	2		T5	8
valid_sources[0x44]	2989	1			T5	11		T10	2		T14	19
valid_sources[0x45]	3530	1			T3	2		T4	3		T5	13
valid_sources[0x46]	3623	1			T3	2		T5	12		T11	2
valid_sources[0x47]	4083	1			T4	3		T5	12		T14	16
valid_sources[0x48]	4075	1			T4	2		T5	12		T10	5
valid_sources[0x49]	3055	1			T3	1		T5	11		T10	1
valid_sources[0x4a]	3137	1			T5	10		T11	2		T14	10
valid_sources[0x4b]	2948	1			T3	1		T5	11		T10	2
valid_sources[0x4c]	3551	1			T3	2		T5	10		T10	1
valid_sources[0x4d]	3946	1			T3	1		T5	12		T10	5
valid_sources[0x4e]	2962	1			T5	5		T8	3		T10	4
valid_sources[0x4f]	3791	1			T1	2		T3	1		T4	2
valid_sources[0x50]	3561	1			T5	14		T14	4		T26	1
valid_sources[0x51]	3001	1			T5	13		T10	7		T12	20
valid_sources[0x52]	5012	1			T3	3		T5	11		T11	2
valid_sources[0x53]	4101	1			T3	4		T4	1		T5	8
valid_sources[0x54]	4250	1			T3	1		T5	9		T14	17
valid_sources[0x55]	3559	1			T1	3		T5	8		T10	4
valid_sources[0x56]	3304	1			T3	1		T5	17		T10	3
valid_sources[0x57]	4167	1			T3	1		T4	2		T5	16
valid_sources[0x58]	3499	1			T1	5		T3	3		T4	2
valid_sources[0x59]	3496	1			T3	2		T5	12		T10	7
valid_sources[0x5a]	3212	1			T3	3		T4	2		T5	4
valid_sources[0x5b]	3447	1			T3	2		T5	13		T11	1
valid_sources[0x5c]	3714	1			T5	6		T11	1		T12	21
valid_sources[0x5d]	3598	1			T3	1		T4	6		T5	9
valid_sources[0x5e]	3418	1			T3	2		T5	8		T10	1
valid_sources[0x5f]	3524	1			T5	13		T10	5		T11	2
valid_sources[0x60]	3094	1			T3	1		T5	9		T10	3
valid_sources[0x61]	4012	1			T3	2		T4	4		T5	6
valid_sources[0x62]	3327	1			T3	2		T5	14		T13	4
valid_sources[0x63]	4813	1			T1	16		T3	1		T5	10
valid_sources[0x64]	3720	1			T1	1		T3	1		T4	4
valid_sources[0x65]	3180	1			T1	23		T3	1		T5	9
valid_sources[0x66]	3077	1			T3	3		T5	10		T10	1
valid_sources[0x67]	4410	1			T5	10		T14	13		T67	3
valid_sources[0x68]	3013	1			T3	1		T5	13		T10	2
valid_sources[0x69]	3580	1			T3	1		T5	8		T8	1
valid_sources[0x6a]	3024	1			T5	12		T11	1		T14	9
valid_sources[0x6b]	2949	1			T5	14		T11	1		T14	20
valid_sources[0x6c]	3331	1			T5	16		T10	2		T14	11
valid_sources[0x6d]	3288	1			T3	1		T5	7		T10	5
valid_sources[0x6e]	4164	1			T3	1		T4	1		T5	8
valid_sources[0x6f]	2972	1			T3	2		T5	5		T10	1
valid_sources[0x70]	4435	1			T3	1		T5	8		T11	1
valid_sources[0x71]	3087	1			T5	9		T14	6		T67	7
valid_sources[0x72]	3713	1			T5	10		T11	1		T14	14
valid_sources[0x73]	3336	1			T4	6		T5	11		T11	1
valid_sources[0x74]	4000	1			T5	15		T10	1		T14	13
valid_sources[0x75]	6198	1			T1	6		T3	1		T5	10
valid_sources[0x76]	3284	1			T4	5		T5	10		T10	3
valid_sources[0x77]	4197	1			T3	2		T4	2		T5	13
valid_sources[0x78]	3222	1			T3	1		T5	5		T10	7
valid_sources[0x79]	2907	1			T3	1		T5	11		T8	1
valid_sources[0x7a]	2941	1			T4	1		T5	14		T8	3
valid_sources[0x7b]	3925	1			T4	2		T5	8		T7	936
valid_sources[0x7c]	3346	1			T5	8		T13	13		T14	8
valid_sources[0x7d]	3819	1			T3	2		T4	2		T5	13
valid_sources[0x7e]	3775	1			T3	1		T5	12		T10	1
valid_sources[0x7f]	4526	1			T5	12		T11	1		T14	15
valid_sources[0x80]	3779	1			T5	15		T10	9		T13	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235125

1

T1

96

T3

77

T4

44

values[0x0]

all_enables

biggest_size

76872

1

T1

36

T3

27

T4

23

values[0x1]

all_enables

biggest_size

41180

1

T1

12

T3

20

T4

9