Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/rstmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

376602

1

T1

148

T3

140

T4

77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	536655	1			T1	186		T2	1		T3	180
values[0x0]	233838	1			T1	105		T3	108		T4	61
values[0x1]	233873	1			T1	88		T3	78		T4	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	526367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

477999

1

T1

192

T3

173

T4

98

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4001	1			T1	9		T3	3		T9	1
valid_sources[0x01]	3130	1			T9	2		T12	3		T60	5
valid_sources[0x02]	3542	1			T9	1		T60	7		T13	10
valid_sources[0x03]	3468	1			T9	1		T60	4		T56	1
valid_sources[0x04]	3422	1			T3	10		T9	3		T12	2
valid_sources[0x05]	3346	1			T11	2		T60	3		T13	10
valid_sources[0x06]	3738	1			T7	8		T9	1		T60	6
valid_sources[0x07]	3525	1			T3	1		T9	1		T60	4
valid_sources[0x08]	3513	1			T1	5		T9	5		T11	2
valid_sources[0x09]	3210	1			T1	1		T9	1		T60	4
valid_sources[0x0a]	5012	1			T1	7		T8	283		T9	1
valid_sources[0x0b]	4082	1			T3	2		T9	5		T12	6
valid_sources[0x0c]	5085	1			T3	9		T9	4		T60	5
valid_sources[0x0d]	3982	1			T5	744		T9	1		T12	9
valid_sources[0x0e]	4097	1			T11	1		T60	5		T13	3
valid_sources[0x0f]	3340	1			T3	2		T9	1		T11	1
valid_sources[0x10]	3742	1			T11	1		T60	4		T13	9
valid_sources[0x11]	4649	1			T3	5		T9	1		T60	3
valid_sources[0x12]	3713	1			T3	4		T60	5		T13	13
valid_sources[0x13]	4148	1			T9	2		T12	6		T60	5
valid_sources[0x14]	4239	1			T8	70		T60	5		T13	11
valid_sources[0x15]	3464	1			T1	2		T9	1		T60	5
valid_sources[0x16]	2983	1			T9	6		T60	2		T13	13
valid_sources[0x17]	4166	1			T1	10		T9	2		T12	2
valid_sources[0x18]	3499	1			T1	2		T60	6		T13	9
valid_sources[0x19]	3765	1			T9	1		T60	5		T13	18
valid_sources[0x1a]	3224	1			T9	2		T60	3		T56	2
valid_sources[0x1b]	3921	1			T10	1		T60	3		T56	3
valid_sources[0x1c]	3208	1			T1	5		T3	8		T9	4
valid_sources[0x1d]	3240	1			T1	7		T60	6		T13	6
valid_sources[0x1e]	3411	1			T1	1		T9	2		T60	4
valid_sources[0x1f]	3509	1			T1	2		T9	1		T60	2
valid_sources[0x20]	3241	1			T3	3		T9	2		T11	1
valid_sources[0x21]	3991	1			T60	5		T13	10		T22	5
valid_sources[0x22]	3603	1			T1	2		T9	1		T60	4
valid_sources[0x23]	3696	1			T1	3		T11	1		T60	5
valid_sources[0x24]	3877	1			T9	3		T11	1		T12	4
valid_sources[0x25]	4179	1			T1	4		T3	3		T8	182
valid_sources[0x26]	3864	1			T1	4		T9	2		T11	1
valid_sources[0x27]	3380	1			T3	2		T9	2		T13	19
valid_sources[0x28]	3665	1			T1	3		T9	3		T60	5
valid_sources[0x29]	4020	1			T3	2		T9	1		T60	9
valid_sources[0x2a]	4061	1			T1	2		T9	2		T12	2
valid_sources[0x2b]	3376	1			T9	4		T12	5		T60	10
valid_sources[0x2c]	3708	1			T3	2		T9	1		T60	8
valid_sources[0x2d]	3406	1			T60	2		T13	2		T22	5
valid_sources[0x2e]	4335	1			T9	1		T60	3		T13	9
valid_sources[0x2f]	3209	1			T9	1		T60	3		T13	20
valid_sources[0x30]	4586	1			T1	7		T9	3		T60	7
valid_sources[0x31]	3607	1			T3	1		T9	1		T60	2
valid_sources[0x32]	6493	1			T60	5		T13	14		T22	6
valid_sources[0x33]	3419	1			T3	3		T12	1		T60	5
valid_sources[0x34]	3684	1			T1	10		T3	5		T9	4
valid_sources[0x35]	3439	1			T9	1		T11	1		T60	5
valid_sources[0x36]	3767	1			T3	3		T9	2		T11	3
valid_sources[0x37]	4011	1			T3	9		T9	2		T11	4
valid_sources[0x38]	3457	1			T1	5		T12	3		T60	1
valid_sources[0x39]	3878	1			T8	592		T60	4		T13	8
valid_sources[0x3a]	4060	1			T3	3		T9	1		T60	4
valid_sources[0x3b]	6982	1			T3	4		T9	4		T11	2
valid_sources[0x3c]	3719	1			T3	16		T9	2		T60	5
valid_sources[0x3d]	4178	1			T9	2		T60	2		T13	7
valid_sources[0x3e]	3447	1			T3	4		T9	3		T60	2
valid_sources[0x3f]	2996	1			T9	3		T11	1		T60	5
valid_sources[0x40]	3586	1			T9	1		T11	1		T12	1
valid_sources[0x41]	3376	1			T3	2		T9	1		T60	9
valid_sources[0x42]	3223	1			T3	4		T9	1		T60	3
valid_sources[0x43]	4246	1			T1	11		T12	7		T60	5
valid_sources[0x44]	3218	1			T1	2		T9	2		T11	1
valid_sources[0x45]	3091	1			T1	5		T3	1		T8	63
valid_sources[0x46]	3806	1			T1	2		T3	3		T9	2
valid_sources[0x47]	4003	1			T9	1		T12	9		T60	3
valid_sources[0x48]	6745	1			T3	4		T60	3		T13	5
valid_sources[0x49]	3301	1			T9	2		T60	3		T13	15
valid_sources[0x4a]	3604	1			T1	5		T3	2		T8	240
valid_sources[0x4b]	3238	1			T60	3		T13	16		T22	15
valid_sources[0x4c]	3612	1			T60	3		T13	20		T51	1
valid_sources[0x4d]	3209	1			T3	1		T9	1		T60	5
valid_sources[0x4e]	3087	1			T9	2		T11	2		T60	7
valid_sources[0x4f]	3266	1			T3	4		T60	3		T13	11
valid_sources[0x50]	3771	1			T1	1		T12	3		T60	5
valid_sources[0x51]	3449	1			T1	3		T60	2		T13	16
valid_sources[0x52]	3137	1			T3	3		T9	2		T11	1
valid_sources[0x53]	3739	1			T1	6		T3	1		T9	3
valid_sources[0x54]	3837	1			T1	1		T9	1		T12	6
valid_sources[0x55]	4511	1			T1	4		T3	1		T9	4
valid_sources[0x56]	3328	1			T1	2		T11	1		T12	14
valid_sources[0x57]	3634	1			T3	1		T11	1		T12	9
valid_sources[0x58]	3316	1			T9	1		T60	1		T13	10
valid_sources[0x59]	3999	1			T3	3		T9	4		T60	1
valid_sources[0x5a]	3761	1			T9	5		T60	5		T13	8
valid_sources[0x5b]	3295	1			T60	2		T13	8		T22	3
valid_sources[0x5c]	3424	1			T60	5		T13	16		T22	9
valid_sources[0x5d]	3709	1			T9	2		T11	1		T60	1
valid_sources[0x5e]	4585	1			T9	2		T60	4		T13	7
valid_sources[0x5f]	4352	1			T8	70		T9	3		T60	2
valid_sources[0x60]	3492	1			T3	3		T12	1		T60	6
valid_sources[0x61]	3222	1			T1	1		T11	6		T60	7
valid_sources[0x62]	6395	1			T1	6		T9	1		T11	1
valid_sources[0x63]	3534	1			T9	2		T12	2		T60	5
valid_sources[0x64]	4204	1			T9	5		T60	6		T13	10
valid_sources[0x65]	3079	1			T9	1		T60	4		T13	4
valid_sources[0x66]	3010	1			T3	6		T60	6		T13	6
valid_sources[0x67]	3406	1			T9	2		T60	4		T13	24
valid_sources[0x68]	3287	1			T1	13		T9	2		T60	4
valid_sources[0x69]	3273	1			T9	4		T60	10		T13	8
valid_sources[0x6a]	4452	1			T3	6		T9	2		T12	5
valid_sources[0x6b]	3990	1			T3	9		T12	7		T60	3
valid_sources[0x6c]	4286	1			T1	5		T60	4		T13	7
valid_sources[0x6d]	3632	1			T1	2		T3	7		T11	1
valid_sources[0x6e]	3451	1			T12	1		T60	8		T13	9
valid_sources[0x6f]	3312	1			T3	8		T13	16		T22	5
valid_sources[0x70]	3483	1			T1	3		T9	1		T60	9
valid_sources[0x71]	3323	1			T3	13		T9	3		T11	1
valid_sources[0x72]	3569	1			T60	3		T13	8		T50	1
valid_sources[0x73]	3925	1			T1	5		T9	8		T60	3
valid_sources[0x74]	3954	1			T9	1		T12	1		T60	5
valid_sources[0x75]	4049	1			T9	1		T11	2		T60	4
valid_sources[0x76]	4918	1			T1	1		T3	7		T9	2
valid_sources[0x77]	3821	1			T3	2		T9	1		T11	1
valid_sources[0x78]	3295	1			T1	6		T3	1		T9	5
valid_sources[0x79]	3617	1			T3	6		T12	5		T60	3
valid_sources[0x7a]	3828	1			T60	7		T13	14		T22	6
valid_sources[0x7b]	3234	1			T9	1		T60	6		T13	17
valid_sources[0x7c]	3569	1			T3	2		T11	1		T60	5
valid_sources[0x7d]	3753	1			T1	3		T9	1		T60	5
valid_sources[0x7e]	3557	1			T1	9		T9	2		T60	6
valid_sources[0x7f]	3392	1			T60	6		T13	11		T22	7
valid_sources[0x80]	3479	1			T9	2		T60	5		T13	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

251478

1

T1

94

T3

88

T4

43

values[0x0]

all_enables

biggest_size

81704

1

T1

41

T3

35

T4

26

values[0x1]

all_enables

biggest_size

43420

1

T1

13

T3

17

T4

8